1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #define _BIOS_PARSER_2_ 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 #include "atomfirmwareid.h" 33 34 #include "dc_bios_types.h" 35 #include "include/grph_object_ctrl_defs.h" 36 #include "include/bios_parser_interface.h" 37 #include "include/i2caux_interface.h" 38 #include "include/logger_interface.h" 39 40 #include "command_table2.h" 41 42 #include "bios_parser_helper.h" 43 #include "command_table_helper2.h" 44 #include "bios_parser2.h" 45 #include "bios_parser_types_internal2.h" 46 #include "bios_parser_interface.h" 47 48 #define LAST_RECORD_TYPE 0xff 49 50 51 struct i2c_id_config_access { 52 uint8_t bfI2C_LineMux:4; 53 uint8_t bfHW_EngineID:3; 54 uint8_t bfHW_Capable:1; 55 uint8_t ucAccess; 56 }; 57 58 static enum object_type object_type_from_bios_object_id( 59 uint32_t bios_object_id); 60 61 static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id); 62 63 static struct graphics_object_id object_id_from_bios_object_id( 64 uint32_t bios_object_id); 65 66 static uint32_t id_from_bios_object_id(enum object_type type, 67 uint32_t bios_object_id); 68 69 static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id); 70 71 static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id); 72 73 static enum connector_id connector_id_from_bios_object_id( 74 uint32_t bios_object_id); 75 76 static enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id); 77 78 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 79 struct atom_i2c_record *record, 80 struct graphics_object_i2c_info *info); 81 82 static enum bp_result bios_parser_get_firmware_info( 83 struct dc_bios *dcb, 84 struct dc_firmware_info *info); 85 86 static enum bp_result bios_parser_get_encoder_cap_info( 87 struct dc_bios *dcb, 88 struct graphics_object_id object_id, 89 struct bp_encoder_cap_info *info); 90 91 static enum bp_result get_firmware_info_v3_1( 92 struct bios_parser *bp, 93 struct dc_firmware_info *info); 94 95 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 96 struct atom_display_object_path_v2 *object); 97 98 static struct atom_encoder_caps_record *get_encoder_cap_record( 99 struct bios_parser *bp, 100 struct atom_display_object_path_v2 *object); 101 102 #define BIOS_IMAGE_SIZE_OFFSET 2 103 #define BIOS_IMAGE_SIZE_UNIT 512 104 105 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 106 107 108 static void destruct(struct bios_parser *bp) 109 { 110 if (bp->base.bios_local_image) 111 dm_free(bp->base.bios_local_image); 112 113 if (bp->base.integrated_info) 114 dm_free(bp->base.integrated_info); 115 } 116 117 static void firmware_parser_destroy(struct dc_bios **dcb) 118 { 119 struct bios_parser *bp = BP_FROM_DCB(*dcb); 120 121 if (!bp) { 122 BREAK_TO_DEBUGGER(); 123 return; 124 } 125 126 destruct(bp); 127 128 dm_free(bp); 129 *dcb = NULL; 130 } 131 132 static void get_atom_data_table_revision( 133 struct atom_common_table_header *atom_data_tbl, 134 struct atom_data_revision *tbl_revision) 135 { 136 if (!tbl_revision) 137 return; 138 139 /* initialize the revision to 0 which is invalid revision */ 140 tbl_revision->major = 0; 141 tbl_revision->minor = 0; 142 143 if (!atom_data_tbl) 144 return; 145 146 tbl_revision->major = 147 (uint32_t) atom_data_tbl->format_revision & 0x3f; 148 tbl_revision->minor = 149 (uint32_t) atom_data_tbl->content_revision & 0x3f; 150 } 151 152 static struct graphics_object_id object_id_from_bios_object_id( 153 uint32_t bios_object_id) 154 { 155 enum object_type type; 156 enum object_enum_id enum_id; 157 struct graphics_object_id go_id = { 0 }; 158 159 type = object_type_from_bios_object_id(bios_object_id); 160 161 if (type == OBJECT_TYPE_UNKNOWN) 162 return go_id; 163 164 enum_id = enum_id_from_bios_object_id(bios_object_id); 165 166 if (enum_id == ENUM_ID_UNKNOWN) 167 return go_id; 168 169 go_id = dal_graphics_object_id_init( 170 id_from_bios_object_id(type, bios_object_id), 171 enum_id, type); 172 173 return go_id; 174 } 175 176 static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id) 177 { 178 uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK) 179 >> OBJECT_TYPE_SHIFT; 180 enum object_type object_type; 181 182 switch (bios_object_type) { 183 case GRAPH_OBJECT_TYPE_GPU: 184 object_type = OBJECT_TYPE_GPU; 185 break; 186 case GRAPH_OBJECT_TYPE_ENCODER: 187 object_type = OBJECT_TYPE_ENCODER; 188 break; 189 case GRAPH_OBJECT_TYPE_CONNECTOR: 190 object_type = OBJECT_TYPE_CONNECTOR; 191 break; 192 case GRAPH_OBJECT_TYPE_ROUTER: 193 object_type = OBJECT_TYPE_ROUTER; 194 break; 195 case GRAPH_OBJECT_TYPE_GENERIC: 196 object_type = OBJECT_TYPE_GENERIC; 197 break; 198 default: 199 object_type = OBJECT_TYPE_UNKNOWN; 200 break; 201 } 202 203 return object_type; 204 } 205 206 static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id) 207 { 208 uint32_t bios_enum_id = 209 (bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 210 enum object_enum_id id; 211 212 switch (bios_enum_id) { 213 case GRAPH_OBJECT_ENUM_ID1: 214 id = ENUM_ID_1; 215 break; 216 case GRAPH_OBJECT_ENUM_ID2: 217 id = ENUM_ID_2; 218 break; 219 case GRAPH_OBJECT_ENUM_ID3: 220 id = ENUM_ID_3; 221 break; 222 case GRAPH_OBJECT_ENUM_ID4: 223 id = ENUM_ID_4; 224 break; 225 case GRAPH_OBJECT_ENUM_ID5: 226 id = ENUM_ID_5; 227 break; 228 case GRAPH_OBJECT_ENUM_ID6: 229 id = ENUM_ID_6; 230 break; 231 case GRAPH_OBJECT_ENUM_ID7: 232 id = ENUM_ID_7; 233 break; 234 default: 235 id = ENUM_ID_UNKNOWN; 236 break; 237 } 238 239 return id; 240 } 241 242 static uint32_t id_from_bios_object_id(enum object_type type, 243 uint32_t bios_object_id) 244 { 245 switch (type) { 246 case OBJECT_TYPE_GPU: 247 return gpu_id_from_bios_object_id(bios_object_id); 248 case OBJECT_TYPE_ENCODER: 249 return (uint32_t)encoder_id_from_bios_object_id(bios_object_id); 250 case OBJECT_TYPE_CONNECTOR: 251 return (uint32_t)connector_id_from_bios_object_id( 252 bios_object_id); 253 case OBJECT_TYPE_GENERIC: 254 return generic_id_from_bios_object_id(bios_object_id); 255 default: 256 return 0; 257 } 258 } 259 260 uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id) 261 { 262 return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 263 } 264 265 static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id) 266 { 267 uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id); 268 enum encoder_id id; 269 270 switch (bios_encoder_id) { 271 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 272 id = ENCODER_ID_INTERNAL_LVDS; 273 break; 274 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 275 id = ENCODER_ID_INTERNAL_TMDS1; 276 break; 277 case ENCODER_OBJECT_ID_INTERNAL_TMDS2: 278 id = ENCODER_ID_INTERNAL_TMDS2; 279 break; 280 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 281 id = ENCODER_ID_INTERNAL_DAC1; 282 break; 283 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 284 id = ENCODER_ID_INTERNAL_DAC2; 285 break; 286 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 287 id = ENCODER_ID_INTERNAL_LVTM1; 288 break; 289 case ENCODER_OBJECT_ID_HDMI_INTERNAL: 290 id = ENCODER_ID_INTERNAL_HDMI; 291 break; 292 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 293 id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1; 294 break; 295 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 296 id = ENCODER_ID_INTERNAL_KLDSCP_DAC1; 297 break; 298 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 299 id = ENCODER_ID_INTERNAL_KLDSCP_DAC2; 300 break; 301 case ENCODER_OBJECT_ID_MVPU_FPGA: 302 id = ENCODER_ID_EXTERNAL_MVPU_FPGA; 303 break; 304 case ENCODER_OBJECT_ID_INTERNAL_DDI: 305 id = ENCODER_ID_INTERNAL_DDI; 306 break; 307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 308 id = ENCODER_ID_INTERNAL_UNIPHY; 309 break; 310 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 311 id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA; 312 break; 313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 314 id = ENCODER_ID_INTERNAL_UNIPHY1; 315 break; 316 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 317 id = ENCODER_ID_INTERNAL_UNIPHY2; 318 break; 319 case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */ 320 id = ENCODER_ID_EXTERNAL_NUTMEG; 321 break; 322 case ENCODER_OBJECT_ID_TRAVIS: 323 id = ENCODER_ID_EXTERNAL_TRAVIS; 324 break; 325 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 326 id = ENCODER_ID_INTERNAL_UNIPHY3; 327 break; 328 default: 329 id = ENCODER_ID_UNKNOWN; 330 ASSERT(0); 331 break; 332 } 333 334 return id; 335 } 336 337 static enum connector_id connector_id_from_bios_object_id( 338 uint32_t bios_object_id) 339 { 340 uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id); 341 342 enum connector_id id; 343 344 switch (bios_connector_id) { 345 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: 346 id = CONNECTOR_ID_SINGLE_LINK_DVII; 347 break; 348 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: 349 id = CONNECTOR_ID_DUAL_LINK_DVII; 350 break; 351 case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: 352 id = CONNECTOR_ID_SINGLE_LINK_DVID; 353 break; 354 case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: 355 id = CONNECTOR_ID_DUAL_LINK_DVID; 356 break; 357 case CONNECTOR_OBJECT_ID_VGA: 358 id = CONNECTOR_ID_VGA; 359 break; 360 case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: 361 id = CONNECTOR_ID_HDMI_TYPE_A; 362 break; 363 case CONNECTOR_OBJECT_ID_LVDS: 364 id = CONNECTOR_ID_LVDS; 365 break; 366 case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR: 367 id = CONNECTOR_ID_PCIE; 368 break; 369 case CONNECTOR_OBJECT_ID_HARDCODE_DVI: 370 id = CONNECTOR_ID_HARDCODE_DVI; 371 break; 372 case CONNECTOR_OBJECT_ID_DISPLAYPORT: 373 id = CONNECTOR_ID_DISPLAY_PORT; 374 break; 375 case CONNECTOR_OBJECT_ID_eDP: 376 id = CONNECTOR_ID_EDP; 377 break; 378 case CONNECTOR_OBJECT_ID_MXM: 379 id = CONNECTOR_ID_MXM; 380 break; 381 default: 382 id = CONNECTOR_ID_UNKNOWN; 383 break; 384 } 385 386 return id; 387 } 388 389 enum generic_id generic_id_from_bios_object_id(uint32_t bios_object_id) 390 { 391 uint32_t bios_generic_id = gpu_id_from_bios_object_id(bios_object_id); 392 393 enum generic_id id; 394 395 switch (bios_generic_id) { 396 case GENERIC_OBJECT_ID_MXM_OPM: 397 id = GENERIC_ID_MXM_OPM; 398 break; 399 case GENERIC_OBJECT_ID_GLSYNC: 400 id = GENERIC_ID_GLSYNC; 401 break; 402 case GENERIC_OBJECT_ID_STEREO_PIN: 403 id = GENERIC_ID_STEREO; 404 break; 405 default: 406 id = GENERIC_ID_UNKNOWN; 407 break; 408 } 409 410 return id; 411 } 412 413 /* BIOS oject table displaypath is per connector. 414 * There is extra path not for connector. BIOS fill its encoderid as 0 415 */ 416 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 417 { 418 struct bios_parser *bp = BP_FROM_DCB(dcb); 419 unsigned int count = 0; 420 unsigned int i; 421 422 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 423 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 424 count++; 425 } 426 return count; 427 } 428 429 static struct graphics_object_id bios_parser_get_encoder_id( 430 struct dc_bios *dcb, 431 uint32_t i) 432 { 433 struct bios_parser *bp = BP_FROM_DCB(dcb); 434 struct graphics_object_id object_id = dal_graphics_object_id_init( 435 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 436 437 if (bp->object_info_tbl.v1_4->number_of_path > i) 438 object_id = object_id_from_bios_object_id( 439 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 440 441 return object_id; 442 } 443 444 static struct graphics_object_id bios_parser_get_connector_id( 445 struct dc_bios *dcb, 446 uint8_t i) 447 { 448 struct bios_parser *bp = BP_FROM_DCB(dcb); 449 struct graphics_object_id object_id = dal_graphics_object_id_init( 450 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 451 struct object_info_table *tbl = &bp->object_info_tbl; 452 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 453 454 if (v1_4->number_of_path > i) { 455 /* If display_objid is generic object id, the encoderObj 456 * /extencoderobjId should be 0 457 */ 458 if (v1_4->display_path[i].encoderobjid != 0 && 459 v1_4->display_path[i].display_objid != 0) 460 object_id = object_id_from_bios_object_id( 461 v1_4->display_path[i].display_objid); 462 } 463 464 return object_id; 465 } 466 467 468 /* TODO: GetNumberOfSrc*/ 469 470 static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb, 471 struct graphics_object_id id) 472 { 473 /* connector has 1 Dest, encoder has 0 Dest */ 474 switch (id.type) { 475 case OBJECT_TYPE_ENCODER: 476 return 0; 477 case OBJECT_TYPE_CONNECTOR: 478 return 1; 479 default: 480 return 0; 481 } 482 } 483 484 /* removed getSrcObjList, getDestObjList*/ 485 486 487 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 488 struct graphics_object_id object_id, uint32_t index, 489 struct graphics_object_id *src_object_id) 490 { 491 struct bios_parser *bp = BP_FROM_DCB(dcb); 492 unsigned int i; 493 enum bp_result bp_result = BP_RESULT_BADINPUT; 494 struct graphics_object_id obj_id = {0}; 495 struct object_info_table *tbl = &bp->object_info_tbl; 496 497 if (!src_object_id) 498 return bp_result; 499 500 switch (object_id.type) { 501 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 502 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 503 */ 504 case OBJECT_TYPE_ENCODER: 505 /* TODO: since num of src must be less than 2. 506 * If found in for loop, should break. 507 * DAL2 implementation may be changed too 508 */ 509 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 510 obj_id = object_id_from_bios_object_id( 511 tbl->v1_4->display_path[i].encoderobjid); 512 if (object_id.type == obj_id.type && 513 object_id.id == obj_id.id && 514 object_id.enum_id == 515 obj_id.enum_id) { 516 *src_object_id = 517 object_id_from_bios_object_id(0x1100); 518 /* break; */ 519 } 520 } 521 bp_result = BP_RESULT_OK; 522 break; 523 case OBJECT_TYPE_CONNECTOR: 524 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 525 obj_id = object_id_from_bios_object_id( 526 tbl->v1_4->display_path[i].display_objid); 527 528 if (object_id.type == obj_id.type && 529 object_id.id == obj_id.id && 530 object_id.enum_id == obj_id.enum_id) { 531 *src_object_id = 532 object_id_from_bios_object_id( 533 tbl->v1_4->display_path[i].encoderobjid); 534 /* break; */ 535 } 536 } 537 bp_result = BP_RESULT_OK; 538 break; 539 default: 540 break; 541 } 542 543 return bp_result; 544 } 545 546 static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb, 547 struct graphics_object_id object_id, uint32_t index, 548 struct graphics_object_id *dest_object_id) 549 { 550 struct bios_parser *bp = BP_FROM_DCB(dcb); 551 unsigned int i; 552 enum bp_result bp_result = BP_RESULT_BADINPUT; 553 struct graphics_object_id obj_id = {0}; 554 struct object_info_table *tbl = &bp->object_info_tbl; 555 556 if (!dest_object_id) 557 return BP_RESULT_BADINPUT; 558 559 switch (object_id.type) { 560 case OBJECT_TYPE_ENCODER: 561 /* TODO: since num of src must be less than 2. 562 * If found in for loop, should break. 563 * DAL2 implementation may be changed too 564 */ 565 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 566 obj_id = object_id_from_bios_object_id( 567 tbl->v1_4->display_path[i].encoderobjid); 568 if (object_id.type == obj_id.type && 569 object_id.id == obj_id.id && 570 object_id.enum_id == 571 obj_id.enum_id) { 572 *dest_object_id = 573 object_id_from_bios_object_id( 574 tbl->v1_4->display_path[i].display_objid); 575 /* break; */ 576 } 577 } 578 bp_result = BP_RESULT_OK; 579 break; 580 default: 581 break; 582 } 583 584 return bp_result; 585 } 586 587 588 /* from graphics_object_id, find display path which includes the object_id */ 589 static struct atom_display_object_path_v2 *get_bios_object( 590 struct bios_parser *bp, 591 struct graphics_object_id id) 592 { 593 unsigned int i; 594 struct graphics_object_id obj_id = {0}; 595 596 switch (id.type) { 597 case OBJECT_TYPE_ENCODER: 598 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 599 obj_id = object_id_from_bios_object_id( 600 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 601 if (id.type == obj_id.type && 602 id.id == obj_id.id && 603 id.enum_id == obj_id.enum_id) 604 return 605 &bp->object_info_tbl.v1_4->display_path[i]; 606 } 607 case OBJECT_TYPE_CONNECTOR: 608 case OBJECT_TYPE_GENERIC: 609 /* Both Generic and Connector Object ID 610 * will be stored on display_objid 611 */ 612 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 613 obj_id = object_id_from_bios_object_id( 614 bp->object_info_tbl.v1_4->display_path[i].display_objid 615 ); 616 if (id.type == obj_id.type && 617 id.id == obj_id.id && 618 id.enum_id == obj_id.enum_id) 619 return 620 &bp->object_info_tbl.v1_4->display_path[i]; 621 } 622 default: 623 return NULL; 624 } 625 } 626 627 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 628 struct graphics_object_id id, 629 struct graphics_object_i2c_info *info) 630 { 631 uint32_t offset; 632 struct atom_display_object_path_v2 *object; 633 struct atom_common_record_header *header; 634 struct atom_i2c_record *record; 635 struct bios_parser *bp = BP_FROM_DCB(dcb); 636 637 if (!info) 638 return BP_RESULT_BADINPUT; 639 640 object = get_bios_object(bp, id); 641 642 if (!object) 643 return BP_RESULT_BADINPUT; 644 645 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 646 647 for (;;) { 648 header = GET_IMAGE(struct atom_common_record_header, offset); 649 650 if (!header) 651 return BP_RESULT_BADBIOSTABLE; 652 653 if (header->record_type == LAST_RECORD_TYPE || 654 !header->record_size) 655 break; 656 657 if (header->record_type == ATOM_I2C_RECORD_TYPE 658 && sizeof(struct atom_i2c_record) <= 659 header->record_size) { 660 /* get the I2C info */ 661 record = (struct atom_i2c_record *) header; 662 663 if (get_gpio_i2c_info(bp, record, info) == 664 BP_RESULT_OK) 665 return BP_RESULT_OK; 666 } 667 668 offset += header->record_size; 669 } 670 671 return BP_RESULT_NORECORD; 672 } 673 674 static enum bp_result get_gpio_i2c_info( 675 struct bios_parser *bp, 676 struct atom_i2c_record *record, 677 struct graphics_object_i2c_info *info) 678 { 679 struct atom_gpio_pin_lut_v2_1 *header; 680 uint32_t count = 0; 681 unsigned int table_index = 0; 682 683 if (!info) 684 return BP_RESULT_BADINPUT; 685 686 /* get the GPIO_I2C info */ 687 if (!DATA_TABLES(gpio_pin_lut)) 688 return BP_RESULT_BADBIOSTABLE; 689 690 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 691 DATA_TABLES(gpio_pin_lut)); 692 if (!header) 693 return BP_RESULT_BADBIOSTABLE; 694 695 if (sizeof(struct atom_common_table_header) + 696 sizeof(struct atom_gpio_pin_assignment) > 697 le16_to_cpu(header->table_header.structuresize)) 698 return BP_RESULT_BADBIOSTABLE; 699 700 /* TODO: is version change? */ 701 if (header->table_header.content_revision != 1) 702 return BP_RESULT_UNSUPPORTED; 703 704 /* get data count */ 705 count = (le16_to_cpu(header->table_header.structuresize) 706 - sizeof(struct atom_common_table_header)) 707 / sizeof(struct atom_gpio_pin_assignment); 708 709 table_index = record->i2c_id & I2C_HW_LANE_MUX; 710 711 if (count < table_index) { 712 bool find_valid = false; 713 714 for (table_index = 0; table_index < count; table_index++) { 715 if (((record->i2c_id & I2C_HW_CAP) == ( 716 header->gpio_pin[table_index].gpio_id & 717 I2C_HW_CAP)) && 718 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 719 (header->gpio_pin[table_index].gpio_id & 720 I2C_HW_ENGINE_ID_MASK)) && 721 ((record->i2c_id & I2C_HW_LANE_MUX) == 722 (header->gpio_pin[table_index].gpio_id & 723 I2C_HW_LANE_MUX))) { 724 /* still valid */ 725 find_valid = true; 726 break; 727 } 728 } 729 /* If we don't find the entry that we are looking for then 730 * we will return BP_Result_BadBiosTable. 731 */ 732 if (find_valid == false) 733 return BP_RESULT_BADBIOSTABLE; 734 } 735 736 /* get the GPIO_I2C_INFO */ 737 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 738 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 739 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 740 info->i2c_slave_address = record->i2c_slave_addr; 741 742 /* TODO: check how to get register offset for en, Y, etc. */ 743 info->gpio_info.clk_a_register_index = 744 le16_to_cpu( 745 header->gpio_pin[table_index].data_a_reg_index); 746 info->gpio_info.clk_a_shift = 747 header->gpio_pin[table_index].gpio_bitshift; 748 749 return BP_RESULT_OK; 750 } 751 752 static enum bp_result get_voltage_ddc_info_v4( 753 uint8_t *i2c_line, 754 uint32_t index, 755 struct atom_common_table_header *header, 756 uint8_t *address) 757 { 758 enum bp_result result = BP_RESULT_NORECORD; 759 struct atom_voltage_objects_info_v4_1 *info = 760 (struct atom_voltage_objects_info_v4_1 *) address; 761 762 uint8_t *voltage_current_object = 763 (uint8_t *) (&(info->voltage_object[0])); 764 765 while ((address + le16_to_cpu(header->structuresize)) > 766 voltage_current_object) { 767 struct atom_i2c_voltage_object_v4 *object = 768 (struct atom_i2c_voltage_object_v4 *) 769 voltage_current_object; 770 771 if (object->header.voltage_mode == 772 ATOM_INIT_VOLTAGE_REGULATOR) { 773 if (object->header.voltage_type == index) { 774 *i2c_line = object->i2c_id ^ 0x90; 775 result = BP_RESULT_OK; 776 break; 777 } 778 } 779 780 voltage_current_object += 781 le16_to_cpu(object->header.object_size); 782 } 783 return result; 784 } 785 786 static enum bp_result bios_parser_get_thermal_ddc_info( 787 struct dc_bios *dcb, 788 uint32_t i2c_channel_id, 789 struct graphics_object_i2c_info *info) 790 { 791 struct bios_parser *bp = BP_FROM_DCB(dcb); 792 struct i2c_id_config_access *config; 793 struct atom_i2c_record record; 794 795 if (!info) 796 return BP_RESULT_BADINPUT; 797 798 config = (struct i2c_id_config_access *) &i2c_channel_id; 799 800 record.i2c_id = config->bfHW_Capable; 801 record.i2c_id |= config->bfI2C_LineMux; 802 record.i2c_id |= config->bfHW_EngineID; 803 804 return get_gpio_i2c_info(bp, &record, info); 805 } 806 807 static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb, 808 uint32_t index, 809 struct graphics_object_i2c_info *info) 810 { 811 uint8_t i2c_line = 0; 812 enum bp_result result = BP_RESULT_NORECORD; 813 uint8_t *voltage_info_address; 814 struct atom_common_table_header *header; 815 struct atom_data_revision revision = {0}; 816 struct bios_parser *bp = BP_FROM_DCB(dcb); 817 818 if (!DATA_TABLES(voltageobject_info)) 819 return result; 820 821 voltage_info_address = get_image(&bp->base, 822 DATA_TABLES(voltageobject_info), 823 sizeof(struct atom_common_table_header)); 824 825 header = (struct atom_common_table_header *) voltage_info_address; 826 827 get_atom_data_table_revision(header, &revision); 828 829 switch (revision.major) { 830 case 4: 831 if (revision.minor != 1) 832 break; 833 result = get_voltage_ddc_info_v4(&i2c_line, index, header, 834 voltage_info_address); 835 break; 836 } 837 838 if (result == BP_RESULT_OK) 839 result = bios_parser_get_thermal_ddc_info(dcb, 840 i2c_line, info); 841 842 return result; 843 } 844 845 static enum bp_result bios_parser_get_hpd_info( 846 struct dc_bios *dcb, 847 struct graphics_object_id id, 848 struct graphics_object_hpd_info *info) 849 { 850 struct bios_parser *bp = BP_FROM_DCB(dcb); 851 struct atom_display_object_path_v2 *object; 852 struct atom_hpd_int_record *record = NULL; 853 854 if (!info) 855 return BP_RESULT_BADINPUT; 856 857 object = get_bios_object(bp, id); 858 859 if (!object) 860 return BP_RESULT_BADINPUT; 861 862 record = get_hpd_record(bp, object); 863 864 if (record != NULL) { 865 info->hpd_int_gpio_uid = record->pin_id; 866 info->hpd_active = record->plugin_pin_state; 867 return BP_RESULT_OK; 868 } 869 870 return BP_RESULT_NORECORD; 871 } 872 873 static struct atom_hpd_int_record *get_hpd_record( 874 struct bios_parser *bp, 875 struct atom_display_object_path_v2 *object) 876 { 877 struct atom_common_record_header *header; 878 uint32_t offset; 879 880 if (!object) { 881 BREAK_TO_DEBUGGER(); /* Invalid object */ 882 return NULL; 883 } 884 885 offset = le16_to_cpu(object->disp_recordoffset) 886 + bp->object_info_tbl_offset; 887 888 for (;;) { 889 header = GET_IMAGE(struct atom_common_record_header, offset); 890 891 if (!header) 892 return NULL; 893 894 if (header->record_type == LAST_RECORD_TYPE || 895 !header->record_size) 896 break; 897 898 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 899 && sizeof(struct atom_hpd_int_record) <= 900 header->record_size) 901 return (struct atom_hpd_int_record *) header; 902 903 offset += header->record_size; 904 } 905 906 return NULL; 907 } 908 909 /** 910 * bios_parser_get_gpio_pin_info 911 * Get GpioPin information of input gpio id 912 * 913 * @param gpio_id, GPIO ID 914 * @param info, GpioPin information structure 915 * @return Bios parser result code 916 * @note 917 * to get the GPIO PIN INFO, we need: 918 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 919 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 920 * to get the registerA offset/mask 921 */ 922 static enum bp_result bios_parser_get_gpio_pin_info( 923 struct dc_bios *dcb, 924 uint32_t gpio_id, 925 struct gpio_pin_info *info) 926 { 927 struct bios_parser *bp = BP_FROM_DCB(dcb); 928 struct atom_gpio_pin_lut_v2_1 *header; 929 uint32_t count = 0; 930 uint32_t i = 0; 931 932 if (!DATA_TABLES(gpio_pin_lut)) 933 return BP_RESULT_BADBIOSTABLE; 934 935 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 936 DATA_TABLES(gpio_pin_lut)); 937 if (!header) 938 return BP_RESULT_BADBIOSTABLE; 939 940 if (sizeof(struct atom_common_table_header) + 941 sizeof(struct atom_gpio_pin_lut_v2_1) 942 > le16_to_cpu(header->table_header.structuresize)) 943 return BP_RESULT_BADBIOSTABLE; 944 945 if (header->table_header.content_revision != 1) 946 return BP_RESULT_UNSUPPORTED; 947 948 /* Temporary hard code gpio pin info */ 949 #if defined(FOR_SIMNOW_BOOT) 950 { 951 struct atom_gpio_pin_assignment gpio_pin[8] = { 952 {0x5db5, 0, 0, 1, 0}, 953 {0x5db5, 8, 8, 2, 0}, 954 {0x5db5, 0x10, 0x10, 3, 0}, 955 {0x5db5, 0x18, 0x14, 4, 0}, 956 {0x5db5, 0x1A, 0x18, 5, 0}, 957 {0x5db5, 0x1C, 0x1C, 6, 0}, 958 }; 959 960 count = 6; 961 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 962 } 963 #else 964 count = (le16_to_cpu(header->table_header.structuresize) 965 - sizeof(struct atom_common_table_header)) 966 / sizeof(struct atom_gpio_pin_assignment); 967 #endif 968 for (i = 0; i < count; ++i) { 969 if (header->gpio_pin[i].gpio_id != gpio_id) 970 continue; 971 972 info->offset = 973 (uint32_t) le16_to_cpu( 974 header->gpio_pin[i].data_a_reg_index); 975 info->offset_y = info->offset + 2; 976 info->offset_en = info->offset + 1; 977 info->offset_mask = info->offset - 1; 978 979 info->mask = (uint32_t) (1 << 980 header->gpio_pin[i].gpio_bitshift); 981 info->mask_y = info->mask + 2; 982 info->mask_en = info->mask + 1; 983 info->mask_mask = info->mask - 1; 984 985 return BP_RESULT_OK; 986 } 987 988 return BP_RESULT_NORECORD; 989 } 990 991 static struct device_id device_type_from_device_id(uint16_t device_id) 992 { 993 994 struct device_id result_device_id; 995 996 switch (device_id) { 997 case ATOM_DISPLAY_LCD1_SUPPORT: 998 result_device_id.device_type = DEVICE_TYPE_LCD; 999 result_device_id.enum_id = 1; 1000 break; 1001 1002 case ATOM_DISPLAY_DFP1_SUPPORT: 1003 result_device_id.device_type = DEVICE_TYPE_DFP; 1004 result_device_id.enum_id = 1; 1005 break; 1006 1007 case ATOM_DISPLAY_DFP2_SUPPORT: 1008 result_device_id.device_type = DEVICE_TYPE_DFP; 1009 result_device_id.enum_id = 2; 1010 break; 1011 1012 case ATOM_DISPLAY_DFP3_SUPPORT: 1013 result_device_id.device_type = DEVICE_TYPE_DFP; 1014 result_device_id.enum_id = 3; 1015 break; 1016 1017 case ATOM_DISPLAY_DFP4_SUPPORT: 1018 result_device_id.device_type = DEVICE_TYPE_DFP; 1019 result_device_id.enum_id = 4; 1020 break; 1021 1022 case ATOM_DISPLAY_DFP5_SUPPORT: 1023 result_device_id.device_type = DEVICE_TYPE_DFP; 1024 result_device_id.enum_id = 5; 1025 break; 1026 1027 case ATOM_DISPLAY_DFP6_SUPPORT: 1028 result_device_id.device_type = DEVICE_TYPE_DFP; 1029 result_device_id.enum_id = 6; 1030 break; 1031 1032 default: 1033 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 1034 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 1035 result_device_id.enum_id = 0; 1036 } 1037 return result_device_id; 1038 } 1039 1040 static enum bp_result bios_parser_get_device_tag( 1041 struct dc_bios *dcb, 1042 struct graphics_object_id connector_object_id, 1043 uint32_t device_tag_index, 1044 struct connector_device_tag_info *info) 1045 { 1046 struct bios_parser *bp = BP_FROM_DCB(dcb); 1047 struct atom_display_object_path_v2 *object; 1048 1049 if (!info) 1050 return BP_RESULT_BADINPUT; 1051 1052 /* getBiosObject will return MXM object */ 1053 object = get_bios_object(bp, connector_object_id); 1054 1055 if (!object) { 1056 BREAK_TO_DEBUGGER(); /* Invalid object id */ 1057 return BP_RESULT_BADINPUT; 1058 } 1059 1060 info->acpi_device = 0; /* BIOS no longer provides this */ 1061 info->dev_id = device_type_from_device_id(object->device_tag); 1062 1063 return BP_RESULT_OK; 1064 } 1065 1066 static enum bp_result get_ss_info_v4_1( 1067 struct bios_parser *bp, 1068 uint32_t id, 1069 uint32_t index, 1070 struct spread_spectrum_info *ss_info) 1071 { 1072 enum bp_result result = BP_RESULT_OK; 1073 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1074 1075 if (!ss_info) 1076 return BP_RESULT_BADINPUT; 1077 1078 if (!DATA_TABLES(dce_info)) 1079 return BP_RESULT_BADBIOSTABLE; 1080 1081 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1082 DATA_TABLES(dce_info)); 1083 if (!disp_cntl_tbl) 1084 return BP_RESULT_BADBIOSTABLE; 1085 1086 ss_info->type.STEP_AND_DELAY_INFO = false; 1087 ss_info->spread_percentage_divider = 1000; 1088 /* BIOS no longer uses target clock. Always enable for now */ 1089 ss_info->target_clock_range = 0xffffffff; 1090 1091 switch (id) { 1092 case AS_SIGNAL_TYPE_DVI: 1093 ss_info->spread_spectrum_percentage = 1094 disp_cntl_tbl->dvi_ss_percentage; 1095 ss_info->spread_spectrum_range = 1096 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1097 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1098 ss_info->type.CENTER_MODE = true; 1099 break; 1100 case AS_SIGNAL_TYPE_HDMI: 1101 ss_info->spread_spectrum_percentage = 1102 disp_cntl_tbl->hdmi_ss_percentage; 1103 ss_info->spread_spectrum_range = 1104 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1105 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1106 ss_info->type.CENTER_MODE = true; 1107 break; 1108 /* TODO LVDS not support anymore? */ 1109 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1110 ss_info->spread_spectrum_percentage = 1111 disp_cntl_tbl->dp_ss_percentage; 1112 ss_info->spread_spectrum_range = 1113 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1114 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1115 ss_info->type.CENTER_MODE = true; 1116 break; 1117 case AS_SIGNAL_TYPE_GPU_PLL: 1118 /* atom_firmware: DAL only get data from dce_info table. 1119 * if data within smu_info is needed for DAL, VBIOS should 1120 * copy it into dce_info 1121 */ 1122 result = BP_RESULT_UNSUPPORTED; 1123 break; 1124 default: 1125 result = BP_RESULT_UNSUPPORTED; 1126 } 1127 1128 return result; 1129 } 1130 1131 static enum bp_result get_ss_info_v4_2( 1132 struct bios_parser *bp, 1133 uint32_t id, 1134 uint32_t index, 1135 struct spread_spectrum_info *ss_info) 1136 { 1137 enum bp_result result = BP_RESULT_OK; 1138 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1139 struct atom_smu_info_v3_1 *smu_info = NULL; 1140 1141 if (!ss_info) 1142 return BP_RESULT_BADINPUT; 1143 1144 if (!DATA_TABLES(dce_info)) 1145 return BP_RESULT_BADBIOSTABLE; 1146 1147 if (!DATA_TABLES(smu_info)) 1148 return BP_RESULT_BADBIOSTABLE; 1149 1150 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1151 DATA_TABLES(dce_info)); 1152 if (!disp_cntl_tbl) 1153 return BP_RESULT_BADBIOSTABLE; 1154 1155 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 1156 if (!smu_info) 1157 return BP_RESULT_BADBIOSTABLE; 1158 1159 ss_info->type.STEP_AND_DELAY_INFO = false; 1160 ss_info->spread_percentage_divider = 1000; 1161 /* BIOS no longer uses target clock. Always enable for now */ 1162 ss_info->target_clock_range = 0xffffffff; 1163 1164 switch (id) { 1165 case AS_SIGNAL_TYPE_DVI: 1166 ss_info->spread_spectrum_percentage = 1167 disp_cntl_tbl->dvi_ss_percentage; 1168 ss_info->spread_spectrum_range = 1169 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1170 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1171 ss_info->type.CENTER_MODE = true; 1172 break; 1173 case AS_SIGNAL_TYPE_HDMI: 1174 ss_info->spread_spectrum_percentage = 1175 disp_cntl_tbl->hdmi_ss_percentage; 1176 ss_info->spread_spectrum_range = 1177 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1178 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1179 ss_info->type.CENTER_MODE = true; 1180 break; 1181 /* TODO LVDS not support anymore? */ 1182 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1183 ss_info->spread_spectrum_percentage = 1184 smu_info->gpuclk_ss_percentage; 1185 ss_info->spread_spectrum_range = 1186 smu_info->gpuclk_ss_rate_10hz * 10; 1187 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1188 ss_info->type.CENTER_MODE = true; 1189 break; 1190 case AS_SIGNAL_TYPE_GPU_PLL: 1191 /* atom_firmware: DAL only get data from dce_info table. 1192 * if data within smu_info is needed for DAL, VBIOS should 1193 * copy it into dce_info 1194 */ 1195 result = BP_RESULT_UNSUPPORTED; 1196 break; 1197 default: 1198 result = BP_RESULT_UNSUPPORTED; 1199 } 1200 1201 return result; 1202 } 1203 1204 /** 1205 * bios_parser_get_spread_spectrum_info 1206 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1207 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1208 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1209 * ver 3.1, 1210 * there is only one entry for each signal /ss id. However, there is 1211 * no planning of supporting multiple spread Sprectum entry for EverGreen 1212 * @param [in] this 1213 * @param [in] signal, ASSignalType to be converted to info index 1214 * @param [in] index, number of entries that match the converted info index 1215 * @param [out] ss_info, sprectrum information structure, 1216 * @return Bios parser result code 1217 */ 1218 static enum bp_result bios_parser_get_spread_spectrum_info( 1219 struct dc_bios *dcb, 1220 enum as_signal_type signal, 1221 uint32_t index, 1222 struct spread_spectrum_info *ss_info) 1223 { 1224 struct bios_parser *bp = BP_FROM_DCB(dcb); 1225 enum bp_result result = BP_RESULT_UNSUPPORTED; 1226 struct atom_common_table_header *header; 1227 struct atom_data_revision tbl_revision; 1228 1229 if (!ss_info) /* check for bad input */ 1230 return BP_RESULT_BADINPUT; 1231 1232 if (!DATA_TABLES(dce_info)) 1233 return BP_RESULT_UNSUPPORTED; 1234 1235 header = GET_IMAGE(struct atom_common_table_header, 1236 DATA_TABLES(dce_info)); 1237 get_atom_data_table_revision(header, &tbl_revision); 1238 1239 switch (tbl_revision.major) { 1240 case 4: 1241 switch (tbl_revision.minor) { 1242 case 1: 1243 return get_ss_info_v4_1(bp, signal, index, ss_info); 1244 case 2: 1245 return get_ss_info_v4_2(bp, signal, index, ss_info); 1246 default: 1247 break; 1248 } 1249 break; 1250 default: 1251 break; 1252 } 1253 /* there can not be more then one entry for SS Info table */ 1254 return result; 1255 } 1256 1257 static enum bp_result get_embedded_panel_info_v2_1( 1258 struct bios_parser *bp, 1259 struct embedded_panel_info *info) 1260 { 1261 struct lcd_info_v2_1 *lvds; 1262 1263 if (!info) 1264 return BP_RESULT_BADINPUT; 1265 1266 if (!DATA_TABLES(lcd_info)) 1267 return BP_RESULT_UNSUPPORTED; 1268 1269 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1270 1271 if (!lvds) 1272 return BP_RESULT_BADBIOSTABLE; 1273 1274 /* TODO: previous vv1_3, should v2_1 */ 1275 if (!((lvds->table_header.format_revision == 2) 1276 && (lvds->table_header.content_revision >= 1))) 1277 return BP_RESULT_UNSUPPORTED; 1278 1279 memset(info, 0, sizeof(struct embedded_panel_info)); 1280 1281 /* We need to convert from 10KHz units into KHz units */ 1282 info->lcd_timing.pixel_clk = 1283 le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1284 /* usHActive does not include borders, according to VBIOS team */ 1285 info->lcd_timing.horizontal_addressable = 1286 le16_to_cpu(lvds->lcd_timing.h_active); 1287 /* usHBlanking_Time includes borders, so we should really be 1288 * subtractingborders duing this translation, but LVDS generally 1289 * doesn't have borders, so we should be okay leaving this as is for 1290 * now. May need to revisit if we ever have LVDS with borders 1291 */ 1292 info->lcd_timing.horizontal_blanking_time = 1293 le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1294 /* usVActive does not include borders, according to VBIOS team*/ 1295 info->lcd_timing.vertical_addressable = 1296 le16_to_cpu(lvds->lcd_timing.v_active); 1297 /* usVBlanking_Time includes borders, so we should really be 1298 * subtracting borders duing this translation, but LVDS generally 1299 * doesn't have borders, so we should be okay leaving this as is for 1300 * now. May need to revisit if we ever have LVDS with borders 1301 */ 1302 info->lcd_timing.vertical_blanking_time = 1303 le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1304 info->lcd_timing.horizontal_sync_offset = 1305 le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1306 info->lcd_timing.horizontal_sync_width = 1307 le16_to_cpu(lvds->lcd_timing.h_sync_width); 1308 info->lcd_timing.vertical_sync_offset = 1309 le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1310 info->lcd_timing.vertical_sync_width = 1311 le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1312 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1313 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1314 1315 /* not provided by VBIOS */ 1316 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1317 1318 info->lcd_timing.misc_info.H_SYNC_POLARITY = 1319 ~(uint32_t) 1320 (lvds->lcd_timing.miscinfo & ATOM_HSYNC_POLARITY); 1321 info->lcd_timing.misc_info.V_SYNC_POLARITY = 1322 ~(uint32_t) 1323 (lvds->lcd_timing.miscinfo & ATOM_VSYNC_POLARITY); 1324 1325 /* not provided by VBIOS */ 1326 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1327 1328 info->lcd_timing.misc_info.H_REPLICATION_BY2 = 1329 lvds->lcd_timing.miscinfo & ATOM_H_REPLICATIONBY2; 1330 info->lcd_timing.misc_info.V_REPLICATION_BY2 = 1331 lvds->lcd_timing.miscinfo & ATOM_V_REPLICATIONBY2; 1332 info->lcd_timing.misc_info.COMPOSITE_SYNC = 1333 lvds->lcd_timing.miscinfo & ATOM_COMPOSITESYNC; 1334 info->lcd_timing.misc_info.INTERLACE = 1335 lvds->lcd_timing.miscinfo & ATOM_INTERLACE; 1336 1337 /* not provided by VBIOS*/ 1338 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1339 /* not provided by VBIOS*/ 1340 info->ss_id = 0; 1341 1342 info->realtek_eDPToLVDS = 1343 (lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID ? 1:0); 1344 1345 return BP_RESULT_OK; 1346 } 1347 1348 static enum bp_result bios_parser_get_embedded_panel_info( 1349 struct dc_bios *dcb, 1350 struct embedded_panel_info *info) 1351 { 1352 struct bios_parser *bp = BP_FROM_DCB(dcb); 1353 struct atom_common_table_header *header; 1354 struct atom_data_revision tbl_revision; 1355 1356 if (!DATA_TABLES(lcd_info)) 1357 return BP_RESULT_FAILURE; 1358 1359 header = GET_IMAGE(struct atom_common_table_header, 1360 DATA_TABLES(lcd_info)); 1361 1362 if (!header) 1363 return BP_RESULT_BADBIOSTABLE; 1364 1365 get_atom_data_table_revision(header, &tbl_revision); 1366 1367 1368 switch (tbl_revision.major) { 1369 case 2: 1370 switch (tbl_revision.minor) { 1371 case 1: 1372 return get_embedded_panel_info_v2_1(bp, info); 1373 default: 1374 break; 1375 } 1376 default: 1377 break; 1378 } 1379 1380 return BP_RESULT_FAILURE; 1381 } 1382 1383 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1384 { 1385 enum dal_device_type device_type = device_id.device_type; 1386 uint32_t enum_id = device_id.enum_id; 1387 1388 switch (device_type) { 1389 case DEVICE_TYPE_LCD: 1390 switch (enum_id) { 1391 case 1: 1392 return ATOM_DISPLAY_LCD1_SUPPORT; 1393 default: 1394 break; 1395 } 1396 break; 1397 case DEVICE_TYPE_DFP: 1398 switch (enum_id) { 1399 case 1: 1400 return ATOM_DISPLAY_DFP1_SUPPORT; 1401 case 2: 1402 return ATOM_DISPLAY_DFP2_SUPPORT; 1403 case 3: 1404 return ATOM_DISPLAY_DFP3_SUPPORT; 1405 case 4: 1406 return ATOM_DISPLAY_DFP4_SUPPORT; 1407 case 5: 1408 return ATOM_DISPLAY_DFP5_SUPPORT; 1409 case 6: 1410 return ATOM_DISPLAY_DFP6_SUPPORT; 1411 default: 1412 break; 1413 } 1414 break; 1415 default: 1416 break; 1417 }; 1418 1419 /* Unidentified device ID, return empty support mask. */ 1420 return 0; 1421 } 1422 1423 static bool bios_parser_is_device_id_supported( 1424 struct dc_bios *dcb, 1425 struct device_id id) 1426 { 1427 struct bios_parser *bp = BP_FROM_DCB(dcb); 1428 1429 uint32_t mask = get_support_mask_for_device_id(id); 1430 1431 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1432 mask) != 0; 1433 } 1434 1435 static void bios_parser_post_init( 1436 struct dc_bios *dcb) 1437 { 1438 /* TODO for OPM module. Need implement later */ 1439 } 1440 1441 static uint32_t bios_parser_get_ss_entry_number( 1442 struct dc_bios *dcb, 1443 enum as_signal_type signal) 1444 { 1445 /* TODO: DAL2 atomfirmware implementation does not need this. 1446 * why DAL3 need this? 1447 */ 1448 return 1; 1449 } 1450 1451 static enum bp_result bios_parser_transmitter_control( 1452 struct dc_bios *dcb, 1453 struct bp_transmitter_control *cntl) 1454 { 1455 struct bios_parser *bp = BP_FROM_DCB(dcb); 1456 1457 if (!bp->cmd_tbl.transmitter_control) 1458 return BP_RESULT_FAILURE; 1459 1460 return bp->cmd_tbl.transmitter_control(bp, cntl); 1461 } 1462 1463 static enum bp_result bios_parser_encoder_control( 1464 struct dc_bios *dcb, 1465 struct bp_encoder_control *cntl) 1466 { 1467 struct bios_parser *bp = BP_FROM_DCB(dcb); 1468 1469 if (!bp->cmd_tbl.dig_encoder_control) 1470 return BP_RESULT_FAILURE; 1471 1472 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1473 } 1474 1475 static enum bp_result bios_parser_set_pixel_clock( 1476 struct dc_bios *dcb, 1477 struct bp_pixel_clock_parameters *bp_params) 1478 { 1479 struct bios_parser *bp = BP_FROM_DCB(dcb); 1480 1481 if (!bp->cmd_tbl.set_pixel_clock) 1482 return BP_RESULT_FAILURE; 1483 1484 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1485 } 1486 1487 static enum bp_result bios_parser_set_dce_clock( 1488 struct dc_bios *dcb, 1489 struct bp_set_dce_clock_parameters *bp_params) 1490 { 1491 struct bios_parser *bp = BP_FROM_DCB(dcb); 1492 1493 if (!bp->cmd_tbl.set_dce_clock) 1494 return BP_RESULT_FAILURE; 1495 1496 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1497 } 1498 1499 static unsigned int bios_parser_get_smu_clock_info( 1500 struct dc_bios *dcb) 1501 { 1502 struct bios_parser *bp = BP_FROM_DCB(dcb); 1503 1504 if (!bp->cmd_tbl.get_smu_clock_info) 1505 return BP_RESULT_FAILURE; 1506 1507 return bp->cmd_tbl.get_smu_clock_info(bp); 1508 } 1509 1510 static enum bp_result bios_parser_program_crtc_timing( 1511 struct dc_bios *dcb, 1512 struct bp_hw_crtc_timing_parameters *bp_params) 1513 { 1514 struct bios_parser *bp = BP_FROM_DCB(dcb); 1515 1516 if (!bp->cmd_tbl.set_crtc_timing) 1517 return BP_RESULT_FAILURE; 1518 1519 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1520 } 1521 1522 static enum bp_result bios_parser_enable_crtc( 1523 struct dc_bios *dcb, 1524 enum controller_id id, 1525 bool enable) 1526 { 1527 struct bios_parser *bp = BP_FROM_DCB(dcb); 1528 1529 if (!bp->cmd_tbl.enable_crtc) 1530 return BP_RESULT_FAILURE; 1531 1532 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1533 } 1534 1535 static enum bp_result bios_parser_crtc_source_select( 1536 struct dc_bios *dcb, 1537 struct bp_crtc_source_select *bp_params) 1538 { 1539 struct bios_parser *bp = BP_FROM_DCB(dcb); 1540 1541 if (!bp->cmd_tbl.select_crtc_source) 1542 return BP_RESULT_FAILURE; 1543 1544 return bp->cmd_tbl.select_crtc_source(bp, bp_params); 1545 } 1546 1547 static enum bp_result bios_parser_enable_disp_power_gating( 1548 struct dc_bios *dcb, 1549 enum controller_id controller_id, 1550 enum bp_pipe_control_action action) 1551 { 1552 struct bios_parser *bp = BP_FROM_DCB(dcb); 1553 1554 if (!bp->cmd_tbl.enable_disp_power_gating) 1555 return BP_RESULT_FAILURE; 1556 1557 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1558 action); 1559 } 1560 1561 static bool bios_parser_is_accelerated_mode( 1562 struct dc_bios *dcb) 1563 { 1564 return bios_is_accelerated_mode(dcb); 1565 } 1566 1567 1568 /** 1569 * bios_parser_set_scratch_critical_state 1570 * 1571 * @brief 1572 * update critical state bit in VBIOS scratch register 1573 * 1574 * @param 1575 * bool - to set or reset state 1576 */ 1577 static void bios_parser_set_scratch_critical_state( 1578 struct dc_bios *dcb, 1579 bool state) 1580 { 1581 bios_set_scratch_critical_state(dcb, state); 1582 } 1583 1584 static enum bp_result bios_parser_get_firmware_info( 1585 struct dc_bios *dcb, 1586 struct dc_firmware_info *info) 1587 { 1588 struct bios_parser *bp = BP_FROM_DCB(dcb); 1589 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1590 struct atom_common_table_header *header; 1591 1592 struct atom_data_revision revision; 1593 1594 if (info && DATA_TABLES(firmwareinfo)) { 1595 header = GET_IMAGE(struct atom_common_table_header, 1596 DATA_TABLES(firmwareinfo)); 1597 get_atom_data_table_revision(header, &revision); 1598 switch (revision.major) { 1599 case 3: 1600 switch (revision.minor) { 1601 case 1: 1602 result = get_firmware_info_v3_1(bp, info); 1603 break; 1604 default: 1605 break; 1606 } 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 return result; 1614 } 1615 1616 static enum bp_result get_firmware_info_v3_1( 1617 struct bios_parser *bp, 1618 struct dc_firmware_info *info) 1619 { 1620 struct atom_firmware_info_v3_1 *firmware_info; 1621 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1622 1623 if (!info) 1624 return BP_RESULT_BADINPUT; 1625 1626 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1627 DATA_TABLES(firmwareinfo)); 1628 1629 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1630 DATA_TABLES(dce_info)); 1631 1632 if (!firmware_info || !dce_info) 1633 return BP_RESULT_BADBIOSTABLE; 1634 1635 memset(info, 0, sizeof(*info)); 1636 1637 /* Pixel clock pll information. */ 1638 /* We need to convert from 10KHz units into KHz units */ 1639 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1640 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1641 1642 /* 27MHz for Vega10: */ 1643 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1644 1645 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1646 if (info->pll_info.crystal_frequency == 0) 1647 info->pll_info.crystal_frequency = 27000; 1648 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1649 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1650 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1651 1652 /* Get GPU PLL VCO Clock */ 1653 1654 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1655 /* VBIOS gives in 10KHz */ 1656 info->smu_gpu_pll_output_freq = 1657 bp->cmd_tbl.get_smu_clock_info(bp) * 10; 1658 } 1659 1660 return BP_RESULT_OK; 1661 } 1662 1663 static enum bp_result bios_parser_get_encoder_cap_info( 1664 struct dc_bios *dcb, 1665 struct graphics_object_id object_id, 1666 struct bp_encoder_cap_info *info) 1667 { 1668 struct bios_parser *bp = BP_FROM_DCB(dcb); 1669 struct atom_display_object_path_v2 *object; 1670 struct atom_encoder_caps_record *record = NULL; 1671 1672 if (!info) 1673 return BP_RESULT_BADINPUT; 1674 1675 object = get_bios_object(bp, object_id); 1676 1677 if (!object) 1678 return BP_RESULT_BADINPUT; 1679 1680 record = get_encoder_cap_record(bp, object); 1681 if (!record) 1682 return BP_RESULT_NORECORD; 1683 1684 info->DP_HBR2_CAP = (record->encodercaps & 1685 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1686 info->DP_HBR2_EN = (record->encodercaps & 1687 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1688 info->DP_HBR3_EN = (record->encodercaps & 1689 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1690 info->HDMI_6GB_EN = (record->encodercaps & 1691 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1692 1693 return BP_RESULT_OK; 1694 } 1695 1696 1697 static struct atom_encoder_caps_record *get_encoder_cap_record( 1698 struct bios_parser *bp, 1699 struct atom_display_object_path_v2 *object) 1700 { 1701 struct atom_common_record_header *header; 1702 uint32_t offset; 1703 1704 if (!object) { 1705 BREAK_TO_DEBUGGER(); /* Invalid object */ 1706 return NULL; 1707 } 1708 1709 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1710 1711 for (;;) { 1712 header = GET_IMAGE(struct atom_common_record_header, offset); 1713 1714 if (!header) 1715 return NULL; 1716 1717 offset += header->record_size; 1718 1719 if (header->record_type == LAST_RECORD_TYPE || 1720 !header->record_size) 1721 break; 1722 1723 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1724 continue; 1725 1726 if (sizeof(struct atom_encoder_caps_record) <= 1727 header->record_size) 1728 return (struct atom_encoder_caps_record *)header; 1729 } 1730 1731 return NULL; 1732 } 1733 1734 /* 1735 * get_integrated_info_v11 1736 * 1737 * @brief 1738 * Get V8 integrated BIOS information 1739 * 1740 * @param 1741 * bios_parser *bp - [in]BIOS parser handler to get master data table 1742 * integrated_info *info - [out] store and output integrated info 1743 * 1744 * @return 1745 * enum bp_result - BP_RESULT_OK if information is available, 1746 * BP_RESULT_BADBIOSTABLE otherwise. 1747 */ 1748 static enum bp_result get_integrated_info_v11( 1749 struct bios_parser *bp, 1750 struct integrated_info *info) 1751 { 1752 struct atom_integrated_system_info_v1_11 *info_v11; 1753 uint32_t i; 1754 1755 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1756 DATA_TABLES(integratedsysteminfo)); 1757 1758 if (info_v11 == NULL) 1759 return BP_RESULT_BADBIOSTABLE; 1760 1761 info->gpu_cap_info = 1762 le32_to_cpu(info_v11->gpucapinfo); 1763 /* 1764 * system_config: Bit[0] = 0 : PCIE power gating disabled 1765 * = 1 : PCIE power gating enabled 1766 * Bit[1] = 0 : DDR-PLL shut down disabled 1767 * = 1 : DDR-PLL shut down enabled 1768 * Bit[2] = 0 : DDR-PLL power down disabled 1769 * = 1 : DDR-PLL power down enabled 1770 */ 1771 info->system_config = le32_to_cpu(info_v11->system_config); 1772 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1773 info->memory_type = info_v11->memorytype; 1774 info->ma_channel_number = info_v11->umachannelnumber; 1775 info->lvds_ss_percentage = 1776 le16_to_cpu(info_v11->lvds_ss_percentage); 1777 info->lvds_sspread_rate_in_10hz = 1778 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1779 info->hdmi_ss_percentage = 1780 le16_to_cpu(info_v11->hdmi_ss_percentage); 1781 info->hdmi_sspread_rate_in_10hz = 1782 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1783 info->dvi_ss_percentage = 1784 le16_to_cpu(info_v11->dvi_ss_percentage); 1785 info->dvi_sspread_rate_in_10_hz = 1786 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1787 info->lvds_misc = info_v11->lvds_misc; 1788 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1789 info->ext_disp_conn_info.gu_id[i] = 1790 info_v11->extdispconninfo.guid[i]; 1791 } 1792 1793 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1794 info->ext_disp_conn_info.path[i].device_connector_id = 1795 object_id_from_bios_object_id( 1796 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1797 1798 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1799 object_id_from_bios_object_id( 1800 le16_to_cpu( 1801 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1802 1803 info->ext_disp_conn_info.path[i].device_tag = 1804 le16_to_cpu( 1805 info_v11->extdispconninfo.path[i].device_tag); 1806 info->ext_disp_conn_info.path[i].device_acpi_enum = 1807 le16_to_cpu( 1808 info_v11->extdispconninfo.path[i].device_acpi_enum); 1809 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1810 info_v11->extdispconninfo.path[i].auxddclut_index; 1811 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1812 info_v11->extdispconninfo.path[i].hpdlut_index; 1813 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1814 info_v11->extdispconninfo.path[i].channelmapping; 1815 } 1816 info->ext_disp_conn_info.checksum = 1817 info_v11->extdispconninfo.checksum; 1818 1819 /** TODO - review **/ 1820 #if 0 1821 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1822 * 10; 1823 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1824 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1825 1826 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1827 /* Convert [10KHz] into [KHz] */ 1828 info->disp_clk_voltage[i].max_supported_clk = 1829 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1830 ulMaximumSupportedCLK) * 10; 1831 info->disp_clk_voltage[i].voltage_index = 1832 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1833 } 1834 1835 info->boot_up_req_display_vector = 1836 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1837 info->boot_up_nb_voltage = 1838 le16_to_cpu(info_v11->usBootUpNBVoltage); 1839 info->ext_disp_conn_info_offset = 1840 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1841 info->gmc_restore_reset_time = 1842 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1843 info->minimum_n_clk = 1844 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1845 for (i = 1; i < 4; ++i) 1846 info->minimum_n_clk = 1847 info->minimum_n_clk < 1848 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1849 info->minimum_n_clk : le32_to_cpu( 1850 info_v11->ulNbpStateNClkFreq[i]); 1851 1852 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1853 info->ddr_dll_power_up_time = 1854 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1855 info->ddr_pll_power_up_time = 1856 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1857 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1858 info->max_lvds_pclk_freq_in_single_link = 1859 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1860 info->max_lvds_pclk_freq_in_single_link = 1861 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1862 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1863 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1864 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1865 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1866 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1867 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1868 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1869 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1870 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1871 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1872 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1873 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1874 info->lvds_off_to_on_delay_in_4ms = 1875 info_v11->ucLVDSOffToOnDelay_in4Ms; 1876 info->lvds_bit_depth_control_val = 1877 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1878 1879 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1880 /* Convert [10KHz] into [KHz] */ 1881 info->avail_s_clk[i].supported_s_clk = 1882 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1883 * 10; 1884 info->avail_s_clk[i].voltage_index = 1885 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1886 info->avail_s_clk[i].voltage_id = 1887 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1888 } 1889 #endif /* TODO*/ 1890 1891 return BP_RESULT_OK; 1892 } 1893 1894 1895 /* 1896 * construct_integrated_info 1897 * 1898 * @brief 1899 * Get integrated BIOS information based on table revision 1900 * 1901 * @param 1902 * bios_parser *bp - [in]BIOS parser handler to get master data table 1903 * integrated_info *info - [out] store and output integrated info 1904 * 1905 * @return 1906 * enum bp_result - BP_RESULT_OK if information is available, 1907 * BP_RESULT_BADBIOSTABLE otherwise. 1908 */ 1909 static enum bp_result construct_integrated_info( 1910 struct bios_parser *bp, 1911 struct integrated_info *info) 1912 { 1913 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1914 1915 struct atom_common_table_header *header; 1916 struct atom_data_revision revision; 1917 1918 struct clock_voltage_caps temp = {0, 0}; 1919 uint32_t i; 1920 uint32_t j; 1921 1922 if (info && DATA_TABLES(integratedsysteminfo)) { 1923 header = GET_IMAGE(struct atom_common_table_header, 1924 DATA_TABLES(integratedsysteminfo)); 1925 1926 get_atom_data_table_revision(header, &revision); 1927 1928 /* Don't need to check major revision as they are all 1 */ 1929 switch (revision.minor) { 1930 case 11: 1931 result = get_integrated_info_v11(bp, info); 1932 break; 1933 default: 1934 return result; 1935 } 1936 } 1937 1938 if (result != BP_RESULT_OK) 1939 return result; 1940 1941 /* Sort voltage table from low to high*/ 1942 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1943 for (j = i; j > 0; --j) { 1944 if (info->disp_clk_voltage[j].max_supported_clk < 1945 info->disp_clk_voltage[j-1].max_supported_clk 1946 ) { 1947 /* swap j and j - 1*/ 1948 temp = info->disp_clk_voltage[j-1]; 1949 info->disp_clk_voltage[j-1] = 1950 info->disp_clk_voltage[j]; 1951 info->disp_clk_voltage[j] = temp; 1952 } 1953 } 1954 } 1955 1956 return result; 1957 } 1958 1959 static struct integrated_info *bios_parser_create_integrated_info( 1960 struct dc_bios *dcb) 1961 { 1962 struct bios_parser *bp = BP_FROM_DCB(dcb); 1963 struct integrated_info *info = NULL; 1964 1965 info = dm_alloc(sizeof(struct integrated_info)); 1966 1967 if (info == NULL) { 1968 ASSERT_CRITICAL(0); 1969 return NULL; 1970 } 1971 1972 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 1973 return info; 1974 1975 dm_free(info); 1976 1977 return NULL; 1978 } 1979 1980 static const struct dc_vbios_funcs vbios_funcs = { 1981 .get_connectors_number = bios_parser_get_connectors_number, 1982 1983 .get_encoder_id = bios_parser_get_encoder_id, 1984 1985 .get_connector_id = bios_parser_get_connector_id, 1986 1987 .get_dst_number = bios_parser_get_dst_number, 1988 1989 .get_src_obj = bios_parser_get_src_obj, 1990 1991 .get_dst_obj = bios_parser_get_dst_obj, 1992 1993 .get_i2c_info = bios_parser_get_i2c_info, 1994 1995 .get_voltage_ddc_info = bios_parser_get_voltage_ddc_info, 1996 1997 .get_thermal_ddc_info = bios_parser_get_thermal_ddc_info, 1998 1999 .get_hpd_info = bios_parser_get_hpd_info, 2000 2001 .get_device_tag = bios_parser_get_device_tag, 2002 2003 .get_firmware_info = bios_parser_get_firmware_info, 2004 2005 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2006 2007 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2008 2009 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2010 2011 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2012 2013 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2014 2015 .is_device_id_supported = bios_parser_is_device_id_supported, 2016 2017 2018 2019 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2020 2021 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2022 2023 2024 /* COMMANDS */ 2025 .encoder_control = bios_parser_encoder_control, 2026 2027 .transmitter_control = bios_parser_transmitter_control, 2028 2029 .enable_crtc = bios_parser_enable_crtc, 2030 2031 .set_pixel_clock = bios_parser_set_pixel_clock, 2032 2033 .set_dce_clock = bios_parser_set_dce_clock, 2034 2035 .program_crtc_timing = bios_parser_program_crtc_timing, 2036 2037 /* .blank_crtc = bios_parser_blank_crtc, */ 2038 2039 .crtc_source_select = bios_parser_crtc_source_select, 2040 2041 /* .external_encoder_control = bios_parser_external_encoder_control, */ 2042 2043 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2044 2045 .post_init = bios_parser_post_init, 2046 2047 .bios_parser_destroy = firmware_parser_destroy, 2048 2049 .get_smu_clock_info = bios_parser_get_smu_clock_info, 2050 }; 2051 2052 static bool bios_parser_construct( 2053 struct bios_parser *bp, 2054 struct bp_init_data *init, 2055 enum dce_version dce_version) 2056 { 2057 uint16_t *rom_header_offset = NULL; 2058 struct atom_rom_header_v2_2 *rom_header = NULL; 2059 struct display_object_info_table_v1_4 *object_info_tbl; 2060 struct atom_data_revision tbl_rev = {0}; 2061 2062 if (!init) 2063 return false; 2064 2065 if (!init->bios) 2066 return false; 2067 2068 bp->base.funcs = &vbios_funcs; 2069 bp->base.bios = init->bios; 2070 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2071 2072 bp->base.ctx = init->ctx; 2073 2074 bp->base.bios_local_image = NULL; 2075 2076 rom_header_offset = 2077 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2078 2079 if (!rom_header_offset) 2080 return false; 2081 2082 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2083 2084 if (!rom_header) 2085 return false; 2086 2087 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2088 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2089 return false; 2090 2091 bp->master_data_tbl = 2092 GET_IMAGE(struct atom_master_data_table_v2_1, 2093 rom_header->masterdatatable_offset); 2094 2095 if (!bp->master_data_tbl) 2096 return false; 2097 2098 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2099 2100 if (!bp->object_info_tbl_offset) 2101 return false; 2102 2103 object_info_tbl = 2104 GET_IMAGE(struct display_object_info_table_v1_4, 2105 bp->object_info_tbl_offset); 2106 2107 if (!object_info_tbl) 2108 return false; 2109 2110 get_atom_data_table_revision(&object_info_tbl->table_header, 2111 &bp->object_info_tbl.revision); 2112 2113 if (bp->object_info_tbl.revision.major == 1 2114 && bp->object_info_tbl.revision.minor >= 4) { 2115 struct display_object_info_table_v1_4 *tbl_v1_4; 2116 2117 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2118 bp->object_info_tbl_offset); 2119 if (!tbl_v1_4) 2120 return false; 2121 2122 bp->object_info_tbl.v1_4 = tbl_v1_4; 2123 } else 2124 return false; 2125 2126 dal_firmware_parser_init_cmd_tbl(bp); 2127 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2128 2129 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2130 2131 return true; 2132 } 2133 2134 struct dc_bios *firmware_parser_create( 2135 struct bp_init_data *init, 2136 enum dce_version dce_version) 2137 { 2138 struct bios_parser *bp = NULL; 2139 2140 bp = dm_alloc(sizeof(struct bios_parser)); 2141 if (!bp) 2142 return NULL; 2143 2144 if (bios_parser_construct(bp, init, dce_version)) 2145 return &bp->base; 2146 2147 dm_free(bp); 2148 return NULL; 2149 } 2150 2151 2152