1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @dcb: pointer to the DC BIOS 489 * @gpio_id: GPIO ID 490 * @info: GpioPin information structure 491 * return: Bios parser result code 492 * note: 493 * to get the GPIO PIN INFO, we need: 494 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 495 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 496 * to get the registerA offset/mask 497 */ 498 static enum bp_result bios_parser_get_gpio_pin_info( 499 struct dc_bios *dcb, 500 uint32_t gpio_id, 501 struct gpio_pin_info *info) 502 { 503 struct bios_parser *bp = BP_FROM_DCB(dcb); 504 struct atom_gpio_pin_lut_v2_1 *header; 505 uint32_t count = 0; 506 uint32_t i = 0; 507 508 if (!DATA_TABLES(gpio_pin_lut)) 509 return BP_RESULT_BADBIOSTABLE; 510 511 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 512 DATA_TABLES(gpio_pin_lut)); 513 if (!header) 514 return BP_RESULT_BADBIOSTABLE; 515 516 if (sizeof(struct atom_common_table_header) + 517 sizeof(struct atom_gpio_pin_assignment) 518 > le16_to_cpu(header->table_header.structuresize)) 519 return BP_RESULT_BADBIOSTABLE; 520 521 if (header->table_header.content_revision != 1) 522 return BP_RESULT_UNSUPPORTED; 523 524 /* Temporary hard code gpio pin info */ 525 #if defined(FOR_SIMNOW_BOOT) 526 { 527 struct atom_gpio_pin_assignment gpio_pin[8] = { 528 {0x5db5, 0, 0, 1, 0}, 529 {0x5db5, 8, 8, 2, 0}, 530 {0x5db5, 0x10, 0x10, 3, 0}, 531 {0x5db5, 0x18, 0x14, 4, 0}, 532 {0x5db5, 0x1A, 0x18, 5, 0}, 533 {0x5db5, 0x1C, 0x1C, 6, 0}, 534 }; 535 536 count = 6; 537 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 538 } 539 #else 540 count = (le16_to_cpu(header->table_header.structuresize) 541 - sizeof(struct atom_common_table_header)) 542 / sizeof(struct atom_gpio_pin_assignment); 543 #endif 544 for (i = 0; i < count; ++i) { 545 if (header->gpio_pin[i].gpio_id != gpio_id) 546 continue; 547 548 info->offset = 549 (uint32_t) le16_to_cpu( 550 header->gpio_pin[i].data_a_reg_index); 551 info->offset_y = info->offset + 2; 552 info->offset_en = info->offset + 1; 553 info->offset_mask = info->offset - 1; 554 555 info->mask = (uint32_t) (1 << 556 header->gpio_pin[i].gpio_bitshift); 557 info->mask_y = info->mask + 2; 558 info->mask_en = info->mask + 1; 559 info->mask_mask = info->mask - 1; 560 561 return BP_RESULT_OK; 562 } 563 564 return BP_RESULT_NORECORD; 565 } 566 567 static struct device_id device_type_from_device_id(uint16_t device_id) 568 { 569 570 struct device_id result_device_id; 571 572 result_device_id.raw_device_tag = device_id; 573 574 switch (device_id) { 575 case ATOM_DISPLAY_LCD1_SUPPORT: 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 result_device_id.enum_id = 1; 578 break; 579 580 case ATOM_DISPLAY_DFP1_SUPPORT: 581 result_device_id.device_type = DEVICE_TYPE_DFP; 582 result_device_id.enum_id = 1; 583 break; 584 585 case ATOM_DISPLAY_DFP2_SUPPORT: 586 result_device_id.device_type = DEVICE_TYPE_DFP; 587 result_device_id.enum_id = 2; 588 break; 589 590 case ATOM_DISPLAY_DFP3_SUPPORT: 591 result_device_id.device_type = DEVICE_TYPE_DFP; 592 result_device_id.enum_id = 3; 593 break; 594 595 case ATOM_DISPLAY_DFP4_SUPPORT: 596 result_device_id.device_type = DEVICE_TYPE_DFP; 597 result_device_id.enum_id = 4; 598 break; 599 600 case ATOM_DISPLAY_DFP5_SUPPORT: 601 result_device_id.device_type = DEVICE_TYPE_DFP; 602 result_device_id.enum_id = 5; 603 break; 604 605 case ATOM_DISPLAY_DFP6_SUPPORT: 606 result_device_id.device_type = DEVICE_TYPE_DFP; 607 result_device_id.enum_id = 6; 608 break; 609 610 default: 611 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 612 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 613 result_device_id.enum_id = 0; 614 } 615 return result_device_id; 616 } 617 618 static enum bp_result bios_parser_get_device_tag( 619 struct dc_bios *dcb, 620 struct graphics_object_id connector_object_id, 621 uint32_t device_tag_index, 622 struct connector_device_tag_info *info) 623 { 624 struct bios_parser *bp = BP_FROM_DCB(dcb); 625 struct atom_display_object_path_v2 *object; 626 627 if (!info) 628 return BP_RESULT_BADINPUT; 629 630 /* getBiosObject will return MXM object */ 631 object = get_bios_object(bp, connector_object_id); 632 633 if (!object) { 634 BREAK_TO_DEBUGGER(); /* Invalid object id */ 635 return BP_RESULT_BADINPUT; 636 } 637 638 info->acpi_device = 0; /* BIOS no longer provides this */ 639 info->dev_id = device_type_from_device_id(object->device_tag); 640 641 return BP_RESULT_OK; 642 } 643 644 static enum bp_result get_ss_info_v4_1( 645 struct bios_parser *bp, 646 uint32_t id, 647 uint32_t index, 648 struct spread_spectrum_info *ss_info) 649 { 650 enum bp_result result = BP_RESULT_OK; 651 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 652 struct atom_smu_info_v3_3 *smu_info = NULL; 653 654 if (!ss_info) 655 return BP_RESULT_BADINPUT; 656 657 if (!DATA_TABLES(dce_info)) 658 return BP_RESULT_BADBIOSTABLE; 659 660 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 661 DATA_TABLES(dce_info)); 662 if (!disp_cntl_tbl) 663 return BP_RESULT_BADBIOSTABLE; 664 665 666 ss_info->type.STEP_AND_DELAY_INFO = false; 667 ss_info->spread_percentage_divider = 1000; 668 /* BIOS no longer uses target clock. Always enable for now */ 669 ss_info->target_clock_range = 0xffffffff; 670 671 switch (id) { 672 case AS_SIGNAL_TYPE_DVI: 673 ss_info->spread_spectrum_percentage = 674 disp_cntl_tbl->dvi_ss_percentage; 675 ss_info->spread_spectrum_range = 676 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 677 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 678 ss_info->type.CENTER_MODE = true; 679 break; 680 case AS_SIGNAL_TYPE_HDMI: 681 ss_info->spread_spectrum_percentage = 682 disp_cntl_tbl->hdmi_ss_percentage; 683 ss_info->spread_spectrum_range = 684 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 685 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 686 ss_info->type.CENTER_MODE = true; 687 break; 688 /* TODO LVDS not support anymore? */ 689 case AS_SIGNAL_TYPE_DISPLAY_PORT: 690 ss_info->spread_spectrum_percentage = 691 disp_cntl_tbl->dp_ss_percentage; 692 ss_info->spread_spectrum_range = 693 disp_cntl_tbl->dp_ss_rate_10hz * 10; 694 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 695 ss_info->type.CENTER_MODE = true; 696 break; 697 case AS_SIGNAL_TYPE_GPU_PLL: 698 /* atom_firmware: DAL only get data from dce_info table. 699 * if data within smu_info is needed for DAL, VBIOS should 700 * copy it into dce_info 701 */ 702 result = BP_RESULT_UNSUPPORTED; 703 break; 704 case AS_SIGNAL_TYPE_XGMI: 705 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 706 DATA_TABLES(smu_info)); 707 if (!smu_info) 708 return BP_RESULT_BADBIOSTABLE; 709 710 ss_info->spread_spectrum_percentage = 711 smu_info->waflclk_ss_percentage; 712 ss_info->spread_spectrum_range = 713 smu_info->gpuclk_ss_rate_10hz * 10; 714 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 715 ss_info->type.CENTER_MODE = true; 716 break; 717 default: 718 result = BP_RESULT_UNSUPPORTED; 719 } 720 721 return result; 722 } 723 724 static enum bp_result get_ss_info_v4_2( 725 struct bios_parser *bp, 726 uint32_t id, 727 uint32_t index, 728 struct spread_spectrum_info *ss_info) 729 { 730 enum bp_result result = BP_RESULT_OK; 731 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 732 struct atom_smu_info_v3_1 *smu_info = NULL; 733 734 if (!ss_info) 735 return BP_RESULT_BADINPUT; 736 737 if (!DATA_TABLES(dce_info)) 738 return BP_RESULT_BADBIOSTABLE; 739 740 if (!DATA_TABLES(smu_info)) 741 return BP_RESULT_BADBIOSTABLE; 742 743 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 744 DATA_TABLES(dce_info)); 745 if (!disp_cntl_tbl) 746 return BP_RESULT_BADBIOSTABLE; 747 748 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 749 if (!smu_info) 750 return BP_RESULT_BADBIOSTABLE; 751 752 ss_info->type.STEP_AND_DELAY_INFO = false; 753 ss_info->spread_percentage_divider = 1000; 754 /* BIOS no longer uses target clock. Always enable for now */ 755 ss_info->target_clock_range = 0xffffffff; 756 757 switch (id) { 758 case AS_SIGNAL_TYPE_DVI: 759 ss_info->spread_spectrum_percentage = 760 disp_cntl_tbl->dvi_ss_percentage; 761 ss_info->spread_spectrum_range = 762 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 763 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 764 ss_info->type.CENTER_MODE = true; 765 break; 766 case AS_SIGNAL_TYPE_HDMI: 767 ss_info->spread_spectrum_percentage = 768 disp_cntl_tbl->hdmi_ss_percentage; 769 ss_info->spread_spectrum_range = 770 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 771 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 772 ss_info->type.CENTER_MODE = true; 773 break; 774 /* TODO LVDS not support anymore? */ 775 case AS_SIGNAL_TYPE_DISPLAY_PORT: 776 ss_info->spread_spectrum_percentage = 777 smu_info->gpuclk_ss_percentage; 778 ss_info->spread_spectrum_range = 779 smu_info->gpuclk_ss_rate_10hz * 10; 780 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 781 ss_info->type.CENTER_MODE = true; 782 break; 783 case AS_SIGNAL_TYPE_GPU_PLL: 784 /* atom_firmware: DAL only get data from dce_info table. 785 * if data within smu_info is needed for DAL, VBIOS should 786 * copy it into dce_info 787 */ 788 result = BP_RESULT_UNSUPPORTED; 789 break; 790 default: 791 result = BP_RESULT_UNSUPPORTED; 792 } 793 794 return result; 795 } 796 797 /** 798 * bios_parser_get_spread_spectrum_info 799 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 800 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 801 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 802 * ver 3.1, 803 * there is only one entry for each signal /ss id. However, there is 804 * no planning of supporting multiple spread Sprectum entry for EverGreen 805 * @dcb: pointer to the DC BIOS 806 * @signal: ASSignalType to be converted to info index 807 * @index: number of entries that match the converted info index 808 * @ss_info: sprectrum information structure, 809 * return: Bios parser result code 810 */ 811 static enum bp_result bios_parser_get_spread_spectrum_info( 812 struct dc_bios *dcb, 813 enum as_signal_type signal, 814 uint32_t index, 815 struct spread_spectrum_info *ss_info) 816 { 817 struct bios_parser *bp = BP_FROM_DCB(dcb); 818 enum bp_result result = BP_RESULT_UNSUPPORTED; 819 struct atom_common_table_header *header; 820 struct atom_data_revision tbl_revision; 821 822 if (!ss_info) /* check for bad input */ 823 return BP_RESULT_BADINPUT; 824 825 if (!DATA_TABLES(dce_info)) 826 return BP_RESULT_UNSUPPORTED; 827 828 header = GET_IMAGE(struct atom_common_table_header, 829 DATA_TABLES(dce_info)); 830 get_atom_data_table_revision(header, &tbl_revision); 831 832 switch (tbl_revision.major) { 833 case 4: 834 switch (tbl_revision.minor) { 835 case 1: 836 return get_ss_info_v4_1(bp, signal, index, ss_info); 837 case 2: 838 case 3: 839 return get_ss_info_v4_2(bp, signal, index, ss_info); 840 default: 841 break; 842 } 843 break; 844 default: 845 break; 846 } 847 /* there can not be more then one entry for SS Info table */ 848 return result; 849 } 850 851 static enum bp_result get_soc_bb_info_v4_4( 852 struct bios_parser *bp, 853 struct bp_soc_bb_info *soc_bb_info) 854 { 855 enum bp_result result = BP_RESULT_OK; 856 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 857 858 if (!soc_bb_info) 859 return BP_RESULT_BADINPUT; 860 861 if (!DATA_TABLES(dce_info)) 862 return BP_RESULT_BADBIOSTABLE; 863 864 if (!DATA_TABLES(smu_info)) 865 return BP_RESULT_BADBIOSTABLE; 866 867 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 868 DATA_TABLES(dce_info)); 869 if (!disp_cntl_tbl) 870 return BP_RESULT_BADBIOSTABLE; 871 872 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 873 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 874 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 875 876 return result; 877 } 878 879 static enum bp_result bios_parser_get_soc_bb_info( 880 struct dc_bios *dcb, 881 struct bp_soc_bb_info *soc_bb_info) 882 { 883 struct bios_parser *bp = BP_FROM_DCB(dcb); 884 enum bp_result result = BP_RESULT_UNSUPPORTED; 885 struct atom_common_table_header *header; 886 struct atom_data_revision tbl_revision; 887 888 if (!soc_bb_info) /* check for bad input */ 889 return BP_RESULT_BADINPUT; 890 891 if (!DATA_TABLES(dce_info)) 892 return BP_RESULT_UNSUPPORTED; 893 894 header = GET_IMAGE(struct atom_common_table_header, 895 DATA_TABLES(dce_info)); 896 get_atom_data_table_revision(header, &tbl_revision); 897 898 switch (tbl_revision.major) { 899 case 4: 900 switch (tbl_revision.minor) { 901 case 1: 902 case 2: 903 case 3: 904 break; 905 case 4: 906 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 907 break; 908 default: 909 break; 910 } 911 break; 912 default: 913 break; 914 } 915 916 return result; 917 } 918 919 static enum bp_result get_disp_caps_v4_1( 920 struct bios_parser *bp, 921 uint8_t *dce_caps) 922 { 923 enum bp_result result = BP_RESULT_OK; 924 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 925 926 if (!dce_caps) 927 return BP_RESULT_BADINPUT; 928 929 if (!DATA_TABLES(dce_info)) 930 return BP_RESULT_BADBIOSTABLE; 931 932 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 933 DATA_TABLES(dce_info)); 934 935 if (!disp_cntl_tbl) 936 return BP_RESULT_BADBIOSTABLE; 937 938 *dce_caps = disp_cntl_tbl->display_caps; 939 940 return result; 941 } 942 943 static enum bp_result get_disp_caps_v4_2( 944 struct bios_parser *bp, 945 uint8_t *dce_caps) 946 { 947 enum bp_result result = BP_RESULT_OK; 948 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 949 950 if (!dce_caps) 951 return BP_RESULT_BADINPUT; 952 953 if (!DATA_TABLES(dce_info)) 954 return BP_RESULT_BADBIOSTABLE; 955 956 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 957 DATA_TABLES(dce_info)); 958 959 if (!disp_cntl_tbl) 960 return BP_RESULT_BADBIOSTABLE; 961 962 *dce_caps = disp_cntl_tbl->display_caps; 963 964 return result; 965 } 966 967 static enum bp_result get_disp_caps_v4_3( 968 struct bios_parser *bp, 969 uint8_t *dce_caps) 970 { 971 enum bp_result result = BP_RESULT_OK; 972 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 973 974 if (!dce_caps) 975 return BP_RESULT_BADINPUT; 976 977 if (!DATA_TABLES(dce_info)) 978 return BP_RESULT_BADBIOSTABLE; 979 980 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 981 DATA_TABLES(dce_info)); 982 983 if (!disp_cntl_tbl) 984 return BP_RESULT_BADBIOSTABLE; 985 986 *dce_caps = disp_cntl_tbl->display_caps; 987 988 return result; 989 } 990 991 static enum bp_result get_disp_caps_v4_4( 992 struct bios_parser *bp, 993 uint8_t *dce_caps) 994 { 995 enum bp_result result = BP_RESULT_OK; 996 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 997 998 if (!dce_caps) 999 return BP_RESULT_BADINPUT; 1000 1001 if (!DATA_TABLES(dce_info)) 1002 return BP_RESULT_BADBIOSTABLE; 1003 1004 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1005 DATA_TABLES(dce_info)); 1006 1007 if (!disp_cntl_tbl) 1008 return BP_RESULT_BADBIOSTABLE; 1009 1010 *dce_caps = disp_cntl_tbl->display_caps; 1011 1012 return result; 1013 } 1014 1015 static enum bp_result bios_parser_get_lttpr_interop( 1016 struct dc_bios *dcb, 1017 uint8_t *dce_caps) 1018 { 1019 struct bios_parser *bp = BP_FROM_DCB(dcb); 1020 enum bp_result result = BP_RESULT_UNSUPPORTED; 1021 struct atom_common_table_header *header; 1022 struct atom_data_revision tbl_revision; 1023 1024 if (!DATA_TABLES(dce_info)) 1025 return BP_RESULT_UNSUPPORTED; 1026 1027 header = GET_IMAGE(struct atom_common_table_header, 1028 DATA_TABLES(dce_info)); 1029 get_atom_data_table_revision(header, &tbl_revision); 1030 switch (tbl_revision.major) { 1031 case 4: 1032 switch (tbl_revision.minor) { 1033 case 1: 1034 result = get_disp_caps_v4_1(bp, dce_caps); 1035 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1036 break; 1037 case 2: 1038 result = get_disp_caps_v4_2(bp, dce_caps); 1039 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1040 break; 1041 case 3: 1042 result = get_disp_caps_v4_3(bp, dce_caps); 1043 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1044 break; 1045 case 4: 1046 result = get_disp_caps_v4_4(bp, dce_caps); 1047 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1048 break; 1049 default: 1050 break; 1051 } 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 return result; 1058 } 1059 1060 static enum bp_result bios_parser_get_lttpr_caps( 1061 struct dc_bios *dcb, 1062 uint8_t *dce_caps) 1063 { 1064 struct bios_parser *bp = BP_FROM_DCB(dcb); 1065 enum bp_result result = BP_RESULT_UNSUPPORTED; 1066 struct atom_common_table_header *header; 1067 struct atom_data_revision tbl_revision; 1068 1069 if (!DATA_TABLES(dce_info)) 1070 return BP_RESULT_UNSUPPORTED; 1071 1072 header = GET_IMAGE(struct atom_common_table_header, 1073 DATA_TABLES(dce_info)); 1074 get_atom_data_table_revision(header, &tbl_revision); 1075 switch (tbl_revision.major) { 1076 case 4: 1077 switch (tbl_revision.minor) { 1078 case 1: 1079 result = get_disp_caps_v4_1(bp, dce_caps); 1080 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1081 break; 1082 case 2: 1083 result = get_disp_caps_v4_2(bp, dce_caps); 1084 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1085 break; 1086 case 3: 1087 result = get_disp_caps_v4_3(bp, dce_caps); 1088 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1089 break; 1090 case 4: 1091 result = get_disp_caps_v4_4(bp, dce_caps); 1092 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1093 break; 1094 default: 1095 break; 1096 } 1097 break; 1098 default: 1099 break; 1100 } 1101 1102 return result; 1103 } 1104 1105 static enum bp_result get_embedded_panel_info_v2_1( 1106 struct bios_parser *bp, 1107 struct embedded_panel_info *info) 1108 { 1109 struct lcd_info_v2_1 *lvds; 1110 1111 if (!info) 1112 return BP_RESULT_BADINPUT; 1113 1114 if (!DATA_TABLES(lcd_info)) 1115 return BP_RESULT_UNSUPPORTED; 1116 1117 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1118 1119 if (!lvds) 1120 return BP_RESULT_BADBIOSTABLE; 1121 1122 /* TODO: previous vv1_3, should v2_1 */ 1123 if (!((lvds->table_header.format_revision == 2) 1124 && (lvds->table_header.content_revision >= 1))) 1125 return BP_RESULT_UNSUPPORTED; 1126 1127 memset(info, 0, sizeof(struct embedded_panel_info)); 1128 1129 /* We need to convert from 10KHz units into KHz units */ 1130 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1131 /* usHActive does not include borders, according to VBIOS team */ 1132 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1133 /* usHBlanking_Time includes borders, so we should really be 1134 * subtractingborders duing this translation, but LVDS generally 1135 * doesn't have borders, so we should be okay leaving this as is for 1136 * now. May need to revisit if we ever have LVDS with borders 1137 */ 1138 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1139 /* usVActive does not include borders, according to VBIOS team*/ 1140 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1141 /* usVBlanking_Time includes borders, so we should really be 1142 * subtracting borders duing this translation, but LVDS generally 1143 * doesn't have borders, so we should be okay leaving this as is for 1144 * now. May need to revisit if we ever have LVDS with borders 1145 */ 1146 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1147 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1148 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1149 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1150 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1151 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1152 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1153 1154 /* not provided by VBIOS */ 1155 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1156 1157 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1158 & ATOM_HSYNC_POLARITY); 1159 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1160 & ATOM_VSYNC_POLARITY); 1161 1162 /* not provided by VBIOS */ 1163 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1164 1165 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1166 & ATOM_H_REPLICATIONBY2); 1167 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1168 & ATOM_V_REPLICATIONBY2); 1169 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1170 & ATOM_COMPOSITESYNC); 1171 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1172 1173 /* not provided by VBIOS*/ 1174 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1175 /* not provided by VBIOS*/ 1176 info->ss_id = 0; 1177 1178 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1179 1180 return BP_RESULT_OK; 1181 } 1182 1183 static enum bp_result bios_parser_get_embedded_panel_info( 1184 struct dc_bios *dcb, 1185 struct embedded_panel_info *info) 1186 { 1187 struct bios_parser 1188 *bp = BP_FROM_DCB(dcb); 1189 struct atom_common_table_header *header; 1190 struct atom_data_revision tbl_revision; 1191 1192 if (!DATA_TABLES(lcd_info)) 1193 return BP_RESULT_FAILURE; 1194 1195 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1196 1197 if (!header) 1198 return BP_RESULT_BADBIOSTABLE; 1199 1200 get_atom_data_table_revision(header, &tbl_revision); 1201 1202 switch (tbl_revision.major) { 1203 case 2: 1204 switch (tbl_revision.minor) { 1205 case 1: 1206 return get_embedded_panel_info_v2_1(bp, info); 1207 default: 1208 break; 1209 } 1210 break; 1211 default: 1212 break; 1213 } 1214 1215 return BP_RESULT_FAILURE; 1216 } 1217 1218 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1219 { 1220 enum dal_device_type device_type = device_id.device_type; 1221 uint32_t enum_id = device_id.enum_id; 1222 1223 switch (device_type) { 1224 case DEVICE_TYPE_LCD: 1225 switch (enum_id) { 1226 case 1: 1227 return ATOM_DISPLAY_LCD1_SUPPORT; 1228 default: 1229 break; 1230 } 1231 break; 1232 case DEVICE_TYPE_DFP: 1233 switch (enum_id) { 1234 case 1: 1235 return ATOM_DISPLAY_DFP1_SUPPORT; 1236 case 2: 1237 return ATOM_DISPLAY_DFP2_SUPPORT; 1238 case 3: 1239 return ATOM_DISPLAY_DFP3_SUPPORT; 1240 case 4: 1241 return ATOM_DISPLAY_DFP4_SUPPORT; 1242 case 5: 1243 return ATOM_DISPLAY_DFP5_SUPPORT; 1244 case 6: 1245 return ATOM_DISPLAY_DFP6_SUPPORT; 1246 default: 1247 break; 1248 } 1249 break; 1250 default: 1251 break; 1252 } 1253 1254 /* Unidentified device ID, return empty support mask. */ 1255 return 0; 1256 } 1257 1258 static bool bios_parser_is_device_id_supported( 1259 struct dc_bios *dcb, 1260 struct device_id id) 1261 { 1262 struct bios_parser *bp = BP_FROM_DCB(dcb); 1263 1264 uint32_t mask = get_support_mask_for_device_id(id); 1265 1266 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1267 mask) != 0; 1268 } 1269 1270 static uint32_t bios_parser_get_ss_entry_number( 1271 struct dc_bios *dcb, 1272 enum as_signal_type signal) 1273 { 1274 /* TODO: DAL2 atomfirmware implementation does not need this. 1275 * why DAL3 need this? 1276 */ 1277 return 1; 1278 } 1279 1280 static enum bp_result bios_parser_transmitter_control( 1281 struct dc_bios *dcb, 1282 struct bp_transmitter_control *cntl) 1283 { 1284 struct bios_parser *bp = BP_FROM_DCB(dcb); 1285 1286 if (!bp->cmd_tbl.transmitter_control) 1287 return BP_RESULT_FAILURE; 1288 1289 return bp->cmd_tbl.transmitter_control(bp, cntl); 1290 } 1291 1292 static enum bp_result bios_parser_encoder_control( 1293 struct dc_bios *dcb, 1294 struct bp_encoder_control *cntl) 1295 { 1296 struct bios_parser *bp = BP_FROM_DCB(dcb); 1297 1298 if (!bp->cmd_tbl.dig_encoder_control) 1299 return BP_RESULT_FAILURE; 1300 1301 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1302 } 1303 1304 static enum bp_result bios_parser_set_pixel_clock( 1305 struct dc_bios *dcb, 1306 struct bp_pixel_clock_parameters *bp_params) 1307 { 1308 struct bios_parser *bp = BP_FROM_DCB(dcb); 1309 1310 if (!bp->cmd_tbl.set_pixel_clock) 1311 return BP_RESULT_FAILURE; 1312 1313 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1314 } 1315 1316 static enum bp_result bios_parser_set_dce_clock( 1317 struct dc_bios *dcb, 1318 struct bp_set_dce_clock_parameters *bp_params) 1319 { 1320 struct bios_parser *bp = BP_FROM_DCB(dcb); 1321 1322 if (!bp->cmd_tbl.set_dce_clock) 1323 return BP_RESULT_FAILURE; 1324 1325 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1326 } 1327 1328 static enum bp_result bios_parser_program_crtc_timing( 1329 struct dc_bios *dcb, 1330 struct bp_hw_crtc_timing_parameters *bp_params) 1331 { 1332 struct bios_parser *bp = BP_FROM_DCB(dcb); 1333 1334 if (!bp->cmd_tbl.set_crtc_timing) 1335 return BP_RESULT_FAILURE; 1336 1337 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1338 } 1339 1340 static enum bp_result bios_parser_enable_crtc( 1341 struct dc_bios *dcb, 1342 enum controller_id id, 1343 bool enable) 1344 { 1345 struct bios_parser *bp = BP_FROM_DCB(dcb); 1346 1347 if (!bp->cmd_tbl.enable_crtc) 1348 return BP_RESULT_FAILURE; 1349 1350 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1351 } 1352 1353 static enum bp_result bios_parser_enable_disp_power_gating( 1354 struct dc_bios *dcb, 1355 enum controller_id controller_id, 1356 enum bp_pipe_control_action action) 1357 { 1358 struct bios_parser *bp = BP_FROM_DCB(dcb); 1359 1360 if (!bp->cmd_tbl.enable_disp_power_gating) 1361 return BP_RESULT_FAILURE; 1362 1363 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1364 action); 1365 } 1366 1367 static enum bp_result bios_parser_enable_lvtma_control( 1368 struct dc_bios *dcb, 1369 uint8_t uc_pwr_on, 1370 uint8_t panel_instance) 1371 { 1372 struct bios_parser *bp = BP_FROM_DCB(dcb); 1373 1374 if (!bp->cmd_tbl.enable_lvtma_control) 1375 return BP_RESULT_FAILURE; 1376 1377 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1378 } 1379 1380 static bool bios_parser_is_accelerated_mode( 1381 struct dc_bios *dcb) 1382 { 1383 return bios_is_accelerated_mode(dcb); 1384 } 1385 1386 /** 1387 * bios_parser_set_scratch_critical_state - update critical state bit 1388 * in VBIOS scratch register 1389 * 1390 * @dcb: pointer to the DC BIO 1391 * @state: set or reset state 1392 */ 1393 static void bios_parser_set_scratch_critical_state( 1394 struct dc_bios *dcb, 1395 bool state) 1396 { 1397 bios_set_scratch_critical_state(dcb, state); 1398 } 1399 1400 static enum bp_result bios_parser_get_firmware_info( 1401 struct dc_bios *dcb, 1402 struct dc_firmware_info *info) 1403 { 1404 struct bios_parser *bp = BP_FROM_DCB(dcb); 1405 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1406 struct atom_common_table_header *header; 1407 1408 struct atom_data_revision revision; 1409 1410 if (info && DATA_TABLES(firmwareinfo)) { 1411 header = GET_IMAGE(struct atom_common_table_header, 1412 DATA_TABLES(firmwareinfo)); 1413 get_atom_data_table_revision(header, &revision); 1414 switch (revision.major) { 1415 case 3: 1416 switch (revision.minor) { 1417 case 1: 1418 result = get_firmware_info_v3_1(bp, info); 1419 break; 1420 case 2: 1421 case 3: 1422 case 4: 1423 result = get_firmware_info_v3_2(bp, info); 1424 break; 1425 default: 1426 break; 1427 } 1428 break; 1429 default: 1430 break; 1431 } 1432 } 1433 1434 return result; 1435 } 1436 1437 static enum bp_result get_firmware_info_v3_1( 1438 struct bios_parser *bp, 1439 struct dc_firmware_info *info) 1440 { 1441 struct atom_firmware_info_v3_1 *firmware_info; 1442 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1443 1444 if (!info) 1445 return BP_RESULT_BADINPUT; 1446 1447 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1448 DATA_TABLES(firmwareinfo)); 1449 1450 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1451 DATA_TABLES(dce_info)); 1452 1453 if (!firmware_info || !dce_info) 1454 return BP_RESULT_BADBIOSTABLE; 1455 1456 memset(info, 0, sizeof(*info)); 1457 1458 /* Pixel clock pll information. */ 1459 /* We need to convert from 10KHz units into KHz units */ 1460 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1461 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1462 1463 /* 27MHz for Vega10: */ 1464 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1465 1466 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1467 if (info->pll_info.crystal_frequency == 0) 1468 info->pll_info.crystal_frequency = 27000; 1469 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1470 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1471 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1472 1473 /* Get GPU PLL VCO Clock */ 1474 1475 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1476 /* VBIOS gives in 10KHz */ 1477 info->smu_gpu_pll_output_freq = 1478 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1479 } 1480 1481 info->oem_i2c_present = false; 1482 1483 return BP_RESULT_OK; 1484 } 1485 1486 static enum bp_result get_firmware_info_v3_2( 1487 struct bios_parser *bp, 1488 struct dc_firmware_info *info) 1489 { 1490 struct atom_firmware_info_v3_2 *firmware_info; 1491 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1492 struct atom_common_table_header *header; 1493 struct atom_data_revision revision; 1494 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1495 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1496 1497 if (!info) 1498 return BP_RESULT_BADINPUT; 1499 1500 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1501 DATA_TABLES(firmwareinfo)); 1502 1503 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1504 DATA_TABLES(dce_info)); 1505 1506 if (!firmware_info || !dce_info) 1507 return BP_RESULT_BADBIOSTABLE; 1508 1509 memset(info, 0, sizeof(*info)); 1510 1511 header = GET_IMAGE(struct atom_common_table_header, 1512 DATA_TABLES(smu_info)); 1513 get_atom_data_table_revision(header, &revision); 1514 1515 if (revision.minor == 2) { 1516 /* Vega12 */ 1517 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1518 DATA_TABLES(smu_info)); 1519 1520 if (!smu_info_v3_2) 1521 return BP_RESULT_BADBIOSTABLE; 1522 1523 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1524 } else if (revision.minor == 3) { 1525 /* Vega20 */ 1526 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1527 DATA_TABLES(smu_info)); 1528 1529 if (!smu_info_v3_3) 1530 return BP_RESULT_BADBIOSTABLE; 1531 1532 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1533 } 1534 1535 // We need to convert from 10KHz units into KHz units. 1536 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1537 1538 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1539 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1540 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1541 if (info->pll_info.crystal_frequency == 0) { 1542 if (revision.minor == 2) 1543 info->pll_info.crystal_frequency = 27000; 1544 else if (revision.minor == 3) 1545 info->pll_info.crystal_frequency = 100000; 1546 } 1547 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1548 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1549 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1550 1551 /* Get GPU PLL VCO Clock */ 1552 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1553 if (revision.minor == 2) 1554 info->smu_gpu_pll_output_freq = 1555 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1556 else if (revision.minor == 3) 1557 info->smu_gpu_pll_output_freq = 1558 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1559 } 1560 1561 if (firmware_info->board_i2c_feature_id == 0x2) { 1562 info->oem_i2c_present = true; 1563 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1564 } else { 1565 info->oem_i2c_present = false; 1566 } 1567 1568 return BP_RESULT_OK; 1569 } 1570 1571 static enum bp_result bios_parser_get_encoder_cap_info( 1572 struct dc_bios *dcb, 1573 struct graphics_object_id object_id, 1574 struct bp_encoder_cap_info *info) 1575 { 1576 struct bios_parser *bp = BP_FROM_DCB(dcb); 1577 struct atom_display_object_path_v2 *object; 1578 struct atom_encoder_caps_record *record = NULL; 1579 1580 if (!info) 1581 return BP_RESULT_BADINPUT; 1582 1583 object = get_bios_object(bp, object_id); 1584 1585 if (!object) 1586 return BP_RESULT_BADINPUT; 1587 1588 record = get_encoder_cap_record(bp, object); 1589 if (!record) 1590 return BP_RESULT_NORECORD; 1591 1592 info->DP_HBR2_CAP = (record->encodercaps & 1593 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1594 info->DP_HBR2_EN = (record->encodercaps & 1595 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1596 info->DP_HBR3_EN = (record->encodercaps & 1597 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1598 info->HDMI_6GB_EN = (record->encodercaps & 1599 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1600 info->DP_IS_USB_C = (record->encodercaps & 1601 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1602 1603 return BP_RESULT_OK; 1604 } 1605 1606 1607 static struct atom_encoder_caps_record *get_encoder_cap_record( 1608 struct bios_parser *bp, 1609 struct atom_display_object_path_v2 *object) 1610 { 1611 struct atom_common_record_header *header; 1612 uint32_t offset; 1613 1614 if (!object) { 1615 BREAK_TO_DEBUGGER(); /* Invalid object */ 1616 return NULL; 1617 } 1618 1619 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1620 1621 for (;;) { 1622 header = GET_IMAGE(struct atom_common_record_header, offset); 1623 1624 if (!header) 1625 return NULL; 1626 1627 offset += header->record_size; 1628 1629 if (header->record_type == LAST_RECORD_TYPE || 1630 !header->record_size) 1631 break; 1632 1633 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1634 continue; 1635 1636 if (sizeof(struct atom_encoder_caps_record) <= 1637 header->record_size) 1638 return (struct atom_encoder_caps_record *)header; 1639 } 1640 1641 return NULL; 1642 } 1643 1644 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 1645 struct bios_parser *bp, 1646 struct atom_display_object_path_v2 *object) 1647 { 1648 struct atom_common_record_header *header; 1649 uint32_t offset; 1650 1651 if (!object) { 1652 BREAK_TO_DEBUGGER(); /* Invalid object */ 1653 return NULL; 1654 } 1655 1656 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 1657 1658 for (;;) { 1659 header = GET_IMAGE(struct atom_common_record_header, offset); 1660 1661 if (!header) 1662 return NULL; 1663 1664 offset += header->record_size; 1665 1666 if (header->record_type == LAST_RECORD_TYPE || 1667 !header->record_size) 1668 break; 1669 1670 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 1671 continue; 1672 1673 if (sizeof(struct atom_disp_connector_caps_record) <= 1674 header->record_size) 1675 return (struct atom_disp_connector_caps_record *)header; 1676 } 1677 1678 return NULL; 1679 } 1680 1681 static enum bp_result bios_parser_get_disp_connector_caps_info( 1682 struct dc_bios *dcb, 1683 struct graphics_object_id object_id, 1684 struct bp_disp_connector_caps_info *info) 1685 { 1686 struct bios_parser *bp = BP_FROM_DCB(dcb); 1687 struct atom_display_object_path_v2 *object; 1688 struct atom_disp_connector_caps_record *record = NULL; 1689 1690 if (!info) 1691 return BP_RESULT_BADINPUT; 1692 1693 object = get_bios_object(bp, object_id); 1694 1695 if (!object) 1696 return BP_RESULT_BADINPUT; 1697 1698 record = get_disp_connector_caps_record(bp, object); 1699 if (!record) 1700 return BP_RESULT_NORECORD; 1701 1702 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 1703 ? 1 : 0; 1704 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 1705 ? 1 : 0; 1706 1707 return BP_RESULT_OK; 1708 } 1709 1710 static enum bp_result get_vram_info_v23( 1711 struct bios_parser *bp, 1712 struct dc_vram_info *info) 1713 { 1714 struct atom_vram_info_header_v2_3 *info_v23; 1715 enum bp_result result = BP_RESULT_OK; 1716 1717 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1718 DATA_TABLES(vram_info)); 1719 1720 if (info_v23 == NULL) 1721 return BP_RESULT_BADBIOSTABLE; 1722 1723 info->num_chans = info_v23->vram_module[0].channel_num; 1724 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1725 1726 return result; 1727 } 1728 1729 static enum bp_result get_vram_info_v24( 1730 struct bios_parser *bp, 1731 struct dc_vram_info *info) 1732 { 1733 struct atom_vram_info_header_v2_4 *info_v24; 1734 enum bp_result result = BP_RESULT_OK; 1735 1736 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1737 DATA_TABLES(vram_info)); 1738 1739 if (info_v24 == NULL) 1740 return BP_RESULT_BADBIOSTABLE; 1741 1742 info->num_chans = info_v24->vram_module[0].channel_num; 1743 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1744 1745 return result; 1746 } 1747 1748 static enum bp_result get_vram_info_v25( 1749 struct bios_parser *bp, 1750 struct dc_vram_info *info) 1751 { 1752 struct atom_vram_info_header_v2_5 *info_v25; 1753 enum bp_result result = BP_RESULT_OK; 1754 1755 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1756 DATA_TABLES(vram_info)); 1757 1758 if (info_v25 == NULL) 1759 return BP_RESULT_BADBIOSTABLE; 1760 1761 info->num_chans = info_v25->vram_module[0].channel_num; 1762 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1763 1764 return result; 1765 } 1766 1767 /* 1768 * get_integrated_info_v11 1769 * 1770 * @brief 1771 * Get V8 integrated BIOS information 1772 * 1773 * @param 1774 * bios_parser *bp - [in]BIOS parser handler to get master data table 1775 * integrated_info *info - [out] store and output integrated info 1776 * 1777 * @return 1778 * enum bp_result - BP_RESULT_OK if information is available, 1779 * BP_RESULT_BADBIOSTABLE otherwise. 1780 */ 1781 static enum bp_result get_integrated_info_v11( 1782 struct bios_parser *bp, 1783 struct integrated_info *info) 1784 { 1785 struct atom_integrated_system_info_v1_11 *info_v11; 1786 uint32_t i; 1787 1788 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1789 DATA_TABLES(integratedsysteminfo)); 1790 1791 if (info_v11 == NULL) 1792 return BP_RESULT_BADBIOSTABLE; 1793 1794 info->gpu_cap_info = 1795 le32_to_cpu(info_v11->gpucapinfo); 1796 /* 1797 * system_config: Bit[0] = 0 : PCIE power gating disabled 1798 * = 1 : PCIE power gating enabled 1799 * Bit[1] = 0 : DDR-PLL shut down disabled 1800 * = 1 : DDR-PLL shut down enabled 1801 * Bit[2] = 0 : DDR-PLL power down disabled 1802 * = 1 : DDR-PLL power down enabled 1803 */ 1804 info->system_config = le32_to_cpu(info_v11->system_config); 1805 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1806 info->memory_type = info_v11->memorytype; 1807 info->ma_channel_number = info_v11->umachannelnumber; 1808 info->lvds_ss_percentage = 1809 le16_to_cpu(info_v11->lvds_ss_percentage); 1810 info->dp_ss_control = 1811 le16_to_cpu(info_v11->reserved1); 1812 info->lvds_sspread_rate_in_10hz = 1813 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1814 info->hdmi_ss_percentage = 1815 le16_to_cpu(info_v11->hdmi_ss_percentage); 1816 info->hdmi_sspread_rate_in_10hz = 1817 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1818 info->dvi_ss_percentage = 1819 le16_to_cpu(info_v11->dvi_ss_percentage); 1820 info->dvi_sspread_rate_in_10_hz = 1821 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1822 info->lvds_misc = info_v11->lvds_misc; 1823 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1824 info->ext_disp_conn_info.gu_id[i] = 1825 info_v11->extdispconninfo.guid[i]; 1826 } 1827 1828 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1829 info->ext_disp_conn_info.path[i].device_connector_id = 1830 object_id_from_bios_object_id( 1831 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1832 1833 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1834 object_id_from_bios_object_id( 1835 le16_to_cpu( 1836 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1837 1838 info->ext_disp_conn_info.path[i].device_tag = 1839 le16_to_cpu( 1840 info_v11->extdispconninfo.path[i].device_tag); 1841 info->ext_disp_conn_info.path[i].device_acpi_enum = 1842 le16_to_cpu( 1843 info_v11->extdispconninfo.path[i].device_acpi_enum); 1844 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1845 info_v11->extdispconninfo.path[i].auxddclut_index; 1846 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1847 info_v11->extdispconninfo.path[i].hpdlut_index; 1848 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1849 info_v11->extdispconninfo.path[i].channelmapping; 1850 info->ext_disp_conn_info.path[i].caps = 1851 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1852 } 1853 info->ext_disp_conn_info.checksum = 1854 info_v11->extdispconninfo.checksum; 1855 1856 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1857 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1858 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1859 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1860 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1861 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1862 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1863 } 1864 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1865 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1866 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1867 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1868 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1869 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1870 } 1871 1872 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1873 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1874 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1875 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1876 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1877 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1878 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1879 } 1880 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1881 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1882 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1883 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1884 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1885 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1886 } 1887 1888 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1889 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1890 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1891 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1892 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1893 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1894 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1895 } 1896 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1897 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1898 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1899 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1900 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1901 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1902 } 1903 1904 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1905 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1906 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1907 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1908 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1909 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1910 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1911 } 1912 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1913 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1914 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1915 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1916 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1917 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1918 } 1919 1920 1921 /** TODO - review **/ 1922 #if 0 1923 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1924 * 10; 1925 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1926 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1927 1928 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1929 /* Convert [10KHz] into [KHz] */ 1930 info->disp_clk_voltage[i].max_supported_clk = 1931 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1932 ulMaximumSupportedCLK) * 10; 1933 info->disp_clk_voltage[i].voltage_index = 1934 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1935 } 1936 1937 info->boot_up_req_display_vector = 1938 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1939 info->boot_up_nb_voltage = 1940 le16_to_cpu(info_v11->usBootUpNBVoltage); 1941 info->ext_disp_conn_info_offset = 1942 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1943 info->gmc_restore_reset_time = 1944 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1945 info->minimum_n_clk = 1946 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1947 for (i = 1; i < 4; ++i) 1948 info->minimum_n_clk = 1949 info->minimum_n_clk < 1950 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1951 info->minimum_n_clk : le32_to_cpu( 1952 info_v11->ulNbpStateNClkFreq[i]); 1953 1954 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1955 info->ddr_dll_power_up_time = 1956 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1957 info->ddr_pll_power_up_time = 1958 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1959 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1960 info->max_lvds_pclk_freq_in_single_link = 1961 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1962 info->max_lvds_pclk_freq_in_single_link = 1963 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1964 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1965 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1966 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1967 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1968 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1969 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1970 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1971 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1972 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1973 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1974 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1975 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1976 info->lvds_off_to_on_delay_in_4ms = 1977 info_v11->ucLVDSOffToOnDelay_in4Ms; 1978 info->lvds_bit_depth_control_val = 1979 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1980 1981 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1982 /* Convert [10KHz] into [KHz] */ 1983 info->avail_s_clk[i].supported_s_clk = 1984 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1985 * 10; 1986 info->avail_s_clk[i].voltage_index = 1987 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1988 info->avail_s_clk[i].voltage_id = 1989 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1990 } 1991 #endif /* TODO*/ 1992 1993 return BP_RESULT_OK; 1994 } 1995 1996 static enum bp_result get_integrated_info_v2_1( 1997 struct bios_parser *bp, 1998 struct integrated_info *info) 1999 { 2000 struct atom_integrated_system_info_v2_1 *info_v2_1; 2001 uint32_t i; 2002 2003 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2004 DATA_TABLES(integratedsysteminfo)); 2005 2006 if (info_v2_1 == NULL) 2007 return BP_RESULT_BADBIOSTABLE; 2008 2009 info->gpu_cap_info = 2010 le32_to_cpu(info_v2_1->gpucapinfo); 2011 /* 2012 * system_config: Bit[0] = 0 : PCIE power gating disabled 2013 * = 1 : PCIE power gating enabled 2014 * Bit[1] = 0 : DDR-PLL shut down disabled 2015 * = 1 : DDR-PLL shut down enabled 2016 * Bit[2] = 0 : DDR-PLL power down disabled 2017 * = 1 : DDR-PLL power down enabled 2018 */ 2019 info->system_config = le32_to_cpu(info_v2_1->system_config); 2020 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2021 info->memory_type = info_v2_1->memorytype; 2022 info->ma_channel_number = info_v2_1->umachannelnumber; 2023 info->dp_ss_control = 2024 le16_to_cpu(info_v2_1->reserved1); 2025 2026 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2027 info->ext_disp_conn_info.gu_id[i] = 2028 info_v2_1->extdispconninfo.guid[i]; 2029 } 2030 2031 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2032 info->ext_disp_conn_info.path[i].device_connector_id = 2033 object_id_from_bios_object_id( 2034 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2035 2036 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2037 object_id_from_bios_object_id( 2038 le16_to_cpu( 2039 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2040 2041 info->ext_disp_conn_info.path[i].device_tag = 2042 le16_to_cpu( 2043 info_v2_1->extdispconninfo.path[i].device_tag); 2044 info->ext_disp_conn_info.path[i].device_acpi_enum = 2045 le16_to_cpu( 2046 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2047 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2048 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2049 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2050 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2051 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2052 info_v2_1->extdispconninfo.path[i].channelmapping; 2053 info->ext_disp_conn_info.path[i].caps = 2054 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2055 } 2056 2057 info->ext_disp_conn_info.checksum = 2058 info_v2_1->extdispconninfo.checksum; 2059 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2060 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2061 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2062 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2063 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2064 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2065 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2066 } 2067 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2068 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2069 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2070 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2071 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2072 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2073 } 2074 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2075 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2076 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2077 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2078 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2079 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2080 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2081 } 2082 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2083 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2084 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2085 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2086 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2087 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2088 } 2089 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2090 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2091 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2092 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2093 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2094 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2095 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2096 } 2097 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2098 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2099 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2100 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2101 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2102 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2103 } 2104 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2105 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2106 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2107 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2108 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2109 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2110 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2111 } 2112 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2113 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2114 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2115 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2116 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2117 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2118 } 2119 2120 info->edp1_info.edp_backlight_pwm_hz = 2121 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2122 info->edp1_info.edp_ss_percentage = 2123 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2124 info->edp1_info.edp_ss_rate_10hz = 2125 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2126 info->edp1_info.edp_pwr_on_off_delay = 2127 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2128 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2129 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2130 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2131 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2132 info->edp1_info.edp_panel_bpc = 2133 info_v2_1->edp1_info.edp_panel_bpc; 2134 info->edp1_info.edp_bootup_bl_level = 2135 2136 info->edp2_info.edp_backlight_pwm_hz = 2137 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2138 info->edp2_info.edp_ss_percentage = 2139 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2140 info->edp2_info.edp_ss_rate_10hz = 2141 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2142 info->edp2_info.edp_pwr_on_off_delay = 2143 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2144 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2145 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2146 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2147 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2148 info->edp2_info.edp_panel_bpc = 2149 info_v2_1->edp2_info.edp_panel_bpc; 2150 info->edp2_info.edp_bootup_bl_level = 2151 info_v2_1->edp2_info.edp_bootup_bl_level; 2152 2153 return BP_RESULT_OK; 2154 } 2155 2156 /* 2157 * construct_integrated_info 2158 * 2159 * @brief 2160 * Get integrated BIOS information based on table revision 2161 * 2162 * @param 2163 * bios_parser *bp - [in]BIOS parser handler to get master data table 2164 * integrated_info *info - [out] store and output integrated info 2165 * 2166 * @return 2167 * enum bp_result - BP_RESULT_OK if information is available, 2168 * BP_RESULT_BADBIOSTABLE otherwise. 2169 */ 2170 static enum bp_result construct_integrated_info( 2171 struct bios_parser *bp, 2172 struct integrated_info *info) 2173 { 2174 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2175 2176 struct atom_common_table_header *header; 2177 struct atom_data_revision revision; 2178 uint32_t i; 2179 uint32_t j; 2180 2181 if (info && DATA_TABLES(integratedsysteminfo)) { 2182 header = GET_IMAGE(struct atom_common_table_header, 2183 DATA_TABLES(integratedsysteminfo)); 2184 2185 get_atom_data_table_revision(header, &revision); 2186 2187 switch (revision.major) { 2188 case 1: 2189 switch (revision.minor) { 2190 case 11: 2191 case 12: 2192 result = get_integrated_info_v11(bp, info); 2193 break; 2194 default: 2195 return result; 2196 } 2197 break; 2198 case 2: 2199 switch (revision.minor) { 2200 case 1: 2201 result = get_integrated_info_v2_1(bp, info); 2202 break; 2203 default: 2204 return result; 2205 } 2206 break; 2207 default: 2208 return result; 2209 } 2210 } 2211 2212 if (result != BP_RESULT_OK) 2213 return result; 2214 2215 /* Sort voltage table from low to high*/ 2216 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2217 for (j = i; j > 0; --j) { 2218 if (info->disp_clk_voltage[j].max_supported_clk < 2219 info->disp_clk_voltage[j-1].max_supported_clk 2220 ) { 2221 /* swap j and j - 1*/ 2222 swap(info->disp_clk_voltage[j - 1], 2223 info->disp_clk_voltage[j]); 2224 } 2225 } 2226 } 2227 2228 return result; 2229 } 2230 2231 static enum bp_result bios_parser_get_vram_info( 2232 struct dc_bios *dcb, 2233 struct dc_vram_info *info) 2234 { 2235 struct bios_parser *bp = BP_FROM_DCB(dcb); 2236 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2237 struct atom_common_table_header *header; 2238 struct atom_data_revision revision; 2239 2240 if (info && DATA_TABLES(vram_info)) { 2241 header = GET_IMAGE(struct atom_common_table_header, 2242 DATA_TABLES(vram_info)); 2243 2244 get_atom_data_table_revision(header, &revision); 2245 2246 switch (revision.major) { 2247 case 2: 2248 switch (revision.minor) { 2249 case 3: 2250 result = get_vram_info_v23(bp, info); 2251 break; 2252 case 4: 2253 result = get_vram_info_v24(bp, info); 2254 break; 2255 case 5: 2256 result = get_vram_info_v25(bp, info); 2257 break; 2258 default: 2259 break; 2260 } 2261 break; 2262 2263 default: 2264 return result; 2265 } 2266 2267 } 2268 return result; 2269 } 2270 2271 static struct integrated_info *bios_parser_create_integrated_info( 2272 struct dc_bios *dcb) 2273 { 2274 struct bios_parser *bp = BP_FROM_DCB(dcb); 2275 struct integrated_info *info = NULL; 2276 2277 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2278 2279 if (info == NULL) { 2280 ASSERT_CRITICAL(0); 2281 return NULL; 2282 } 2283 2284 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2285 return info; 2286 2287 kfree(info); 2288 2289 return NULL; 2290 } 2291 2292 static enum bp_result update_slot_layout_info( 2293 struct dc_bios *dcb, 2294 unsigned int i, 2295 struct slot_layout_info *slot_layout_info) 2296 { 2297 unsigned int record_offset; 2298 unsigned int j; 2299 struct atom_display_object_path_v2 *object; 2300 struct atom_bracket_layout_record *record; 2301 struct atom_common_record_header *record_header; 2302 enum bp_result result; 2303 struct bios_parser *bp; 2304 struct object_info_table *tbl; 2305 struct display_object_info_table_v1_4 *v1_4; 2306 2307 record = NULL; 2308 record_header = NULL; 2309 result = BP_RESULT_NORECORD; 2310 2311 bp = BP_FROM_DCB(dcb); 2312 tbl = &bp->object_info_tbl; 2313 v1_4 = tbl->v1_4; 2314 2315 object = &v1_4->display_path[i]; 2316 record_offset = (unsigned int) 2317 (object->disp_recordoffset) + 2318 (unsigned int)(bp->object_info_tbl_offset); 2319 2320 for (;;) { 2321 2322 record_header = (struct atom_common_record_header *) 2323 GET_IMAGE(struct atom_common_record_header, 2324 record_offset); 2325 if (record_header == NULL) { 2326 result = BP_RESULT_BADBIOSTABLE; 2327 break; 2328 } 2329 2330 /* the end of the list */ 2331 if (record_header->record_type == 0xff || 2332 record_header->record_size == 0) { 2333 break; 2334 } 2335 2336 if (record_header->record_type == 2337 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2338 sizeof(struct atom_bracket_layout_record) 2339 <= record_header->record_size) { 2340 record = (struct atom_bracket_layout_record *) 2341 (record_header); 2342 result = BP_RESULT_OK; 2343 break; 2344 } 2345 2346 record_offset += record_header->record_size; 2347 } 2348 2349 /* return if the record not found */ 2350 if (result != BP_RESULT_OK) 2351 return result; 2352 2353 /* get slot sizes */ 2354 slot_layout_info->length = record->bracketlen; 2355 slot_layout_info->width = record->bracketwidth; 2356 2357 /* get info for each connector in the slot */ 2358 slot_layout_info->num_of_connectors = record->conn_num; 2359 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2360 slot_layout_info->connectors[j].connector_type = 2361 (enum connector_layout_type) 2362 (record->conn_info[j].connector_type); 2363 switch (record->conn_info[j].connector_type) { 2364 case CONNECTOR_TYPE_DVI_D: 2365 slot_layout_info->connectors[j].connector_type = 2366 CONNECTOR_LAYOUT_TYPE_DVI_D; 2367 slot_layout_info->connectors[j].length = 2368 CONNECTOR_SIZE_DVI; 2369 break; 2370 2371 case CONNECTOR_TYPE_HDMI: 2372 slot_layout_info->connectors[j].connector_type = 2373 CONNECTOR_LAYOUT_TYPE_HDMI; 2374 slot_layout_info->connectors[j].length = 2375 CONNECTOR_SIZE_HDMI; 2376 break; 2377 2378 case CONNECTOR_TYPE_DISPLAY_PORT: 2379 slot_layout_info->connectors[j].connector_type = 2380 CONNECTOR_LAYOUT_TYPE_DP; 2381 slot_layout_info->connectors[j].length = 2382 CONNECTOR_SIZE_DP; 2383 break; 2384 2385 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2386 slot_layout_info->connectors[j].connector_type = 2387 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2388 slot_layout_info->connectors[j].length = 2389 CONNECTOR_SIZE_MINI_DP; 2390 break; 2391 2392 default: 2393 slot_layout_info->connectors[j].connector_type = 2394 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2395 slot_layout_info->connectors[j].length = 2396 CONNECTOR_SIZE_UNKNOWN; 2397 } 2398 2399 slot_layout_info->connectors[j].position = 2400 record->conn_info[j].position; 2401 slot_layout_info->connectors[j].connector_id = 2402 object_id_from_bios_object_id( 2403 record->conn_info[j].connectorobjid); 2404 } 2405 return result; 2406 } 2407 2408 2409 static enum bp_result get_bracket_layout_record( 2410 struct dc_bios *dcb, 2411 unsigned int bracket_layout_id, 2412 struct slot_layout_info *slot_layout_info) 2413 { 2414 unsigned int i; 2415 struct bios_parser *bp = BP_FROM_DCB(dcb); 2416 enum bp_result result; 2417 struct object_info_table *tbl; 2418 struct display_object_info_table_v1_4 *v1_4; 2419 2420 if (slot_layout_info == NULL) { 2421 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2422 return BP_RESULT_BADINPUT; 2423 } 2424 tbl = &bp->object_info_tbl; 2425 v1_4 = tbl->v1_4; 2426 2427 result = BP_RESULT_NORECORD; 2428 for (i = 0; i < v1_4->number_of_path; ++i) { 2429 2430 if (bracket_layout_id == 2431 v1_4->display_path[i].display_objid) { 2432 result = update_slot_layout_info(dcb, i, 2433 slot_layout_info); 2434 break; 2435 } 2436 } 2437 return result; 2438 } 2439 2440 static enum bp_result bios_get_board_layout_info( 2441 struct dc_bios *dcb, 2442 struct board_layout_info *board_layout_info) 2443 { 2444 unsigned int i; 2445 enum bp_result record_result; 2446 2447 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2448 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2449 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2450 0, 0 2451 }; 2452 2453 if (board_layout_info == NULL) { 2454 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2455 return BP_RESULT_BADINPUT; 2456 } 2457 2458 board_layout_info->num_of_slots = 0; 2459 2460 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2461 record_result = get_bracket_layout_record(dcb, 2462 slot_index_to_vbios_id[i], 2463 &board_layout_info->slots[i]); 2464 2465 if (record_result == BP_RESULT_NORECORD && i > 0) 2466 break; /* no more slots present in bios */ 2467 else if (record_result != BP_RESULT_OK) 2468 return record_result; /* fail */ 2469 2470 ++board_layout_info->num_of_slots; 2471 } 2472 2473 /* all data is valid */ 2474 board_layout_info->is_number_of_slots_valid = 1; 2475 board_layout_info->is_slots_size_valid = 1; 2476 board_layout_info->is_connector_offsets_valid = 1; 2477 board_layout_info->is_connector_lengths_valid = 1; 2478 2479 return BP_RESULT_OK; 2480 } 2481 2482 2483 static uint16_t bios_parser_pack_data_tables( 2484 struct dc_bios *dcb, 2485 void *dst) 2486 { 2487 #ifdef PACK_BIOS_DATA 2488 struct bios_parser *bp = BP_FROM_DCB(dcb); 2489 struct atom_rom_header_v2_2 *rom_header = NULL; 2490 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2491 struct atom_common_table_header *data_tbl_header = NULL; 2492 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2493 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2494 struct atom_data_revision tbl_rev = {0}; 2495 uint16_t *rom_header_offset = NULL; 2496 const uint8_t *bios = bp->base.bios; 2497 uint8_t *bios_dst = (uint8_t *)dst; 2498 uint16_t packed_rom_header_offset; 2499 uint16_t packed_masterdatatable_offset; 2500 uint16_t packed_data_tbl_offset; 2501 uint16_t data_tbl_offset; 2502 unsigned int i; 2503 2504 rom_header_offset = 2505 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2506 2507 if (!rom_header_offset) 2508 return 0; 2509 2510 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2511 2512 if (!rom_header) 2513 return 0; 2514 2515 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2516 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2517 return 0; 2518 2519 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2520 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2521 return 0; 2522 2523 packed_rom_header_offset = 2524 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2525 2526 packed_masterdatatable_offset = 2527 packed_rom_header_offset + rom_header->table_header.structuresize; 2528 2529 packed_data_tbl_offset = 2530 packed_masterdatatable_offset + 2531 bp->master_data_tbl->table_header.structuresize; 2532 2533 packed_rom_header = 2534 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2535 2536 packed_master_data_tbl = 2537 (struct atom_master_data_table_v2_1 *)(bios_dst + 2538 packed_masterdatatable_offset); 2539 2540 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2541 2542 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2543 packed_rom_header_offset; 2544 2545 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2546 rom_header->table_header.structuresize); 2547 2548 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2549 2550 memcpy(&packed_master_data_tbl->table_header, 2551 &bp->master_data_tbl->table_header, 2552 sizeof(bp->master_data_tbl->table_header)); 2553 2554 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2555 2556 /* Each data table offset in data table list is 2 bytes, 2557 * we can use that to iterate through listOfdatatables 2558 * without knowing the name of each member. 2559 */ 2560 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2561 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2562 2563 if (data_tbl_offset) { 2564 data_tbl_header = 2565 (struct atom_common_table_header *)(bios + data_tbl_offset); 2566 2567 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2568 data_tbl_header->structuresize); 2569 2570 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2571 packed_data_tbl_offset; 2572 2573 packed_data_tbl_offset += data_tbl_header->structuresize; 2574 } else { 2575 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2576 } 2577 } 2578 return packed_data_tbl_offset; 2579 #endif 2580 // TODO: There is data bytes alignment issue, disable it for now. 2581 return 0; 2582 } 2583 2584 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2585 struct bios_parser *bp, 2586 uint32_t rev_major, 2587 uint32_t rev_minor, 2588 uint16_t *dc_golden_table_ver) 2589 { 2590 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2591 uint32_t dc_golden_offset = 0; 2592 *dc_golden_table_ver = 0; 2593 2594 if (!DATA_TABLES(dce_info)) 2595 return NULL; 2596 2597 /* ver.4.4 or higher */ 2598 switch (rev_major) { 2599 case 4: 2600 switch (rev_minor) { 2601 case 4: 2602 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2603 DATA_TABLES(dce_info)); 2604 if (!disp_cntl_tbl_4_4) 2605 return NULL; 2606 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2607 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2608 break; 2609 } 2610 break; 2611 } 2612 2613 if (!dc_golden_offset) 2614 return NULL; 2615 2616 if (*dc_golden_table_ver != 1) 2617 return NULL; 2618 2619 return GET_IMAGE(struct atom_dc_golden_table_v1, 2620 dc_golden_offset); 2621 } 2622 2623 static enum bp_result bios_get_atom_dc_golden_table( 2624 struct dc_bios *dcb) 2625 { 2626 struct bios_parser *bp = BP_FROM_DCB(dcb); 2627 enum bp_result result = BP_RESULT_OK; 2628 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2629 struct atom_common_table_header *header; 2630 struct atom_data_revision tbl_revision; 2631 uint16_t dc_golden_table_ver = 0; 2632 2633 header = GET_IMAGE(struct atom_common_table_header, 2634 DATA_TABLES(dce_info)); 2635 if (!header) 2636 return BP_RESULT_UNSUPPORTED; 2637 2638 get_atom_data_table_revision(header, &tbl_revision); 2639 2640 atom_dc_golden_table = bios_get_golden_table(bp, 2641 tbl_revision.major, 2642 tbl_revision.minor, 2643 &dc_golden_table_ver); 2644 2645 if (!atom_dc_golden_table) 2646 return BP_RESULT_UNSUPPORTED; 2647 2648 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2649 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2650 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2651 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2652 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2653 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2654 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2655 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2656 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2657 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2658 2659 return result; 2660 } 2661 2662 2663 static const struct dc_vbios_funcs vbios_funcs = { 2664 .get_connectors_number = bios_parser_get_connectors_number, 2665 2666 .get_connector_id = bios_parser_get_connector_id, 2667 2668 .get_src_obj = bios_parser_get_src_obj, 2669 2670 .get_i2c_info = bios_parser_get_i2c_info, 2671 2672 .get_hpd_info = bios_parser_get_hpd_info, 2673 2674 .get_device_tag = bios_parser_get_device_tag, 2675 2676 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2677 2678 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2679 2680 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2681 2682 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2683 2684 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2685 2686 .is_device_id_supported = bios_parser_is_device_id_supported, 2687 2688 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2689 2690 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2691 2692 2693 /* COMMANDS */ 2694 .encoder_control = bios_parser_encoder_control, 2695 2696 .transmitter_control = bios_parser_transmitter_control, 2697 2698 .enable_crtc = bios_parser_enable_crtc, 2699 2700 .set_pixel_clock = bios_parser_set_pixel_clock, 2701 2702 .set_dce_clock = bios_parser_set_dce_clock, 2703 2704 .program_crtc_timing = bios_parser_program_crtc_timing, 2705 2706 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2707 2708 .bios_parser_destroy = firmware_parser_destroy, 2709 2710 .get_board_layout_info = bios_get_board_layout_info, 2711 .pack_data_tables = bios_parser_pack_data_tables, 2712 2713 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2714 2715 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2716 2717 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2718 2719 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 2720 2721 .get_lttpr_caps = bios_parser_get_lttpr_caps, 2722 2723 .get_lttpr_interop = bios_parser_get_lttpr_interop, 2724 }; 2725 2726 static bool bios_parser2_construct( 2727 struct bios_parser *bp, 2728 struct bp_init_data *init, 2729 enum dce_version dce_version) 2730 { 2731 uint16_t *rom_header_offset = NULL; 2732 struct atom_rom_header_v2_2 *rom_header = NULL; 2733 struct display_object_info_table_v1_4 *object_info_tbl; 2734 struct atom_data_revision tbl_rev = {0}; 2735 2736 if (!init) 2737 return false; 2738 2739 if (!init->bios) 2740 return false; 2741 2742 bp->base.funcs = &vbios_funcs; 2743 bp->base.bios = init->bios; 2744 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2745 2746 bp->base.ctx = init->ctx; 2747 2748 bp->base.bios_local_image = NULL; 2749 2750 rom_header_offset = 2751 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2752 2753 if (!rom_header_offset) 2754 return false; 2755 2756 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2757 2758 if (!rom_header) 2759 return false; 2760 2761 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2762 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2763 return false; 2764 2765 bp->master_data_tbl = 2766 GET_IMAGE(struct atom_master_data_table_v2_1, 2767 rom_header->masterdatatable_offset); 2768 2769 if (!bp->master_data_tbl) 2770 return false; 2771 2772 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2773 2774 if (!bp->object_info_tbl_offset) 2775 return false; 2776 2777 object_info_tbl = 2778 GET_IMAGE(struct display_object_info_table_v1_4, 2779 bp->object_info_tbl_offset); 2780 2781 if (!object_info_tbl) 2782 return false; 2783 2784 get_atom_data_table_revision(&object_info_tbl->table_header, 2785 &bp->object_info_tbl.revision); 2786 2787 if (bp->object_info_tbl.revision.major == 1 2788 && bp->object_info_tbl.revision.minor >= 4) { 2789 struct display_object_info_table_v1_4 *tbl_v1_4; 2790 2791 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2792 bp->object_info_tbl_offset); 2793 if (!tbl_v1_4) 2794 return false; 2795 2796 bp->object_info_tbl.v1_4 = tbl_v1_4; 2797 } else 2798 return false; 2799 2800 dal_firmware_parser_init_cmd_tbl(bp); 2801 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2802 2803 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2804 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2805 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2806 2807 return true; 2808 } 2809 2810 struct dc_bios *firmware_parser_create( 2811 struct bp_init_data *init, 2812 enum dce_version dce_version) 2813 { 2814 struct bios_parser *bp = NULL; 2815 2816 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2817 if (!bp) 2818 return NULL; 2819 2820 if (bios_parser2_construct(bp, init, dce_version)) 2821 return &bp->base; 2822 2823 kfree(bp); 2824 return NULL; 2825 } 2826 2827 2828