1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static enum bp_result get_firmware_info_v3_4( 103 struct bios_parser *bp, 104 struct dc_firmware_info *info); 105 106 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 static struct atom_encoder_caps_record *get_encoder_cap_record( 110 struct bios_parser *bp, 111 struct atom_display_object_path_v2 *object); 112 113 #define BIOS_IMAGE_SIZE_OFFSET 2 114 #define BIOS_IMAGE_SIZE_UNIT 512 115 116 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 117 118 static void bios_parser2_destruct(struct bios_parser *bp) 119 { 120 kfree(bp->base.bios_local_image); 121 kfree(bp->base.integrated_info); 122 } 123 124 static void firmware_parser_destroy(struct dc_bios **dcb) 125 { 126 struct bios_parser *bp = BP_FROM_DCB(*dcb); 127 128 if (!bp) { 129 BREAK_TO_DEBUGGER(); 130 return; 131 } 132 133 bios_parser2_destruct(bp); 134 135 kfree(bp); 136 *dcb = NULL; 137 } 138 139 static void get_atom_data_table_revision( 140 struct atom_common_table_header *atom_data_tbl, 141 struct atom_data_revision *tbl_revision) 142 { 143 if (!tbl_revision) 144 return; 145 146 /* initialize the revision to 0 which is invalid revision */ 147 tbl_revision->major = 0; 148 tbl_revision->minor = 0; 149 150 if (!atom_data_tbl) 151 return; 152 153 tbl_revision->major = 154 (uint32_t) atom_data_tbl->format_revision & 0x3f; 155 tbl_revision->minor = 156 (uint32_t) atom_data_tbl->content_revision & 0x3f; 157 } 158 159 /* BIOS oject table displaypath is per connector. 160 * There is extra path not for connector. BIOS fill its encoderid as 0 161 */ 162 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 163 { 164 struct bios_parser *bp = BP_FROM_DCB(dcb); 165 unsigned int count = 0; 166 unsigned int i; 167 168 switch (bp->object_info_tbl.revision.minor) { 169 default: 170 case 4: 171 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 172 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 173 count++; 174 175 break; 176 177 case 5: 178 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 179 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 180 count++; 181 182 break; 183 } 184 return count; 185 } 186 187 static struct graphics_object_id bios_parser_get_connector_id( 188 struct dc_bios *dcb, 189 uint8_t i) 190 { 191 struct bios_parser *bp = BP_FROM_DCB(dcb); 192 struct graphics_object_id object_id = dal_graphics_object_id_init( 193 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 194 struct object_info_table *tbl = &bp->object_info_tbl; 195 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 196 197 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 198 199 switch (bp->object_info_tbl.revision.minor) { 200 default: 201 case 4: 202 if (v1_4->number_of_path > i) { 203 /* If display_objid is generic object id, the encoderObj 204 * /extencoderobjId should be 0 205 */ 206 if (v1_4->display_path[i].encoderobjid != 0 && 207 v1_4->display_path[i].display_objid != 0) 208 object_id = object_id_from_bios_object_id( 209 v1_4->display_path[i].display_objid); 210 } 211 break; 212 213 case 5: 214 if (v1_5->number_of_path > i) { 215 /* If display_objid is generic object id, the encoderObjId 216 * should be 0 217 */ 218 if (v1_5->display_path[i].encoderobjid != 0 && 219 v1_5->display_path[i].display_objid != 0) 220 object_id = object_id_from_bios_object_id( 221 v1_5->display_path[i].display_objid); 222 } 223 break; 224 } 225 return object_id; 226 } 227 228 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 229 struct graphics_object_id object_id, uint32_t index, 230 struct graphics_object_id *src_object_id) 231 { 232 struct bios_parser *bp = BP_FROM_DCB(dcb); 233 unsigned int i; 234 enum bp_result bp_result = BP_RESULT_BADINPUT; 235 struct graphics_object_id obj_id = { 0 }; 236 struct object_info_table *tbl = &bp->object_info_tbl; 237 238 if (!src_object_id) 239 return bp_result; 240 241 switch (object_id.type) { 242 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 243 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 244 */ 245 case OBJECT_TYPE_ENCODER: 246 /* TODO: since num of src must be less than 2. 247 * If found in for loop, should break. 248 * DAL2 implementation may be changed too 249 */ 250 switch (bp->object_info_tbl.revision.minor) { 251 default: 252 case 4: 253 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 254 obj_id = object_id_from_bios_object_id( 255 tbl->v1_4->display_path[i].encoderobjid); 256 if (object_id.type == obj_id.type && 257 object_id.id == obj_id.id && 258 object_id.enum_id == obj_id.enum_id) { 259 *src_object_id = 260 object_id_from_bios_object_id( 261 0x1100); 262 /* break; */ 263 } 264 } 265 bp_result = BP_RESULT_OK; 266 break; 267 268 case 5: 269 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 270 obj_id = object_id_from_bios_object_id( 271 tbl->v1_5->display_path[i].encoderobjid); 272 if (object_id.type == obj_id.type && 273 object_id.id == obj_id.id && 274 object_id.enum_id == obj_id.enum_id) { 275 *src_object_id = 276 object_id_from_bios_object_id( 277 0x1100); 278 /* break; */ 279 } 280 } 281 bp_result = BP_RESULT_OK; 282 break; 283 } 284 break; 285 case OBJECT_TYPE_CONNECTOR: 286 switch (bp->object_info_tbl.revision.minor) { 287 default: 288 case 4: 289 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 290 obj_id = object_id_from_bios_object_id( 291 tbl->v1_4->display_path[i] 292 .display_objid); 293 294 if (object_id.type == obj_id.type && 295 object_id.id == obj_id.id && 296 object_id.enum_id == obj_id.enum_id) { 297 *src_object_id = 298 object_id_from_bios_object_id( 299 tbl->v1_4 300 ->display_path[i] 301 .encoderobjid); 302 /* break; */ 303 } 304 } 305 bp_result = BP_RESULT_OK; 306 break; 307 } 308 bp_result = BP_RESULT_OK; 309 break; 310 case 5: 311 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 312 obj_id = object_id_from_bios_object_id( 313 tbl->v1_5->display_path[i].display_objid); 314 315 if (object_id.type == obj_id.type && 316 object_id.id == obj_id.id && 317 object_id.enum_id == obj_id.enum_id) { 318 *src_object_id = object_id_from_bios_object_id( 319 tbl->v1_5->display_path[i].encoderobjid); 320 /* break; */ 321 } 322 } 323 bp_result = BP_RESULT_OK; 324 break; 325 326 default: 327 bp_result = BP_RESULT_OK; 328 break; 329 } 330 331 return bp_result; 332 } 333 334 /* from graphics_object_id, find display path which includes the object_id */ 335 static struct atom_display_object_path_v2 *get_bios_object( 336 struct bios_parser *bp, 337 struct graphics_object_id id) 338 { 339 unsigned int i; 340 struct graphics_object_id obj_id = {0}; 341 342 switch (id.type) { 343 case OBJECT_TYPE_ENCODER: 344 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 345 obj_id = object_id_from_bios_object_id( 346 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 347 if (id.type == obj_id.type && id.id == obj_id.id 348 && id.enum_id == obj_id.enum_id) 349 return &bp->object_info_tbl.v1_4->display_path[i]; 350 } 351 fallthrough; 352 case OBJECT_TYPE_CONNECTOR: 353 case OBJECT_TYPE_GENERIC: 354 /* Both Generic and Connector Object ID 355 * will be stored on display_objid 356 */ 357 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 358 obj_id = object_id_from_bios_object_id( 359 bp->object_info_tbl.v1_4->display_path[i].display_objid); 360 if (id.type == obj_id.type && id.id == obj_id.id 361 && id.enum_id == obj_id.enum_id) 362 return &bp->object_info_tbl.v1_4->display_path[i]; 363 } 364 fallthrough; 365 default: 366 return NULL; 367 } 368 } 369 370 /* from graphics_object_id, find display path which includes the object_id */ 371 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( 372 struct bios_parser *bp, 373 struct graphics_object_id id) 374 { 375 unsigned int i; 376 struct graphics_object_id obj_id = {0}; 377 378 switch (id.type) { 379 case OBJECT_TYPE_ENCODER: 380 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 381 obj_id = object_id_from_bios_object_id( 382 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 383 if (id.type == obj_id.type && id.id == obj_id.id 384 && id.enum_id == obj_id.enum_id) 385 return &bp->object_info_tbl.v1_5->display_path[i]; 386 } 387 break; 388 389 case OBJECT_TYPE_CONNECTOR: 390 case OBJECT_TYPE_GENERIC: 391 /* Both Generic and Connector Object ID 392 * will be stored on display_objid 393 */ 394 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 395 obj_id = object_id_from_bios_object_id( 396 bp->object_info_tbl.v1_5->display_path[i].display_objid); 397 if (id.type == obj_id.type && id.id == obj_id.id 398 && id.enum_id == obj_id.enum_id) 399 return &bp->object_info_tbl.v1_5->display_path[i]; 400 } 401 break; 402 403 default: 404 return NULL; 405 } 406 407 return NULL; 408 } 409 410 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 411 struct graphics_object_id id, 412 struct graphics_object_i2c_info *info) 413 { 414 uint32_t offset; 415 struct atom_display_object_path_v2 *object; 416 417 struct atom_display_object_path_v3 *object_path_v3; 418 419 struct atom_common_record_header *header; 420 struct atom_i2c_record *record; 421 struct atom_i2c_record dummy_record = {0}; 422 struct bios_parser *bp = BP_FROM_DCB(dcb); 423 424 if (!info) 425 return BP_RESULT_BADINPUT; 426 427 if (id.type == OBJECT_TYPE_GENERIC) { 428 dummy_record.i2c_id = id.id; 429 430 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 431 return BP_RESULT_OK; 432 else 433 return BP_RESULT_NORECORD; 434 } 435 436 switch (bp->object_info_tbl.revision.minor) { 437 case 4: 438 default: 439 object = get_bios_object(bp, id); 440 441 if (!object) 442 return BP_RESULT_BADINPUT; 443 444 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 445 break; 446 case 5: 447 object_path_v3 = get_bios_object_from_path_v3(bp, id); 448 449 if (!object_path_v3) 450 return BP_RESULT_BADINPUT; 451 452 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 453 break; 454 } 455 456 for (;;) { 457 header = GET_IMAGE(struct atom_common_record_header, offset); 458 459 if (!header) 460 return BP_RESULT_BADBIOSTABLE; 461 462 if (header->record_type == LAST_RECORD_TYPE || 463 !header->record_size) 464 break; 465 466 if (header->record_type == ATOM_I2C_RECORD_TYPE 467 && sizeof(struct atom_i2c_record) <= 468 header->record_size) { 469 /* get the I2C info */ 470 record = (struct atom_i2c_record *) header; 471 472 if (get_gpio_i2c_info(bp, record, info) == 473 BP_RESULT_OK) 474 return BP_RESULT_OK; 475 } 476 477 offset += header->record_size; 478 } 479 480 return BP_RESULT_NORECORD; 481 } 482 483 static enum bp_result get_gpio_i2c_info( 484 struct bios_parser *bp, 485 struct atom_i2c_record *record, 486 struct graphics_object_i2c_info *info) 487 { 488 struct atom_gpio_pin_lut_v2_1 *header; 489 uint32_t count = 0; 490 unsigned int table_index = 0; 491 bool find_valid = false; 492 493 if (!info) 494 return BP_RESULT_BADINPUT; 495 496 /* get the GPIO_I2C info */ 497 if (!DATA_TABLES(gpio_pin_lut)) 498 return BP_RESULT_BADBIOSTABLE; 499 500 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 501 DATA_TABLES(gpio_pin_lut)); 502 if (!header) 503 return BP_RESULT_BADBIOSTABLE; 504 505 if (sizeof(struct atom_common_table_header) + 506 sizeof(struct atom_gpio_pin_assignment) > 507 le16_to_cpu(header->table_header.structuresize)) 508 return BP_RESULT_BADBIOSTABLE; 509 510 /* TODO: is version change? */ 511 if (header->table_header.content_revision != 1) 512 return BP_RESULT_UNSUPPORTED; 513 514 /* get data count */ 515 count = (le16_to_cpu(header->table_header.structuresize) 516 - sizeof(struct atom_common_table_header)) 517 / sizeof(struct atom_gpio_pin_assignment); 518 519 for (table_index = 0; table_index < count; table_index++) { 520 if (((record->i2c_id & I2C_HW_CAP) == ( 521 header->gpio_pin[table_index].gpio_id & 522 I2C_HW_CAP)) && 523 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 524 (header->gpio_pin[table_index].gpio_id & 525 I2C_HW_ENGINE_ID_MASK)) && 526 ((record->i2c_id & I2C_HW_LANE_MUX) == 527 (header->gpio_pin[table_index].gpio_id & 528 I2C_HW_LANE_MUX))) { 529 /* still valid */ 530 find_valid = true; 531 break; 532 } 533 } 534 535 /* If we don't find the entry that we are looking for then 536 * we will return BP_Result_BadBiosTable. 537 */ 538 if (find_valid == false) 539 return BP_RESULT_BADBIOSTABLE; 540 541 /* get the GPIO_I2C_INFO */ 542 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 543 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 544 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 545 info->i2c_slave_address = record->i2c_slave_addr; 546 547 /* TODO: check how to get register offset for en, Y, etc. */ 548 info->gpio_info.clk_a_register_index = 549 le16_to_cpu( 550 header->gpio_pin[table_index].data_a_reg_index); 551 info->gpio_info.clk_a_shift = 552 header->gpio_pin[table_index].gpio_bitshift; 553 554 return BP_RESULT_OK; 555 } 556 557 static struct atom_hpd_int_record *get_hpd_record_for_path_v3( 558 struct bios_parser *bp, 559 struct atom_display_object_path_v3 *object) 560 { 561 struct atom_common_record_header *header; 562 uint32_t offset; 563 564 if (!object) { 565 BREAK_TO_DEBUGGER(); /* Invalid object */ 566 return NULL; 567 } 568 569 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 570 571 for (;;) { 572 header = GET_IMAGE(struct atom_common_record_header, offset); 573 574 if (!header) 575 return NULL; 576 577 if (header->record_type == ATOM_RECORD_END_TYPE || 578 !header->record_size) 579 break; 580 581 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 582 && sizeof(struct atom_hpd_int_record) <= 583 header->record_size) 584 return (struct atom_hpd_int_record *) header; 585 586 offset += header->record_size; 587 } 588 589 return NULL; 590 } 591 592 static enum bp_result bios_parser_get_hpd_info( 593 struct dc_bios *dcb, 594 struct graphics_object_id id, 595 struct graphics_object_hpd_info *info) 596 { 597 struct bios_parser *bp = BP_FROM_DCB(dcb); 598 struct atom_display_object_path_v2 *object; 599 struct atom_display_object_path_v3 *object_path_v3; 600 struct atom_hpd_int_record *record = NULL; 601 602 if (!info) 603 return BP_RESULT_BADINPUT; 604 605 switch (bp->object_info_tbl.revision.minor) { 606 case 4: 607 default: 608 object = get_bios_object(bp, id); 609 610 if (!object) 611 return BP_RESULT_BADINPUT; 612 613 record = get_hpd_record(bp, object); 614 615 break; 616 case 5: 617 object_path_v3 = get_bios_object_from_path_v3(bp, id); 618 619 if (!object_path_v3) 620 return BP_RESULT_BADINPUT; 621 622 record = get_hpd_record_for_path_v3(bp, object_path_v3); 623 break; 624 } 625 626 if (record != NULL) { 627 info->hpd_int_gpio_uid = record->pin_id; 628 info->hpd_active = record->plugin_pin_state; 629 return BP_RESULT_OK; 630 } 631 632 return BP_RESULT_NORECORD; 633 } 634 635 static struct atom_hpd_int_record *get_hpd_record( 636 struct bios_parser *bp, 637 struct atom_display_object_path_v2 *object) 638 { 639 struct atom_common_record_header *header; 640 uint32_t offset; 641 642 if (!object) { 643 BREAK_TO_DEBUGGER(); /* Invalid object */ 644 return NULL; 645 } 646 647 offset = le16_to_cpu(object->disp_recordoffset) 648 + bp->object_info_tbl_offset; 649 650 for (;;) { 651 header = GET_IMAGE(struct atom_common_record_header, offset); 652 653 if (!header) 654 return NULL; 655 656 if (header->record_type == LAST_RECORD_TYPE || 657 !header->record_size) 658 break; 659 660 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 661 && sizeof(struct atom_hpd_int_record) <= 662 header->record_size) 663 return (struct atom_hpd_int_record *) header; 664 665 offset += header->record_size; 666 } 667 668 return NULL; 669 } 670 671 /** 672 * bios_parser_get_gpio_pin_info 673 * Get GpioPin information of input gpio id 674 * 675 * @dcb: pointer to the DC BIOS 676 * @gpio_id: GPIO ID 677 * @info: GpioPin information structure 678 * return: Bios parser result code 679 * note: 680 * to get the GPIO PIN INFO, we need: 681 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 682 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 683 * to get the registerA offset/mask 684 */ 685 static enum bp_result bios_parser_get_gpio_pin_info( 686 struct dc_bios *dcb, 687 uint32_t gpio_id, 688 struct gpio_pin_info *info) 689 { 690 struct bios_parser *bp = BP_FROM_DCB(dcb); 691 struct atom_gpio_pin_lut_v2_1 *header; 692 uint32_t count = 0; 693 uint32_t i = 0; 694 695 if (!DATA_TABLES(gpio_pin_lut)) 696 return BP_RESULT_BADBIOSTABLE; 697 698 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 699 DATA_TABLES(gpio_pin_lut)); 700 if (!header) 701 return BP_RESULT_BADBIOSTABLE; 702 703 if (sizeof(struct atom_common_table_header) + 704 sizeof(struct atom_gpio_pin_assignment) 705 > le16_to_cpu(header->table_header.structuresize)) 706 return BP_RESULT_BADBIOSTABLE; 707 708 if (header->table_header.content_revision != 1) 709 return BP_RESULT_UNSUPPORTED; 710 711 /* Temporary hard code gpio pin info */ 712 count = (le16_to_cpu(header->table_header.structuresize) 713 - sizeof(struct atom_common_table_header)) 714 / sizeof(struct atom_gpio_pin_assignment); 715 for (i = 0; i < count; ++i) { 716 if (header->gpio_pin[i].gpio_id != gpio_id) 717 continue; 718 719 info->offset = 720 (uint32_t) le16_to_cpu( 721 header->gpio_pin[i].data_a_reg_index); 722 info->offset_y = info->offset + 2; 723 info->offset_en = info->offset + 1; 724 info->offset_mask = info->offset - 1; 725 726 info->mask = (uint32_t) (1 << 727 header->gpio_pin[i].gpio_bitshift); 728 info->mask_y = info->mask + 2; 729 info->mask_en = info->mask + 1; 730 info->mask_mask = info->mask - 1; 731 732 return BP_RESULT_OK; 733 } 734 735 return BP_RESULT_NORECORD; 736 } 737 738 static struct device_id device_type_from_device_id(uint16_t device_id) 739 { 740 741 struct device_id result_device_id; 742 743 result_device_id.raw_device_tag = device_id; 744 745 switch (device_id) { 746 case ATOM_DISPLAY_LCD1_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_LCD; 748 result_device_id.enum_id = 1; 749 break; 750 751 case ATOM_DISPLAY_LCD2_SUPPORT: 752 result_device_id.device_type = DEVICE_TYPE_LCD; 753 result_device_id.enum_id = 2; 754 break; 755 756 case ATOM_DISPLAY_DFP1_SUPPORT: 757 result_device_id.device_type = DEVICE_TYPE_DFP; 758 result_device_id.enum_id = 1; 759 break; 760 761 case ATOM_DISPLAY_DFP2_SUPPORT: 762 result_device_id.device_type = DEVICE_TYPE_DFP; 763 result_device_id.enum_id = 2; 764 break; 765 766 case ATOM_DISPLAY_DFP3_SUPPORT: 767 result_device_id.device_type = DEVICE_TYPE_DFP; 768 result_device_id.enum_id = 3; 769 break; 770 771 case ATOM_DISPLAY_DFP4_SUPPORT: 772 result_device_id.device_type = DEVICE_TYPE_DFP; 773 result_device_id.enum_id = 4; 774 break; 775 776 case ATOM_DISPLAY_DFP5_SUPPORT: 777 result_device_id.device_type = DEVICE_TYPE_DFP; 778 result_device_id.enum_id = 5; 779 break; 780 781 case ATOM_DISPLAY_DFP6_SUPPORT: 782 result_device_id.device_type = DEVICE_TYPE_DFP; 783 result_device_id.enum_id = 6; 784 break; 785 786 default: 787 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 788 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 789 result_device_id.enum_id = 0; 790 } 791 return result_device_id; 792 } 793 794 static enum bp_result bios_parser_get_device_tag( 795 struct dc_bios *dcb, 796 struct graphics_object_id connector_object_id, 797 uint32_t device_tag_index, 798 struct connector_device_tag_info *info) 799 { 800 struct bios_parser *bp = BP_FROM_DCB(dcb); 801 struct atom_display_object_path_v2 *object; 802 803 struct atom_display_object_path_v3 *object_path_v3; 804 805 806 if (!info) 807 return BP_RESULT_BADINPUT; 808 809 switch (bp->object_info_tbl.revision.minor) { 810 case 4: 811 default: 812 /* getBiosObject will return MXM object */ 813 object = get_bios_object(bp, connector_object_id); 814 815 if (!object) { 816 BREAK_TO_DEBUGGER(); /* Invalid object id */ 817 return BP_RESULT_BADINPUT; 818 } 819 820 info->acpi_device = 0; /* BIOS no longer provides this */ 821 info->dev_id = device_type_from_device_id(object->device_tag); 822 break; 823 case 5: 824 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 825 826 if (!object_path_v3) { 827 BREAK_TO_DEBUGGER(); /* Invalid object id */ 828 return BP_RESULT_BADINPUT; 829 } 830 info->acpi_device = 0; /* BIOS no longer provides this */ 831 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 832 break; 833 } 834 835 return BP_RESULT_OK; 836 } 837 838 static enum bp_result get_ss_info_v4_1( 839 struct bios_parser *bp, 840 uint32_t id, 841 uint32_t index, 842 struct spread_spectrum_info *ss_info) 843 { 844 enum bp_result result = BP_RESULT_OK; 845 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 846 struct atom_smu_info_v3_3 *smu_info = NULL; 847 848 if (!ss_info) 849 return BP_RESULT_BADINPUT; 850 851 if (!DATA_TABLES(dce_info)) 852 return BP_RESULT_BADBIOSTABLE; 853 854 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 855 DATA_TABLES(dce_info)); 856 if (!disp_cntl_tbl) 857 return BP_RESULT_BADBIOSTABLE; 858 859 860 ss_info->type.STEP_AND_DELAY_INFO = false; 861 ss_info->spread_percentage_divider = 1000; 862 /* BIOS no longer uses target clock. Always enable for now */ 863 ss_info->target_clock_range = 0xffffffff; 864 865 switch (id) { 866 case AS_SIGNAL_TYPE_DVI: 867 ss_info->spread_spectrum_percentage = 868 disp_cntl_tbl->dvi_ss_percentage; 869 ss_info->spread_spectrum_range = 870 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 871 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 872 ss_info->type.CENTER_MODE = true; 873 break; 874 case AS_SIGNAL_TYPE_HDMI: 875 ss_info->spread_spectrum_percentage = 876 disp_cntl_tbl->hdmi_ss_percentage; 877 ss_info->spread_spectrum_range = 878 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 879 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 880 ss_info->type.CENTER_MODE = true; 881 break; 882 /* TODO LVDS not support anymore? */ 883 case AS_SIGNAL_TYPE_DISPLAY_PORT: 884 ss_info->spread_spectrum_percentage = 885 disp_cntl_tbl->dp_ss_percentage; 886 ss_info->spread_spectrum_range = 887 disp_cntl_tbl->dp_ss_rate_10hz * 10; 888 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 889 ss_info->type.CENTER_MODE = true; 890 break; 891 case AS_SIGNAL_TYPE_GPU_PLL: 892 /* atom_firmware: DAL only get data from dce_info table. 893 * if data within smu_info is needed for DAL, VBIOS should 894 * copy it into dce_info 895 */ 896 result = BP_RESULT_UNSUPPORTED; 897 break; 898 case AS_SIGNAL_TYPE_XGMI: 899 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 900 DATA_TABLES(smu_info)); 901 if (!smu_info) 902 return BP_RESULT_BADBIOSTABLE; 903 904 ss_info->spread_spectrum_percentage = 905 smu_info->waflclk_ss_percentage; 906 ss_info->spread_spectrum_range = 907 smu_info->gpuclk_ss_rate_10hz * 10; 908 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 909 ss_info->type.CENTER_MODE = true; 910 break; 911 default: 912 result = BP_RESULT_UNSUPPORTED; 913 } 914 915 return result; 916 } 917 918 static enum bp_result get_ss_info_v4_2( 919 struct bios_parser *bp, 920 uint32_t id, 921 uint32_t index, 922 struct spread_spectrum_info *ss_info) 923 { 924 enum bp_result result = BP_RESULT_OK; 925 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 926 struct atom_smu_info_v3_1 *smu_info = NULL; 927 928 if (!ss_info) 929 return BP_RESULT_BADINPUT; 930 931 if (!DATA_TABLES(dce_info)) 932 return BP_RESULT_BADBIOSTABLE; 933 934 if (!DATA_TABLES(smu_info)) 935 return BP_RESULT_BADBIOSTABLE; 936 937 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 938 DATA_TABLES(dce_info)); 939 if (!disp_cntl_tbl) 940 return BP_RESULT_BADBIOSTABLE; 941 942 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 943 if (!smu_info) 944 return BP_RESULT_BADBIOSTABLE; 945 946 ss_info->type.STEP_AND_DELAY_INFO = false; 947 ss_info->spread_percentage_divider = 1000; 948 /* BIOS no longer uses target clock. Always enable for now */ 949 ss_info->target_clock_range = 0xffffffff; 950 951 switch (id) { 952 case AS_SIGNAL_TYPE_DVI: 953 ss_info->spread_spectrum_percentage = 954 disp_cntl_tbl->dvi_ss_percentage; 955 ss_info->spread_spectrum_range = 956 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 957 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 958 ss_info->type.CENTER_MODE = true; 959 break; 960 case AS_SIGNAL_TYPE_HDMI: 961 ss_info->spread_spectrum_percentage = 962 disp_cntl_tbl->hdmi_ss_percentage; 963 ss_info->spread_spectrum_range = 964 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 965 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 966 ss_info->type.CENTER_MODE = true; 967 break; 968 /* TODO LVDS not support anymore? */ 969 case AS_SIGNAL_TYPE_DISPLAY_PORT: 970 ss_info->spread_spectrum_percentage = 971 smu_info->gpuclk_ss_percentage; 972 ss_info->spread_spectrum_range = 973 smu_info->gpuclk_ss_rate_10hz * 10; 974 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 975 ss_info->type.CENTER_MODE = true; 976 break; 977 case AS_SIGNAL_TYPE_GPU_PLL: 978 /* atom_firmware: DAL only get data from dce_info table. 979 * if data within smu_info is needed for DAL, VBIOS should 980 * copy it into dce_info 981 */ 982 result = BP_RESULT_UNSUPPORTED; 983 break; 984 default: 985 result = BP_RESULT_UNSUPPORTED; 986 } 987 988 return result; 989 } 990 991 static enum bp_result get_ss_info_v4_5( 992 struct bios_parser *bp, 993 uint32_t id, 994 uint32_t index, 995 struct spread_spectrum_info *ss_info) 996 { 997 enum bp_result result = BP_RESULT_OK; 998 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 999 1000 if (!ss_info) 1001 return BP_RESULT_BADINPUT; 1002 1003 if (!DATA_TABLES(dce_info)) 1004 return BP_RESULT_BADBIOSTABLE; 1005 1006 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1007 DATA_TABLES(dce_info)); 1008 if (!disp_cntl_tbl) 1009 return BP_RESULT_BADBIOSTABLE; 1010 1011 ss_info->type.STEP_AND_DELAY_INFO = false; 1012 ss_info->spread_percentage_divider = 1000; 1013 /* BIOS no longer uses target clock. Always enable for now */ 1014 ss_info->target_clock_range = 0xffffffff; 1015 1016 switch (id) { 1017 case AS_SIGNAL_TYPE_DVI: 1018 ss_info->spread_spectrum_percentage = 1019 disp_cntl_tbl->dvi_ss_percentage; 1020 ss_info->spread_spectrum_range = 1021 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1022 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1023 ss_info->type.CENTER_MODE = true; 1024 break; 1025 case AS_SIGNAL_TYPE_HDMI: 1026 ss_info->spread_spectrum_percentage = 1027 disp_cntl_tbl->hdmi_ss_percentage; 1028 ss_info->spread_spectrum_range = 1029 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1030 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1031 ss_info->type.CENTER_MODE = true; 1032 break; 1033 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1034 ss_info->spread_spectrum_percentage = 1035 disp_cntl_tbl->dp_ss_percentage; 1036 ss_info->spread_spectrum_range = 1037 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1038 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1039 ss_info->type.CENTER_MODE = true; 1040 break; 1041 case AS_SIGNAL_TYPE_GPU_PLL: 1042 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1043 * SMU Display PLL supposed to be without spread. 1044 * Better place for it would be in atom_display_controller_info_v4_5 table. 1045 */ 1046 result = BP_RESULT_UNSUPPORTED; 1047 break; 1048 default: 1049 result = BP_RESULT_UNSUPPORTED; 1050 break; 1051 } 1052 1053 return result; 1054 } 1055 1056 /** 1057 * bios_parser_get_spread_spectrum_info 1058 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1059 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1060 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1061 * ver 3.1, 1062 * there is only one entry for each signal /ss id. However, there is 1063 * no planning of supporting multiple spread Sprectum entry for EverGreen 1064 * @dcb: pointer to the DC BIOS 1065 * @signal: ASSignalType to be converted to info index 1066 * @index: number of entries that match the converted info index 1067 * @ss_info: sprectrum information structure, 1068 * return: Bios parser result code 1069 */ 1070 static enum bp_result bios_parser_get_spread_spectrum_info( 1071 struct dc_bios *dcb, 1072 enum as_signal_type signal, 1073 uint32_t index, 1074 struct spread_spectrum_info *ss_info) 1075 { 1076 struct bios_parser *bp = BP_FROM_DCB(dcb); 1077 enum bp_result result = BP_RESULT_UNSUPPORTED; 1078 struct atom_common_table_header *header; 1079 struct atom_data_revision tbl_revision; 1080 1081 if (!ss_info) /* check for bad input */ 1082 return BP_RESULT_BADINPUT; 1083 1084 if (!DATA_TABLES(dce_info)) 1085 return BP_RESULT_UNSUPPORTED; 1086 1087 header = GET_IMAGE(struct atom_common_table_header, 1088 DATA_TABLES(dce_info)); 1089 get_atom_data_table_revision(header, &tbl_revision); 1090 1091 switch (tbl_revision.major) { 1092 case 4: 1093 switch (tbl_revision.minor) { 1094 case 1: 1095 return get_ss_info_v4_1(bp, signal, index, ss_info); 1096 case 2: 1097 case 3: 1098 case 4: 1099 return get_ss_info_v4_2(bp, signal, index, ss_info); 1100 case 5: 1101 return get_ss_info_v4_5(bp, signal, index, ss_info); 1102 1103 default: 1104 ASSERT(0); 1105 break; 1106 } 1107 break; 1108 default: 1109 break; 1110 } 1111 /* there can not be more then one entry for SS Info table */ 1112 return result; 1113 } 1114 1115 static enum bp_result get_soc_bb_info_v4_4( 1116 struct bios_parser *bp, 1117 struct bp_soc_bb_info *soc_bb_info) 1118 { 1119 enum bp_result result = BP_RESULT_OK; 1120 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1121 1122 if (!soc_bb_info) 1123 return BP_RESULT_BADINPUT; 1124 1125 if (!DATA_TABLES(dce_info)) 1126 return BP_RESULT_BADBIOSTABLE; 1127 1128 if (!DATA_TABLES(smu_info)) 1129 return BP_RESULT_BADBIOSTABLE; 1130 1131 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1132 DATA_TABLES(dce_info)); 1133 if (!disp_cntl_tbl) 1134 return BP_RESULT_BADBIOSTABLE; 1135 1136 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1137 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1138 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1139 1140 return result; 1141 } 1142 1143 static enum bp_result get_soc_bb_info_v4_5( 1144 struct bios_parser *bp, 1145 struct bp_soc_bb_info *soc_bb_info) 1146 { 1147 enum bp_result result = BP_RESULT_OK; 1148 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1149 1150 if (!soc_bb_info) 1151 return BP_RESULT_BADINPUT; 1152 1153 if (!DATA_TABLES(dce_info)) 1154 return BP_RESULT_BADBIOSTABLE; 1155 1156 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1157 DATA_TABLES(dce_info)); 1158 if (!disp_cntl_tbl) 1159 return BP_RESULT_BADBIOSTABLE; 1160 1161 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1162 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1163 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1164 1165 return result; 1166 } 1167 1168 static enum bp_result bios_parser_get_soc_bb_info( 1169 struct dc_bios *dcb, 1170 struct bp_soc_bb_info *soc_bb_info) 1171 { 1172 struct bios_parser *bp = BP_FROM_DCB(dcb); 1173 enum bp_result result = BP_RESULT_UNSUPPORTED; 1174 struct atom_common_table_header *header; 1175 struct atom_data_revision tbl_revision; 1176 1177 if (!soc_bb_info) /* check for bad input */ 1178 return BP_RESULT_BADINPUT; 1179 1180 if (!DATA_TABLES(dce_info)) 1181 return BP_RESULT_UNSUPPORTED; 1182 1183 header = GET_IMAGE(struct atom_common_table_header, 1184 DATA_TABLES(dce_info)); 1185 get_atom_data_table_revision(header, &tbl_revision); 1186 1187 switch (tbl_revision.major) { 1188 case 4: 1189 switch (tbl_revision.minor) { 1190 case 1: 1191 case 2: 1192 case 3: 1193 break; 1194 case 4: 1195 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1196 break; 1197 case 5: 1198 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1199 break; 1200 default: 1201 break; 1202 } 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 return result; 1209 } 1210 1211 static enum bp_result get_disp_caps_v4_1( 1212 struct bios_parser *bp, 1213 uint8_t *dce_caps) 1214 { 1215 enum bp_result result = BP_RESULT_OK; 1216 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1217 1218 if (!dce_caps) 1219 return BP_RESULT_BADINPUT; 1220 1221 if (!DATA_TABLES(dce_info)) 1222 return BP_RESULT_BADBIOSTABLE; 1223 1224 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1225 DATA_TABLES(dce_info)); 1226 1227 if (!disp_cntl_tbl) 1228 return BP_RESULT_BADBIOSTABLE; 1229 1230 *dce_caps = disp_cntl_tbl->display_caps; 1231 1232 return result; 1233 } 1234 1235 static enum bp_result get_disp_caps_v4_2( 1236 struct bios_parser *bp, 1237 uint8_t *dce_caps) 1238 { 1239 enum bp_result result = BP_RESULT_OK; 1240 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1241 1242 if (!dce_caps) 1243 return BP_RESULT_BADINPUT; 1244 1245 if (!DATA_TABLES(dce_info)) 1246 return BP_RESULT_BADBIOSTABLE; 1247 1248 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1249 DATA_TABLES(dce_info)); 1250 1251 if (!disp_cntl_tbl) 1252 return BP_RESULT_BADBIOSTABLE; 1253 1254 *dce_caps = disp_cntl_tbl->display_caps; 1255 1256 return result; 1257 } 1258 1259 static enum bp_result get_disp_caps_v4_3( 1260 struct bios_parser *bp, 1261 uint8_t *dce_caps) 1262 { 1263 enum bp_result result = BP_RESULT_OK; 1264 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1265 1266 if (!dce_caps) 1267 return BP_RESULT_BADINPUT; 1268 1269 if (!DATA_TABLES(dce_info)) 1270 return BP_RESULT_BADBIOSTABLE; 1271 1272 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1273 DATA_TABLES(dce_info)); 1274 1275 if (!disp_cntl_tbl) 1276 return BP_RESULT_BADBIOSTABLE; 1277 1278 *dce_caps = disp_cntl_tbl->display_caps; 1279 1280 return result; 1281 } 1282 1283 static enum bp_result get_disp_caps_v4_4( 1284 struct bios_parser *bp, 1285 uint8_t *dce_caps) 1286 { 1287 enum bp_result result = BP_RESULT_OK; 1288 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1289 1290 if (!dce_caps) 1291 return BP_RESULT_BADINPUT; 1292 1293 if (!DATA_TABLES(dce_info)) 1294 return BP_RESULT_BADBIOSTABLE; 1295 1296 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1297 DATA_TABLES(dce_info)); 1298 1299 if (!disp_cntl_tbl) 1300 return BP_RESULT_BADBIOSTABLE; 1301 1302 *dce_caps = disp_cntl_tbl->display_caps; 1303 1304 return result; 1305 } 1306 1307 static enum bp_result get_disp_caps_v4_5( 1308 struct bios_parser *bp, 1309 uint8_t *dce_caps) 1310 { 1311 enum bp_result result = BP_RESULT_OK; 1312 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1313 1314 if (!dce_caps) 1315 return BP_RESULT_BADINPUT; 1316 1317 if (!DATA_TABLES(dce_info)) 1318 return BP_RESULT_BADBIOSTABLE; 1319 1320 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1321 DATA_TABLES(dce_info)); 1322 1323 if (!disp_cntl_tbl) 1324 return BP_RESULT_BADBIOSTABLE; 1325 1326 *dce_caps = disp_cntl_tbl->display_caps; 1327 1328 return result; 1329 } 1330 1331 static enum bp_result bios_parser_get_lttpr_interop( 1332 struct dc_bios *dcb, 1333 uint8_t *dce_caps) 1334 { 1335 struct bios_parser *bp = BP_FROM_DCB(dcb); 1336 enum bp_result result = BP_RESULT_UNSUPPORTED; 1337 struct atom_common_table_header *header; 1338 struct atom_data_revision tbl_revision; 1339 1340 if (!DATA_TABLES(dce_info)) 1341 return BP_RESULT_UNSUPPORTED; 1342 1343 header = GET_IMAGE(struct atom_common_table_header, 1344 DATA_TABLES(dce_info)); 1345 get_atom_data_table_revision(header, &tbl_revision); 1346 switch (tbl_revision.major) { 1347 case 4: 1348 switch (tbl_revision.minor) { 1349 case 1: 1350 result = get_disp_caps_v4_1(bp, dce_caps); 1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1352 break; 1353 case 2: 1354 result = get_disp_caps_v4_2(bp, dce_caps); 1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1356 break; 1357 case 3: 1358 result = get_disp_caps_v4_3(bp, dce_caps); 1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1360 break; 1361 case 4: 1362 result = get_disp_caps_v4_4(bp, dce_caps); 1363 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1364 break; 1365 case 5: 1366 result = get_disp_caps_v4_5(bp, dce_caps); 1367 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1368 break; 1369 1370 default: 1371 break; 1372 } 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 return result; 1379 } 1380 1381 static enum bp_result bios_parser_get_lttpr_caps( 1382 struct dc_bios *dcb, 1383 uint8_t *dce_caps) 1384 { 1385 struct bios_parser *bp = BP_FROM_DCB(dcb); 1386 enum bp_result result = BP_RESULT_UNSUPPORTED; 1387 struct atom_common_table_header *header; 1388 struct atom_data_revision tbl_revision; 1389 1390 if (!DATA_TABLES(dce_info)) 1391 return BP_RESULT_UNSUPPORTED; 1392 1393 header = GET_IMAGE(struct atom_common_table_header, 1394 DATA_TABLES(dce_info)); 1395 get_atom_data_table_revision(header, &tbl_revision); 1396 switch (tbl_revision.major) { 1397 case 4: 1398 switch (tbl_revision.minor) { 1399 case 1: 1400 result = get_disp_caps_v4_1(bp, dce_caps); 1401 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1402 break; 1403 case 2: 1404 result = get_disp_caps_v4_2(bp, dce_caps); 1405 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1406 break; 1407 case 3: 1408 result = get_disp_caps_v4_3(bp, dce_caps); 1409 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1410 break; 1411 case 4: 1412 result = get_disp_caps_v4_4(bp, dce_caps); 1413 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1414 break; 1415 case 5: 1416 result = get_disp_caps_v4_5(bp, dce_caps); 1417 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1418 1419 default: 1420 break; 1421 } 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return result; 1428 } 1429 1430 static enum bp_result get_embedded_panel_info_v2_1( 1431 struct bios_parser *bp, 1432 struct embedded_panel_info *info) 1433 { 1434 struct lcd_info_v2_1 *lvds; 1435 1436 if (!info) 1437 return BP_RESULT_BADINPUT; 1438 1439 if (!DATA_TABLES(lcd_info)) 1440 return BP_RESULT_UNSUPPORTED; 1441 1442 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1443 1444 if (!lvds) 1445 return BP_RESULT_BADBIOSTABLE; 1446 1447 /* TODO: previous vv1_3, should v2_1 */ 1448 if (!((lvds->table_header.format_revision == 2) 1449 && (lvds->table_header.content_revision >= 1))) 1450 return BP_RESULT_UNSUPPORTED; 1451 1452 memset(info, 0, sizeof(struct embedded_panel_info)); 1453 1454 /* We need to convert from 10KHz units into KHz units */ 1455 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1456 /* usHActive does not include borders, according to VBIOS team */ 1457 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1458 /* usHBlanking_Time includes borders, so we should really be 1459 * subtractingborders duing this translation, but LVDS generally 1460 * doesn't have borders, so we should be okay leaving this as is for 1461 * now. May need to revisit if we ever have LVDS with borders 1462 */ 1463 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1464 /* usVActive does not include borders, according to VBIOS team*/ 1465 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1466 /* usVBlanking_Time includes borders, so we should really be 1467 * subtracting borders duing this translation, but LVDS generally 1468 * doesn't have borders, so we should be okay leaving this as is for 1469 * now. May need to revisit if we ever have LVDS with borders 1470 */ 1471 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1472 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1473 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1474 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1475 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1476 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1477 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1478 1479 /* not provided by VBIOS */ 1480 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1481 1482 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1483 & ATOM_HSYNC_POLARITY); 1484 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1485 & ATOM_VSYNC_POLARITY); 1486 1487 /* not provided by VBIOS */ 1488 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1489 1490 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1491 & ATOM_H_REPLICATIONBY2); 1492 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1493 & ATOM_V_REPLICATIONBY2); 1494 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1495 & ATOM_COMPOSITESYNC); 1496 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1497 1498 /* not provided by VBIOS*/ 1499 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1500 /* not provided by VBIOS*/ 1501 info->ss_id = 0; 1502 1503 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1504 1505 return BP_RESULT_OK; 1506 } 1507 1508 static enum bp_result bios_parser_get_embedded_panel_info( 1509 struct dc_bios *dcb, 1510 struct embedded_panel_info *info) 1511 { 1512 struct bios_parser 1513 *bp = BP_FROM_DCB(dcb); 1514 struct atom_common_table_header *header; 1515 struct atom_data_revision tbl_revision; 1516 1517 if (!DATA_TABLES(lcd_info)) 1518 return BP_RESULT_FAILURE; 1519 1520 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1521 1522 if (!header) 1523 return BP_RESULT_BADBIOSTABLE; 1524 1525 get_atom_data_table_revision(header, &tbl_revision); 1526 1527 switch (tbl_revision.major) { 1528 case 2: 1529 switch (tbl_revision.minor) { 1530 case 1: 1531 return get_embedded_panel_info_v2_1(bp, info); 1532 default: 1533 break; 1534 } 1535 default: 1536 break; 1537 } 1538 1539 return BP_RESULT_FAILURE; 1540 } 1541 1542 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1543 { 1544 enum dal_device_type device_type = device_id.device_type; 1545 uint32_t enum_id = device_id.enum_id; 1546 1547 switch (device_type) { 1548 case DEVICE_TYPE_LCD: 1549 switch (enum_id) { 1550 case 1: 1551 return ATOM_DISPLAY_LCD1_SUPPORT; 1552 default: 1553 break; 1554 } 1555 break; 1556 case DEVICE_TYPE_DFP: 1557 switch (enum_id) { 1558 case 1: 1559 return ATOM_DISPLAY_DFP1_SUPPORT; 1560 case 2: 1561 return ATOM_DISPLAY_DFP2_SUPPORT; 1562 case 3: 1563 return ATOM_DISPLAY_DFP3_SUPPORT; 1564 case 4: 1565 return ATOM_DISPLAY_DFP4_SUPPORT; 1566 case 5: 1567 return ATOM_DISPLAY_DFP5_SUPPORT; 1568 case 6: 1569 return ATOM_DISPLAY_DFP6_SUPPORT; 1570 default: 1571 break; 1572 } 1573 break; 1574 default: 1575 break; 1576 } 1577 1578 /* Unidentified device ID, return empty support mask. */ 1579 return 0; 1580 } 1581 1582 static bool bios_parser_is_device_id_supported( 1583 struct dc_bios *dcb, 1584 struct device_id id) 1585 { 1586 struct bios_parser *bp = BP_FROM_DCB(dcb); 1587 1588 uint32_t mask = get_support_mask_for_device_id(id); 1589 1590 switch (bp->object_info_tbl.revision.minor) { 1591 case 4: 1592 default: 1593 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1594 break; 1595 case 5: 1596 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1597 break; 1598 } 1599 1600 return false; 1601 } 1602 1603 static uint32_t bios_parser_get_ss_entry_number( 1604 struct dc_bios *dcb, 1605 enum as_signal_type signal) 1606 { 1607 /* TODO: DAL2 atomfirmware implementation does not need this. 1608 * why DAL3 need this? 1609 */ 1610 return 1; 1611 } 1612 1613 static enum bp_result bios_parser_transmitter_control( 1614 struct dc_bios *dcb, 1615 struct bp_transmitter_control *cntl) 1616 { 1617 struct bios_parser *bp = BP_FROM_DCB(dcb); 1618 1619 if (!bp->cmd_tbl.transmitter_control) 1620 return BP_RESULT_FAILURE; 1621 1622 return bp->cmd_tbl.transmitter_control(bp, cntl); 1623 } 1624 1625 static enum bp_result bios_parser_encoder_control( 1626 struct dc_bios *dcb, 1627 struct bp_encoder_control *cntl) 1628 { 1629 struct bios_parser *bp = BP_FROM_DCB(dcb); 1630 1631 if (!bp->cmd_tbl.dig_encoder_control) 1632 return BP_RESULT_FAILURE; 1633 1634 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1635 } 1636 1637 static enum bp_result bios_parser_set_pixel_clock( 1638 struct dc_bios *dcb, 1639 struct bp_pixel_clock_parameters *bp_params) 1640 { 1641 struct bios_parser *bp = BP_FROM_DCB(dcb); 1642 1643 if (!bp->cmd_tbl.set_pixel_clock) 1644 return BP_RESULT_FAILURE; 1645 1646 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1647 } 1648 1649 static enum bp_result bios_parser_set_dce_clock( 1650 struct dc_bios *dcb, 1651 struct bp_set_dce_clock_parameters *bp_params) 1652 { 1653 struct bios_parser *bp = BP_FROM_DCB(dcb); 1654 1655 if (!bp->cmd_tbl.set_dce_clock) 1656 return BP_RESULT_FAILURE; 1657 1658 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1659 } 1660 1661 static enum bp_result bios_parser_program_crtc_timing( 1662 struct dc_bios *dcb, 1663 struct bp_hw_crtc_timing_parameters *bp_params) 1664 { 1665 struct bios_parser *bp = BP_FROM_DCB(dcb); 1666 1667 if (!bp->cmd_tbl.set_crtc_timing) 1668 return BP_RESULT_FAILURE; 1669 1670 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1671 } 1672 1673 static enum bp_result bios_parser_enable_crtc( 1674 struct dc_bios *dcb, 1675 enum controller_id id, 1676 bool enable) 1677 { 1678 struct bios_parser *bp = BP_FROM_DCB(dcb); 1679 1680 if (!bp->cmd_tbl.enable_crtc) 1681 return BP_RESULT_FAILURE; 1682 1683 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1684 } 1685 1686 static enum bp_result bios_parser_enable_disp_power_gating( 1687 struct dc_bios *dcb, 1688 enum controller_id controller_id, 1689 enum bp_pipe_control_action action) 1690 { 1691 struct bios_parser *bp = BP_FROM_DCB(dcb); 1692 1693 if (!bp->cmd_tbl.enable_disp_power_gating) 1694 return BP_RESULT_FAILURE; 1695 1696 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1697 action); 1698 } 1699 1700 static enum bp_result bios_parser_enable_lvtma_control( 1701 struct dc_bios *dcb, 1702 uint8_t uc_pwr_on, 1703 uint8_t panel_instance) 1704 { 1705 struct bios_parser *bp = BP_FROM_DCB(dcb); 1706 1707 if (!bp->cmd_tbl.enable_lvtma_control) 1708 return BP_RESULT_FAILURE; 1709 1710 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1711 } 1712 1713 static bool bios_parser_is_accelerated_mode( 1714 struct dc_bios *dcb) 1715 { 1716 return bios_is_accelerated_mode(dcb); 1717 } 1718 1719 /** 1720 * bios_parser_set_scratch_critical_state - update critical state bit 1721 * in VBIOS scratch register 1722 * 1723 * @dcb: pointer to the DC BIO 1724 * @state: set or reset state 1725 */ 1726 static void bios_parser_set_scratch_critical_state( 1727 struct dc_bios *dcb, 1728 bool state) 1729 { 1730 bios_set_scratch_critical_state(dcb, state); 1731 } 1732 1733 struct atom_dig_transmitter_info_header_v5_3 { 1734 struct atom_common_table_header table_header; 1735 uint16_t dpphy_hdmi_settings_offset; 1736 uint16_t dpphy_dvi_settings_offset; 1737 uint16_t dpphy_dp_setting_table_offset; 1738 uint16_t uniphy_xbar_settings_v2_table_offset; 1739 uint16_t dpphy_internal_reg_overide_offset; 1740 }; 1741 1742 static enum bp_result bios_parser_get_firmware_info( 1743 struct dc_bios *dcb, 1744 struct dc_firmware_info *info) 1745 { 1746 struct bios_parser *bp = BP_FROM_DCB(dcb); 1747 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1748 struct atom_common_table_header *header; 1749 1750 struct atom_data_revision revision; 1751 1752 if (info && DATA_TABLES(firmwareinfo)) { 1753 header = GET_IMAGE(struct atom_common_table_header, 1754 DATA_TABLES(firmwareinfo)); 1755 get_atom_data_table_revision(header, &revision); 1756 switch (revision.major) { 1757 case 3: 1758 switch (revision.minor) { 1759 case 1: 1760 result = get_firmware_info_v3_1(bp, info); 1761 break; 1762 case 2: 1763 case 3: 1764 result = get_firmware_info_v3_2(bp, info); 1765 break; 1766 case 4: 1767 result = get_firmware_info_v3_4(bp, info); 1768 break; 1769 default: 1770 break; 1771 } 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 1778 return result; 1779 } 1780 1781 static enum bp_result get_firmware_info_v3_1( 1782 struct bios_parser *bp, 1783 struct dc_firmware_info *info) 1784 { 1785 struct atom_firmware_info_v3_1 *firmware_info; 1786 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1787 1788 if (!info) 1789 return BP_RESULT_BADINPUT; 1790 1791 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1792 DATA_TABLES(firmwareinfo)); 1793 1794 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1795 DATA_TABLES(dce_info)); 1796 1797 if (!firmware_info || !dce_info) 1798 return BP_RESULT_BADBIOSTABLE; 1799 1800 memset(info, 0, sizeof(*info)); 1801 1802 /* Pixel clock pll information. */ 1803 /* We need to convert from 10KHz units into KHz units */ 1804 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1805 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1806 1807 /* 27MHz for Vega10: */ 1808 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1809 1810 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1811 if (info->pll_info.crystal_frequency == 0) 1812 info->pll_info.crystal_frequency = 27000; 1813 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1814 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1815 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1816 1817 /* Get GPU PLL VCO Clock */ 1818 1819 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1820 /* VBIOS gives in 10KHz */ 1821 info->smu_gpu_pll_output_freq = 1822 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1823 } 1824 1825 info->oem_i2c_present = false; 1826 1827 return BP_RESULT_OK; 1828 } 1829 1830 static enum bp_result get_firmware_info_v3_2( 1831 struct bios_parser *bp, 1832 struct dc_firmware_info *info) 1833 { 1834 struct atom_firmware_info_v3_2 *firmware_info; 1835 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1836 struct atom_common_table_header *header; 1837 struct atom_data_revision revision; 1838 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1839 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1840 1841 if (!info) 1842 return BP_RESULT_BADINPUT; 1843 1844 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1845 DATA_TABLES(firmwareinfo)); 1846 1847 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1848 DATA_TABLES(dce_info)); 1849 1850 if (!firmware_info || !dce_info) 1851 return BP_RESULT_BADBIOSTABLE; 1852 1853 memset(info, 0, sizeof(*info)); 1854 1855 header = GET_IMAGE(struct atom_common_table_header, 1856 DATA_TABLES(smu_info)); 1857 get_atom_data_table_revision(header, &revision); 1858 1859 if (revision.minor == 2) { 1860 /* Vega12 */ 1861 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1862 DATA_TABLES(smu_info)); 1863 1864 if (!smu_info_v3_2) 1865 return BP_RESULT_BADBIOSTABLE; 1866 1867 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1868 } else if (revision.minor == 3) { 1869 /* Vega20 */ 1870 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1871 DATA_TABLES(smu_info)); 1872 1873 if (!smu_info_v3_3) 1874 return BP_RESULT_BADBIOSTABLE; 1875 1876 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1877 } 1878 1879 // We need to convert from 10KHz units into KHz units. 1880 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1881 1882 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1883 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1884 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1885 if (info->pll_info.crystal_frequency == 0) { 1886 if (revision.minor == 2) 1887 info->pll_info.crystal_frequency = 27000; 1888 else if (revision.minor == 3) 1889 info->pll_info.crystal_frequency = 100000; 1890 } 1891 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1892 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1893 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1894 1895 /* Get GPU PLL VCO Clock */ 1896 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1897 if (revision.minor == 2) 1898 info->smu_gpu_pll_output_freq = 1899 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1900 else if (revision.minor == 3) 1901 info->smu_gpu_pll_output_freq = 1902 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1903 } 1904 1905 if (firmware_info->board_i2c_feature_id == 0x2) { 1906 info->oem_i2c_present = true; 1907 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1908 } else { 1909 info->oem_i2c_present = false; 1910 } 1911 1912 return BP_RESULT_OK; 1913 } 1914 1915 static enum bp_result get_firmware_info_v3_4( 1916 struct bios_parser *bp, 1917 struct dc_firmware_info *info) 1918 { 1919 struct atom_firmware_info_v3_4 *firmware_info; 1920 struct atom_common_table_header *header; 1921 struct atom_data_revision revision; 1922 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1923 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1924 1925 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1926 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1927 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1928 1929 if (!info) 1930 return BP_RESULT_BADINPUT; 1931 1932 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1933 DATA_TABLES(firmwareinfo)); 1934 1935 if (!firmware_info) 1936 return BP_RESULT_BADBIOSTABLE; 1937 1938 memset(info, 0, sizeof(*info)); 1939 1940 header = GET_IMAGE(struct atom_common_table_header, 1941 DATA_TABLES(dce_info)); 1942 1943 get_atom_data_table_revision(header, &revision); 1944 1945 switch (revision.major) { 1946 case 4: 1947 switch (revision.minor) { 1948 case 5: 1949 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1950 DATA_TABLES(dce_info)); 1951 1952 if (!dce_info_v4_5) 1953 return BP_RESULT_BADBIOSTABLE; 1954 1955 /* 100MHz expected */ 1956 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1957 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1958 /* 50MHz expected */ 1959 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1960 1961 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1962 break; 1963 1964 case 4: 1965 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1966 DATA_TABLES(dce_info)); 1967 1968 if (!dce_info_v4_4) 1969 return BP_RESULT_BADBIOSTABLE; 1970 1971 /* 100MHz expected */ 1972 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1973 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1974 /* 50MHz expected */ 1975 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1976 1977 /* Get SMU Display PLL VCO Frequency in KHz*/ 1978 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1979 break; 1980 1981 default: 1982 /* should not come here, keep as backup, as was before */ 1983 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1984 DATA_TABLES(dce_info)); 1985 1986 if (!dce_info_v4_1) 1987 return BP_RESULT_BADBIOSTABLE; 1988 1989 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 1990 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 1991 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 1992 break; 1993 } 1994 break; 1995 1996 default: 1997 ASSERT(0); 1998 break; 1999 } 2000 2001 header = GET_IMAGE(struct atom_common_table_header, 2002 DATA_TABLES(smu_info)); 2003 get_atom_data_table_revision(header, &revision); 2004 2005 switch (revision.major) { 2006 case 3: 2007 switch (revision.minor) { 2008 case 5: 2009 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2010 DATA_TABLES(smu_info)); 2011 2012 if (!smu_info_v3_5) 2013 return BP_RESULT_BADBIOSTABLE; 2014 2015 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2016 break; 2017 2018 default: 2019 break; 2020 } 2021 break; 2022 2023 case 4: 2024 switch (revision.minor) { 2025 case 0: 2026 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2027 DATA_TABLES(smu_info)); 2028 2029 if (!smu_info_v4_0) 2030 return BP_RESULT_BADBIOSTABLE; 2031 2032 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2033 break; 2034 2035 default: 2036 break; 2037 } 2038 break; 2039 2040 default: 2041 break; 2042 } 2043 2044 // We need to convert from 10KHz units into KHz units. 2045 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2046 2047 if (firmware_info->board_i2c_feature_id == 0x2) { 2048 info->oem_i2c_present = true; 2049 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2050 } else { 2051 info->oem_i2c_present = false; 2052 } 2053 2054 return BP_RESULT_OK; 2055 } 2056 2057 static enum bp_result bios_parser_get_encoder_cap_info( 2058 struct dc_bios *dcb, 2059 struct graphics_object_id object_id, 2060 struct bp_encoder_cap_info *info) 2061 { 2062 struct bios_parser *bp = BP_FROM_DCB(dcb); 2063 struct atom_display_object_path_v2 *object; 2064 struct atom_encoder_caps_record *record = NULL; 2065 2066 if (!info) 2067 return BP_RESULT_BADINPUT; 2068 2069 #if defined(CONFIG_DRM_AMD_DC_DCN) 2070 /* encoder cap record not available in v1_5 */ 2071 if (bp->object_info_tbl.revision.minor == 5) 2072 return BP_RESULT_NORECORD; 2073 #endif 2074 2075 object = get_bios_object(bp, object_id); 2076 2077 if (!object) 2078 return BP_RESULT_BADINPUT; 2079 2080 record = get_encoder_cap_record(bp, object); 2081 if (!record) 2082 return BP_RESULT_NORECORD; 2083 2084 info->DP_HBR2_CAP = (record->encodercaps & 2085 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2086 info->DP_HBR2_EN = (record->encodercaps & 2087 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2088 info->DP_HBR3_EN = (record->encodercaps & 2089 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2090 info->HDMI_6GB_EN = (record->encodercaps & 2091 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2092 info->IS_DP2_CAPABLE = (record->encodercaps & 2093 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2094 info->DP_UHBR10_EN = (record->encodercaps & 2095 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2096 info->DP_UHBR13_5_EN = (record->encodercaps & 2097 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2098 info->DP_UHBR20_EN = (record->encodercaps & 2099 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2100 info->DP_IS_USB_C = (record->encodercaps & 2101 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2102 2103 return BP_RESULT_OK; 2104 } 2105 2106 2107 static struct atom_encoder_caps_record *get_encoder_cap_record( 2108 struct bios_parser *bp, 2109 struct atom_display_object_path_v2 *object) 2110 { 2111 struct atom_common_record_header *header; 2112 uint32_t offset; 2113 2114 if (!object) { 2115 BREAK_TO_DEBUGGER(); /* Invalid object */ 2116 return NULL; 2117 } 2118 2119 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2120 2121 for (;;) { 2122 header = GET_IMAGE(struct atom_common_record_header, offset); 2123 2124 if (!header) 2125 return NULL; 2126 2127 offset += header->record_size; 2128 2129 if (header->record_type == LAST_RECORD_TYPE || 2130 !header->record_size) 2131 break; 2132 2133 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2134 continue; 2135 2136 if (sizeof(struct atom_encoder_caps_record) <= 2137 header->record_size) 2138 return (struct atom_encoder_caps_record *)header; 2139 } 2140 2141 return NULL; 2142 } 2143 2144 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2145 struct bios_parser *bp, 2146 struct atom_display_object_path_v2 *object) 2147 { 2148 struct atom_common_record_header *header; 2149 uint32_t offset; 2150 2151 if (!object) { 2152 BREAK_TO_DEBUGGER(); /* Invalid object */ 2153 return NULL; 2154 } 2155 2156 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2157 2158 for (;;) { 2159 header = GET_IMAGE(struct atom_common_record_header, offset); 2160 2161 if (!header) 2162 return NULL; 2163 2164 offset += header->record_size; 2165 2166 if (header->record_type == LAST_RECORD_TYPE || 2167 !header->record_size) 2168 break; 2169 2170 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2171 continue; 2172 2173 if (sizeof(struct atom_disp_connector_caps_record) <= 2174 header->record_size) 2175 return (struct atom_disp_connector_caps_record *)header; 2176 } 2177 2178 return NULL; 2179 } 2180 2181 static struct atom_connector_caps_record *get_connector_caps_record( 2182 struct bios_parser *bp, 2183 struct atom_display_object_path_v3 *object) 2184 { 2185 struct atom_common_record_header *header; 2186 uint32_t offset; 2187 2188 if (!object) { 2189 BREAK_TO_DEBUGGER(); /* Invalid object */ 2190 return NULL; 2191 } 2192 2193 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2194 2195 for (;;) { 2196 header = GET_IMAGE(struct atom_common_record_header, offset); 2197 2198 if (!header) 2199 return NULL; 2200 2201 offset += header->record_size; 2202 2203 if (header->record_type == ATOM_RECORD_END_TYPE || 2204 !header->record_size) 2205 break; 2206 2207 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2208 continue; 2209 2210 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2211 return (struct atom_connector_caps_record *)header; 2212 } 2213 2214 return NULL; 2215 } 2216 2217 static enum bp_result bios_parser_get_disp_connector_caps_info( 2218 struct dc_bios *dcb, 2219 struct graphics_object_id object_id, 2220 struct bp_disp_connector_caps_info *info) 2221 { 2222 struct bios_parser *bp = BP_FROM_DCB(dcb); 2223 struct atom_display_object_path_v2 *object; 2224 2225 struct atom_display_object_path_v3 *object_path_v3; 2226 struct atom_connector_caps_record *record_path_v3; 2227 2228 struct atom_disp_connector_caps_record *record = NULL; 2229 2230 if (!info) 2231 return BP_RESULT_BADINPUT; 2232 2233 switch (bp->object_info_tbl.revision.minor) { 2234 case 4: 2235 default: 2236 object = get_bios_object(bp, object_id); 2237 2238 if (!object) 2239 return BP_RESULT_BADINPUT; 2240 2241 record = get_disp_connector_caps_record(bp, object); 2242 if (!record) 2243 return BP_RESULT_NORECORD; 2244 2245 info->INTERNAL_DISPLAY = 2246 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2247 info->INTERNAL_DISPLAY_BL = 2248 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2249 break; 2250 case 5: 2251 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2252 2253 if (!object_path_v3) 2254 return BP_RESULT_BADINPUT; 2255 2256 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2257 if (!record_path_v3) 2258 return BP_RESULT_NORECORD; 2259 2260 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2261 ? 1 : 0; 2262 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2263 ? 1 : 0; 2264 break; 2265 } 2266 2267 return BP_RESULT_OK; 2268 } 2269 2270 static struct atom_connector_speed_record *get_connector_speed_cap_record( 2271 struct bios_parser *bp, 2272 struct atom_display_object_path_v3 *object) 2273 { 2274 struct atom_common_record_header *header; 2275 uint32_t offset; 2276 2277 if (!object) { 2278 BREAK_TO_DEBUGGER(); /* Invalid object */ 2279 return NULL; 2280 } 2281 2282 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2283 2284 for (;;) { 2285 header = GET_IMAGE(struct atom_common_record_header, offset); 2286 2287 if (!header) 2288 return NULL; 2289 2290 offset += header->record_size; 2291 2292 if (header->record_type == ATOM_RECORD_END_TYPE || 2293 !header->record_size) 2294 break; 2295 2296 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2297 continue; 2298 2299 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2300 return (struct atom_connector_speed_record *)header; 2301 } 2302 2303 return NULL; 2304 } 2305 2306 static enum bp_result bios_parser_get_connector_speed_cap_info( 2307 struct dc_bios *dcb, 2308 struct graphics_object_id object_id, 2309 struct bp_connector_speed_cap_info *info) 2310 { 2311 struct bios_parser *bp = BP_FROM_DCB(dcb); 2312 struct atom_display_object_path_v3 *object_path_v3; 2313 //struct atom_connector_speed_record *record = NULL; 2314 struct atom_connector_speed_record *record; 2315 2316 if (!info) 2317 return BP_RESULT_BADINPUT; 2318 2319 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2320 2321 if (!object_path_v3) 2322 return BP_RESULT_BADINPUT; 2323 2324 record = get_connector_speed_cap_record(bp, object_path_v3); 2325 if (!record) 2326 return BP_RESULT_NORECORD; 2327 2328 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2329 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2330 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2331 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2332 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2333 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2334 return BP_RESULT_OK; 2335 } 2336 2337 static enum bp_result get_vram_info_v23( 2338 struct bios_parser *bp, 2339 struct dc_vram_info *info) 2340 { 2341 struct atom_vram_info_header_v2_3 *info_v23; 2342 static enum bp_result result = BP_RESULT_OK; 2343 2344 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2345 DATA_TABLES(vram_info)); 2346 2347 if (info_v23 == NULL) 2348 return BP_RESULT_BADBIOSTABLE; 2349 2350 info->num_chans = info_v23->vram_module[0].channel_num; 2351 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2352 2353 return result; 2354 } 2355 2356 static enum bp_result get_vram_info_v24( 2357 struct bios_parser *bp, 2358 struct dc_vram_info *info) 2359 { 2360 struct atom_vram_info_header_v2_4 *info_v24; 2361 static enum bp_result result = BP_RESULT_OK; 2362 2363 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2364 DATA_TABLES(vram_info)); 2365 2366 if (info_v24 == NULL) 2367 return BP_RESULT_BADBIOSTABLE; 2368 2369 info->num_chans = info_v24->vram_module[0].channel_num; 2370 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2371 2372 return result; 2373 } 2374 2375 static enum bp_result get_vram_info_v25( 2376 struct bios_parser *bp, 2377 struct dc_vram_info *info) 2378 { 2379 struct atom_vram_info_header_v2_5 *info_v25; 2380 static enum bp_result result = BP_RESULT_OK; 2381 2382 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2383 DATA_TABLES(vram_info)); 2384 2385 if (info_v25 == NULL) 2386 return BP_RESULT_BADBIOSTABLE; 2387 2388 info->num_chans = info_v25->vram_module[0].channel_num; 2389 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2390 2391 return result; 2392 } 2393 2394 /* 2395 * get_integrated_info_v11 2396 * 2397 * @brief 2398 * Get V8 integrated BIOS information 2399 * 2400 * @param 2401 * bios_parser *bp - [in]BIOS parser handler to get master data table 2402 * integrated_info *info - [out] store and output integrated info 2403 * 2404 * @return 2405 * static enum bp_result - BP_RESULT_OK if information is available, 2406 * BP_RESULT_BADBIOSTABLE otherwise. 2407 */ 2408 static enum bp_result get_integrated_info_v11( 2409 struct bios_parser *bp, 2410 struct integrated_info *info) 2411 { 2412 struct atom_integrated_system_info_v1_11 *info_v11; 2413 uint32_t i; 2414 2415 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2416 DATA_TABLES(integratedsysteminfo)); 2417 2418 if (info_v11 == NULL) 2419 return BP_RESULT_BADBIOSTABLE; 2420 2421 info->gpu_cap_info = 2422 le32_to_cpu(info_v11->gpucapinfo); 2423 /* 2424 * system_config: Bit[0] = 0 : PCIE power gating disabled 2425 * = 1 : PCIE power gating enabled 2426 * Bit[1] = 0 : DDR-PLL shut down disabled 2427 * = 1 : DDR-PLL shut down enabled 2428 * Bit[2] = 0 : DDR-PLL power down disabled 2429 * = 1 : DDR-PLL power down enabled 2430 */ 2431 info->system_config = le32_to_cpu(info_v11->system_config); 2432 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2433 info->memory_type = info_v11->memorytype; 2434 info->ma_channel_number = info_v11->umachannelnumber; 2435 info->lvds_ss_percentage = 2436 le16_to_cpu(info_v11->lvds_ss_percentage); 2437 info->dp_ss_control = 2438 le16_to_cpu(info_v11->reserved1); 2439 info->lvds_sspread_rate_in_10hz = 2440 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2441 info->hdmi_ss_percentage = 2442 le16_to_cpu(info_v11->hdmi_ss_percentage); 2443 info->hdmi_sspread_rate_in_10hz = 2444 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2445 info->dvi_ss_percentage = 2446 le16_to_cpu(info_v11->dvi_ss_percentage); 2447 info->dvi_sspread_rate_in_10_hz = 2448 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2449 info->lvds_misc = info_v11->lvds_misc; 2450 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2451 info->ext_disp_conn_info.gu_id[i] = 2452 info_v11->extdispconninfo.guid[i]; 2453 } 2454 2455 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2456 info->ext_disp_conn_info.path[i].device_connector_id = 2457 object_id_from_bios_object_id( 2458 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2459 2460 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2461 object_id_from_bios_object_id( 2462 le16_to_cpu( 2463 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2464 2465 info->ext_disp_conn_info.path[i].device_tag = 2466 le16_to_cpu( 2467 info_v11->extdispconninfo.path[i].device_tag); 2468 info->ext_disp_conn_info.path[i].device_acpi_enum = 2469 le16_to_cpu( 2470 info_v11->extdispconninfo.path[i].device_acpi_enum); 2471 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2472 info_v11->extdispconninfo.path[i].auxddclut_index; 2473 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2474 info_v11->extdispconninfo.path[i].hpdlut_index; 2475 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2476 info_v11->extdispconninfo.path[i].channelmapping; 2477 info->ext_disp_conn_info.path[i].caps = 2478 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2479 } 2480 info->ext_disp_conn_info.checksum = 2481 info_v11->extdispconninfo.checksum; 2482 2483 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2484 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2485 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2486 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2487 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2488 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2489 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2490 } 2491 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2492 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2493 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2494 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2495 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2496 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2497 } 2498 2499 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2500 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2501 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2502 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2503 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2504 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2505 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2506 } 2507 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2508 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2509 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2510 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2511 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2512 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2513 } 2514 2515 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2516 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2517 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2518 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2519 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2520 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2521 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2522 } 2523 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2524 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2525 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2526 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2527 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2528 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2529 } 2530 2531 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2532 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2533 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2534 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2535 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2536 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2537 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2538 } 2539 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2540 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2541 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2542 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2543 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2544 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2545 } 2546 2547 2548 /** TODO - review **/ 2549 #if 0 2550 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2551 * 10; 2552 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2553 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2554 2555 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2556 /* Convert [10KHz] into [KHz] */ 2557 info->disp_clk_voltage[i].max_supported_clk = 2558 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2559 ulMaximumSupportedCLK) * 10; 2560 info->disp_clk_voltage[i].voltage_index = 2561 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2562 } 2563 2564 info->boot_up_req_display_vector = 2565 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2566 info->boot_up_nb_voltage = 2567 le16_to_cpu(info_v11->usBootUpNBVoltage); 2568 info->ext_disp_conn_info_offset = 2569 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2570 info->gmc_restore_reset_time = 2571 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2572 info->minimum_n_clk = 2573 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2574 for (i = 1; i < 4; ++i) 2575 info->minimum_n_clk = 2576 info->minimum_n_clk < 2577 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2578 info->minimum_n_clk : le32_to_cpu( 2579 info_v11->ulNbpStateNClkFreq[i]); 2580 2581 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2582 info->ddr_dll_power_up_time = 2583 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2584 info->ddr_pll_power_up_time = 2585 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2586 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2587 info->max_lvds_pclk_freq_in_single_link = 2588 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2589 info->max_lvds_pclk_freq_in_single_link = 2590 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2591 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2592 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2593 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2594 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2595 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2596 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2597 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2598 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2599 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2600 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2601 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2602 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2603 info->lvds_off_to_on_delay_in_4ms = 2604 info_v11->ucLVDSOffToOnDelay_in4Ms; 2605 info->lvds_bit_depth_control_val = 2606 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2607 2608 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2609 /* Convert [10KHz] into [KHz] */ 2610 info->avail_s_clk[i].supported_s_clk = 2611 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2612 * 10; 2613 info->avail_s_clk[i].voltage_index = 2614 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2615 info->avail_s_clk[i].voltage_id = 2616 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2617 } 2618 #endif /* TODO*/ 2619 2620 return BP_RESULT_OK; 2621 } 2622 2623 static enum bp_result get_integrated_info_v2_1( 2624 struct bios_parser *bp, 2625 struct integrated_info *info) 2626 { 2627 struct atom_integrated_system_info_v2_1 *info_v2_1; 2628 uint32_t i; 2629 2630 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2631 DATA_TABLES(integratedsysteminfo)); 2632 2633 if (info_v2_1 == NULL) 2634 return BP_RESULT_BADBIOSTABLE; 2635 2636 info->gpu_cap_info = 2637 le32_to_cpu(info_v2_1->gpucapinfo); 2638 /* 2639 * system_config: Bit[0] = 0 : PCIE power gating disabled 2640 * = 1 : PCIE power gating enabled 2641 * Bit[1] = 0 : DDR-PLL shut down disabled 2642 * = 1 : DDR-PLL shut down enabled 2643 * Bit[2] = 0 : DDR-PLL power down disabled 2644 * = 1 : DDR-PLL power down enabled 2645 */ 2646 info->system_config = le32_to_cpu(info_v2_1->system_config); 2647 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2648 info->memory_type = info_v2_1->memorytype; 2649 info->ma_channel_number = info_v2_1->umachannelnumber; 2650 info->dp_ss_control = 2651 le16_to_cpu(info_v2_1->reserved1); 2652 2653 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2654 info->ext_disp_conn_info.gu_id[i] = 2655 info_v2_1->extdispconninfo.guid[i]; 2656 } 2657 2658 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2659 info->ext_disp_conn_info.path[i].device_connector_id = 2660 object_id_from_bios_object_id( 2661 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2662 2663 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2664 object_id_from_bios_object_id( 2665 le16_to_cpu( 2666 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2667 2668 info->ext_disp_conn_info.path[i].device_tag = 2669 le16_to_cpu( 2670 info_v2_1->extdispconninfo.path[i].device_tag); 2671 info->ext_disp_conn_info.path[i].device_acpi_enum = 2672 le16_to_cpu( 2673 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2674 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2675 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2676 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2677 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2678 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2679 info_v2_1->extdispconninfo.path[i].channelmapping; 2680 info->ext_disp_conn_info.path[i].caps = 2681 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2682 } 2683 2684 info->ext_disp_conn_info.checksum = 2685 info_v2_1->extdispconninfo.checksum; 2686 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2687 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2688 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2689 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2690 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2691 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2692 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2693 } 2694 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2695 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2696 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2697 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2698 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2699 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2700 } 2701 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2702 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2703 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2704 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2705 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2706 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2707 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2708 } 2709 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2710 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2711 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2712 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2713 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2714 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2715 } 2716 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2717 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2718 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2719 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2720 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2721 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2722 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2723 } 2724 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2725 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2726 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2727 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2728 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2729 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2730 } 2731 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2732 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2733 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2734 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2735 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2736 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2737 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2738 } 2739 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2740 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2741 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2742 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2743 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2744 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2745 } 2746 2747 info->edp1_info.edp_backlight_pwm_hz = 2748 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2749 info->edp1_info.edp_ss_percentage = 2750 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2751 info->edp1_info.edp_ss_rate_10hz = 2752 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2753 info->edp1_info.edp_pwr_on_off_delay = 2754 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2755 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2756 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2757 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2758 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2759 info->edp1_info.edp_panel_bpc = 2760 info_v2_1->edp1_info.edp_panel_bpc; 2761 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2762 2763 info->edp2_info.edp_backlight_pwm_hz = 2764 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2765 info->edp2_info.edp_ss_percentage = 2766 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2767 info->edp2_info.edp_ss_rate_10hz = 2768 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2769 info->edp2_info.edp_pwr_on_off_delay = 2770 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2771 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2772 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2773 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2774 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2775 info->edp2_info.edp_panel_bpc = 2776 info_v2_1->edp2_info.edp_panel_bpc; 2777 info->edp2_info.edp_bootup_bl_level = 2778 info_v2_1->edp2_info.edp_bootup_bl_level; 2779 2780 return BP_RESULT_OK; 2781 } 2782 2783 static enum bp_result get_integrated_info_v2_2( 2784 struct bios_parser *bp, 2785 struct integrated_info *info) 2786 { 2787 struct atom_integrated_system_info_v2_2 *info_v2_2; 2788 uint32_t i; 2789 2790 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2791 DATA_TABLES(integratedsysteminfo)); 2792 2793 if (info_v2_2 == NULL) 2794 return BP_RESULT_BADBIOSTABLE; 2795 2796 info->gpu_cap_info = 2797 le32_to_cpu(info_v2_2->gpucapinfo); 2798 /* 2799 * system_config: Bit[0] = 0 : PCIE power gating disabled 2800 * = 1 : PCIE power gating enabled 2801 * Bit[1] = 0 : DDR-PLL shut down disabled 2802 * = 1 : DDR-PLL shut down enabled 2803 * Bit[2] = 0 : DDR-PLL power down disabled 2804 * = 1 : DDR-PLL power down enabled 2805 */ 2806 info->system_config = le32_to_cpu(info_v2_2->system_config); 2807 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2808 info->memory_type = info_v2_2->memorytype; 2809 info->ma_channel_number = info_v2_2->umachannelnumber; 2810 info->dp_ss_control = 2811 le16_to_cpu(info_v2_2->reserved1); 2812 2813 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2814 info->ext_disp_conn_info.gu_id[i] = 2815 info_v2_2->extdispconninfo.guid[i]; 2816 } 2817 2818 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2819 info->ext_disp_conn_info.path[i].device_connector_id = 2820 object_id_from_bios_object_id( 2821 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2822 2823 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2824 object_id_from_bios_object_id( 2825 le16_to_cpu( 2826 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2827 2828 info->ext_disp_conn_info.path[i].device_tag = 2829 le16_to_cpu( 2830 info_v2_2->extdispconninfo.path[i].device_tag); 2831 info->ext_disp_conn_info.path[i].device_acpi_enum = 2832 le16_to_cpu( 2833 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2834 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2835 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2836 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2837 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2838 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2839 info_v2_2->extdispconninfo.path[i].channelmapping; 2840 info->ext_disp_conn_info.path[i].caps = 2841 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2842 } 2843 2844 info->ext_disp_conn_info.checksum = 2845 info_v2_2->extdispconninfo.checksum; 2846 info->ext_disp_conn_info.fixdpvoltageswing = 2847 info_v2_2->extdispconninfo.fixdpvoltageswing; 2848 2849 info->edp1_info.edp_backlight_pwm_hz = 2850 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2851 info->edp1_info.edp_ss_percentage = 2852 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2853 info->edp1_info.edp_ss_rate_10hz = 2854 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2855 info->edp1_info.edp_pwr_on_off_delay = 2856 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2857 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2858 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2859 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2860 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2861 info->edp1_info.edp_panel_bpc = 2862 info_v2_2->edp1_info.edp_panel_bpc; 2863 info->edp1_info.edp_bootup_bl_level = 2864 2865 info->edp2_info.edp_backlight_pwm_hz = 2866 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2867 info->edp2_info.edp_ss_percentage = 2868 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2869 info->edp2_info.edp_ss_rate_10hz = 2870 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2871 info->edp2_info.edp_pwr_on_off_delay = 2872 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2873 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2874 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2875 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2876 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2877 info->edp2_info.edp_panel_bpc = 2878 info_v2_2->edp2_info.edp_panel_bpc; 2879 info->edp2_info.edp_bootup_bl_level = 2880 info_v2_2->edp2_info.edp_bootup_bl_level; 2881 2882 return BP_RESULT_OK; 2883 } 2884 2885 /* 2886 * construct_integrated_info 2887 * 2888 * @brief 2889 * Get integrated BIOS information based on table revision 2890 * 2891 * @param 2892 * bios_parser *bp - [in]BIOS parser handler to get master data table 2893 * integrated_info *info - [out] store and output integrated info 2894 * 2895 * @return 2896 * static enum bp_result - BP_RESULT_OK if information is available, 2897 * BP_RESULT_BADBIOSTABLE otherwise. 2898 */ 2899 static enum bp_result construct_integrated_info( 2900 struct bios_parser *bp, 2901 struct integrated_info *info) 2902 { 2903 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2904 2905 struct atom_common_table_header *header; 2906 struct atom_data_revision revision; 2907 2908 struct clock_voltage_caps temp = {0, 0}; 2909 uint32_t i; 2910 uint32_t j; 2911 2912 if (info && DATA_TABLES(integratedsysteminfo)) { 2913 header = GET_IMAGE(struct atom_common_table_header, 2914 DATA_TABLES(integratedsysteminfo)); 2915 2916 get_atom_data_table_revision(header, &revision); 2917 2918 switch (revision.major) { 2919 case 1: 2920 switch (revision.minor) { 2921 case 11: 2922 case 12: 2923 result = get_integrated_info_v11(bp, info); 2924 break; 2925 default: 2926 return result; 2927 } 2928 break; 2929 case 2: 2930 switch (revision.minor) { 2931 case 1: 2932 result = get_integrated_info_v2_1(bp, info); 2933 break; 2934 case 2: 2935 result = get_integrated_info_v2_2(bp, info); 2936 break; 2937 default: 2938 return result; 2939 } 2940 break; 2941 default: 2942 return result; 2943 } 2944 } 2945 2946 if (result != BP_RESULT_OK) 2947 return result; 2948 2949 /* Sort voltage table from low to high*/ 2950 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2951 for (j = i; j > 0; --j) { 2952 if (info->disp_clk_voltage[j].max_supported_clk < 2953 info->disp_clk_voltage[j-1].max_supported_clk 2954 ) { 2955 /* swap j and j - 1*/ 2956 temp = info->disp_clk_voltage[j-1]; 2957 info->disp_clk_voltage[j-1] = 2958 info->disp_clk_voltage[j]; 2959 info->disp_clk_voltage[j] = temp; 2960 } 2961 } 2962 } 2963 2964 return result; 2965 } 2966 2967 static enum bp_result bios_parser_get_vram_info( 2968 struct dc_bios *dcb, 2969 struct dc_vram_info *info) 2970 { 2971 struct bios_parser *bp = BP_FROM_DCB(dcb); 2972 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2973 struct atom_common_table_header *header; 2974 struct atom_data_revision revision; 2975 2976 if (info && DATA_TABLES(vram_info)) { 2977 header = GET_IMAGE(struct atom_common_table_header, 2978 DATA_TABLES(vram_info)); 2979 2980 get_atom_data_table_revision(header, &revision); 2981 2982 switch (revision.major) { 2983 case 2: 2984 switch (revision.minor) { 2985 case 3: 2986 result = get_vram_info_v23(bp, info); 2987 break; 2988 case 4: 2989 result = get_vram_info_v24(bp, info); 2990 break; 2991 case 5: 2992 result = get_vram_info_v25(bp, info); 2993 break; 2994 default: 2995 break; 2996 } 2997 break; 2998 2999 default: 3000 return result; 3001 } 3002 3003 } 3004 return result; 3005 } 3006 3007 static struct integrated_info *bios_parser_create_integrated_info( 3008 struct dc_bios *dcb) 3009 { 3010 struct bios_parser *bp = BP_FROM_DCB(dcb); 3011 struct integrated_info *info = NULL; 3012 3013 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 3014 3015 if (info == NULL) { 3016 ASSERT_CRITICAL(0); 3017 return NULL; 3018 } 3019 3020 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3021 return info; 3022 3023 kfree(info); 3024 3025 return NULL; 3026 } 3027 3028 static enum bp_result update_slot_layout_info( 3029 struct dc_bios *dcb, 3030 unsigned int i, 3031 struct slot_layout_info *slot_layout_info) 3032 { 3033 unsigned int record_offset; 3034 unsigned int j; 3035 struct atom_display_object_path_v2 *object; 3036 struct atom_bracket_layout_record *record; 3037 struct atom_common_record_header *record_header; 3038 static enum bp_result result; 3039 struct bios_parser *bp; 3040 struct object_info_table *tbl; 3041 struct display_object_info_table_v1_4 *v1_4; 3042 3043 record = NULL; 3044 record_header = NULL; 3045 result = BP_RESULT_NORECORD; 3046 3047 bp = BP_FROM_DCB(dcb); 3048 tbl = &bp->object_info_tbl; 3049 v1_4 = tbl->v1_4; 3050 3051 object = &v1_4->display_path[i]; 3052 record_offset = (unsigned int) 3053 (object->disp_recordoffset) + 3054 (unsigned int)(bp->object_info_tbl_offset); 3055 3056 for (;;) { 3057 3058 record_header = (struct atom_common_record_header *) 3059 GET_IMAGE(struct atom_common_record_header, 3060 record_offset); 3061 if (record_header == NULL) { 3062 result = BP_RESULT_BADBIOSTABLE; 3063 break; 3064 } 3065 3066 /* the end of the list */ 3067 if (record_header->record_type == 0xff || 3068 record_header->record_size == 0) { 3069 break; 3070 } 3071 3072 if (record_header->record_type == 3073 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3074 sizeof(struct atom_bracket_layout_record) 3075 <= record_header->record_size) { 3076 record = (struct atom_bracket_layout_record *) 3077 (record_header); 3078 result = BP_RESULT_OK; 3079 break; 3080 } 3081 3082 record_offset += record_header->record_size; 3083 } 3084 3085 /* return if the record not found */ 3086 if (result != BP_RESULT_OK) 3087 return result; 3088 3089 /* get slot sizes */ 3090 slot_layout_info->length = record->bracketlen; 3091 slot_layout_info->width = record->bracketwidth; 3092 3093 /* get info for each connector in the slot */ 3094 slot_layout_info->num_of_connectors = record->conn_num; 3095 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3096 slot_layout_info->connectors[j].connector_type = 3097 (enum connector_layout_type) 3098 (record->conn_info[j].connector_type); 3099 switch (record->conn_info[j].connector_type) { 3100 case CONNECTOR_TYPE_DVI_D: 3101 slot_layout_info->connectors[j].connector_type = 3102 CONNECTOR_LAYOUT_TYPE_DVI_D; 3103 slot_layout_info->connectors[j].length = 3104 CONNECTOR_SIZE_DVI; 3105 break; 3106 3107 case CONNECTOR_TYPE_HDMI: 3108 slot_layout_info->connectors[j].connector_type = 3109 CONNECTOR_LAYOUT_TYPE_HDMI; 3110 slot_layout_info->connectors[j].length = 3111 CONNECTOR_SIZE_HDMI; 3112 break; 3113 3114 case CONNECTOR_TYPE_DISPLAY_PORT: 3115 slot_layout_info->connectors[j].connector_type = 3116 CONNECTOR_LAYOUT_TYPE_DP; 3117 slot_layout_info->connectors[j].length = 3118 CONNECTOR_SIZE_DP; 3119 break; 3120 3121 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3122 slot_layout_info->connectors[j].connector_type = 3123 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3124 slot_layout_info->connectors[j].length = 3125 CONNECTOR_SIZE_MINI_DP; 3126 break; 3127 3128 default: 3129 slot_layout_info->connectors[j].connector_type = 3130 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3131 slot_layout_info->connectors[j].length = 3132 CONNECTOR_SIZE_UNKNOWN; 3133 } 3134 3135 slot_layout_info->connectors[j].position = 3136 record->conn_info[j].position; 3137 slot_layout_info->connectors[j].connector_id = 3138 object_id_from_bios_object_id( 3139 record->conn_info[j].connectorobjid); 3140 } 3141 return result; 3142 } 3143 3144 static enum bp_result update_slot_layout_info_v2( 3145 struct dc_bios *dcb, 3146 unsigned int i, 3147 struct slot_layout_info *slot_layout_info) 3148 { 3149 unsigned int record_offset; 3150 struct atom_display_object_path_v3 *object; 3151 struct atom_bracket_layout_record_v2 *record; 3152 struct atom_common_record_header *record_header; 3153 static enum bp_result result; 3154 struct bios_parser *bp; 3155 struct object_info_table *tbl; 3156 struct display_object_info_table_v1_5 *v1_5; 3157 struct graphics_object_id connector_id; 3158 3159 record = NULL; 3160 record_header = NULL; 3161 result = BP_RESULT_NORECORD; 3162 3163 bp = BP_FROM_DCB(dcb); 3164 tbl = &bp->object_info_tbl; 3165 v1_5 = tbl->v1_5; 3166 3167 object = &v1_5->display_path[i]; 3168 record_offset = (unsigned int) 3169 (object->disp_recordoffset) + 3170 (unsigned int)(bp->object_info_tbl_offset); 3171 3172 for (;;) { 3173 3174 record_header = (struct atom_common_record_header *) 3175 GET_IMAGE(struct atom_common_record_header, 3176 record_offset); 3177 if (record_header == NULL) { 3178 result = BP_RESULT_BADBIOSTABLE; 3179 break; 3180 } 3181 3182 /* the end of the list */ 3183 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3184 record_header->record_size == 0) { 3185 break; 3186 } 3187 3188 if (record_header->record_type == 3189 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3190 sizeof(struct atom_bracket_layout_record_v2) 3191 <= record_header->record_size) { 3192 record = (struct atom_bracket_layout_record_v2 *) 3193 (record_header); 3194 result = BP_RESULT_OK; 3195 break; 3196 } 3197 3198 record_offset += record_header->record_size; 3199 } 3200 3201 /* return if the record not found */ 3202 if (result != BP_RESULT_OK) 3203 return result; 3204 3205 /* get slot sizes */ 3206 connector_id = object_id_from_bios_object_id(object->display_objid); 3207 3208 slot_layout_info->length = record->bracketlen; 3209 slot_layout_info->width = record->bracketwidth; 3210 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3211 slot_layout_info->connectors[i].position = record->conn_num; 3212 slot_layout_info->connectors[i].connector_id = connector_id; 3213 3214 switch (connector_id.id) { 3215 case CONNECTOR_ID_SINGLE_LINK_DVID: 3216 case CONNECTOR_ID_DUAL_LINK_DVID: 3217 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3218 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3219 break; 3220 3221 case CONNECTOR_ID_HDMI_TYPE_A: 3222 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3223 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3224 break; 3225 3226 case CONNECTOR_ID_DISPLAY_PORT: 3227 case CONNECTOR_ID_USBC: 3228 if (record->mini_type == MINI_TYPE_NORMAL) { 3229 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3230 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3231 } else { 3232 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3233 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3234 } 3235 break; 3236 3237 default: 3238 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3239 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3240 } 3241 return result; 3242 } 3243 3244 static enum bp_result get_bracket_layout_record( 3245 struct dc_bios *dcb, 3246 unsigned int bracket_layout_id, 3247 struct slot_layout_info *slot_layout_info) 3248 { 3249 unsigned int i; 3250 struct bios_parser *bp = BP_FROM_DCB(dcb); 3251 static enum bp_result result; 3252 struct object_info_table *tbl; 3253 struct display_object_info_table_v1_4 *v1_4; 3254 struct display_object_info_table_v1_5 *v1_5; 3255 3256 if (slot_layout_info == NULL) { 3257 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3258 return BP_RESULT_BADINPUT; 3259 } 3260 tbl = &bp->object_info_tbl; 3261 v1_4 = tbl->v1_4; 3262 3263 result = BP_RESULT_NORECORD; 3264 switch (bp->object_info_tbl.revision.minor) { 3265 case 4: 3266 default: 3267 for (i = 0; i < v1_4->number_of_path; ++i) { 3268 if (bracket_layout_id == 3269 v1_4->display_path[i].display_objid) { 3270 result = update_slot_layout_info(dcb, i, slot_layout_info); 3271 break; 3272 } 3273 } 3274 break; 3275 case 5: 3276 for (i = 0; i < v1_5->number_of_path; ++i) 3277 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3278 break; 3279 } 3280 return result; 3281 } 3282 3283 static enum bp_result bios_get_board_layout_info( 3284 struct dc_bios *dcb, 3285 struct board_layout_info *board_layout_info) 3286 { 3287 unsigned int i; 3288 3289 struct bios_parser *bp; 3290 3291 static enum bp_result record_result; 3292 3293 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3294 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3295 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3296 0, 0 3297 }; 3298 3299 3300 bp = BP_FROM_DCB(dcb); 3301 3302 if (board_layout_info == NULL) { 3303 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3304 return BP_RESULT_BADINPUT; 3305 } 3306 3307 board_layout_info->num_of_slots = 0; 3308 3309 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 3310 record_result = get_bracket_layout_record(dcb, 3311 slot_index_to_vbios_id[i], 3312 &board_layout_info->slots[i]); 3313 3314 if (record_result == BP_RESULT_NORECORD && i > 0) 3315 break; /* no more slots present in bios */ 3316 else if (record_result != BP_RESULT_OK) 3317 return record_result; /* fail */ 3318 3319 ++board_layout_info->num_of_slots; 3320 } 3321 3322 /* all data is valid */ 3323 board_layout_info->is_number_of_slots_valid = 1; 3324 board_layout_info->is_slots_size_valid = 1; 3325 board_layout_info->is_connector_offsets_valid = 1; 3326 board_layout_info->is_connector_lengths_valid = 1; 3327 3328 return BP_RESULT_OK; 3329 } 3330 3331 3332 static uint16_t bios_parser_pack_data_tables( 3333 struct dc_bios *dcb, 3334 void *dst) 3335 { 3336 // TODO: There is data bytes alignment issue, disable it for now. 3337 return 0; 3338 } 3339 3340 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3341 struct bios_parser *bp, 3342 uint32_t rev_major, 3343 uint32_t rev_minor, 3344 uint16_t *dc_golden_table_ver) 3345 { 3346 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3347 uint32_t dc_golden_offset = 0; 3348 *dc_golden_table_ver = 0; 3349 3350 if (!DATA_TABLES(dce_info)) 3351 return NULL; 3352 3353 /* ver.4.4 or higher */ 3354 switch (rev_major) { 3355 case 4: 3356 switch (rev_minor) { 3357 case 4: 3358 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3359 DATA_TABLES(dce_info)); 3360 if (!disp_cntl_tbl_4_4) 3361 return NULL; 3362 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3363 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3364 break; 3365 case 5: 3366 default: 3367 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3368 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3369 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3370 */ 3371 break; 3372 } 3373 break; 3374 } 3375 3376 if (!dc_golden_offset) 3377 return NULL; 3378 3379 if (*dc_golden_table_ver != 1) 3380 return NULL; 3381 3382 return GET_IMAGE(struct atom_dc_golden_table_v1, 3383 dc_golden_offset); 3384 } 3385 3386 static enum bp_result bios_get_atom_dc_golden_table( 3387 struct dc_bios *dcb) 3388 { 3389 struct bios_parser *bp = BP_FROM_DCB(dcb); 3390 enum bp_result result = BP_RESULT_OK; 3391 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3392 struct atom_common_table_header *header; 3393 struct atom_data_revision tbl_revision; 3394 uint16_t dc_golden_table_ver = 0; 3395 3396 header = GET_IMAGE(struct atom_common_table_header, 3397 DATA_TABLES(dce_info)); 3398 if (!header) 3399 return BP_RESULT_UNSUPPORTED; 3400 3401 get_atom_data_table_revision(header, &tbl_revision); 3402 3403 atom_dc_golden_table = bios_get_golden_table(bp, 3404 tbl_revision.major, 3405 tbl_revision.minor, 3406 &dc_golden_table_ver); 3407 3408 if (!atom_dc_golden_table) 3409 return BP_RESULT_UNSUPPORTED; 3410 3411 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3412 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3413 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3414 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3415 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3416 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3417 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3418 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3419 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3420 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3421 3422 return result; 3423 } 3424 3425 3426 static const struct dc_vbios_funcs vbios_funcs = { 3427 .get_connectors_number = bios_parser_get_connectors_number, 3428 3429 .get_connector_id = bios_parser_get_connector_id, 3430 3431 .get_src_obj = bios_parser_get_src_obj, 3432 3433 .get_i2c_info = bios_parser_get_i2c_info, 3434 3435 .get_hpd_info = bios_parser_get_hpd_info, 3436 3437 .get_device_tag = bios_parser_get_device_tag, 3438 3439 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3440 3441 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3442 3443 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3444 3445 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3446 3447 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3448 3449 .is_device_id_supported = bios_parser_is_device_id_supported, 3450 3451 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3452 3453 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3454 3455 3456 /* COMMANDS */ 3457 .encoder_control = bios_parser_encoder_control, 3458 3459 .transmitter_control = bios_parser_transmitter_control, 3460 3461 .enable_crtc = bios_parser_enable_crtc, 3462 3463 .set_pixel_clock = bios_parser_set_pixel_clock, 3464 3465 .set_dce_clock = bios_parser_set_dce_clock, 3466 3467 .program_crtc_timing = bios_parser_program_crtc_timing, 3468 3469 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3470 3471 .bios_parser_destroy = firmware_parser_destroy, 3472 3473 .get_board_layout_info = bios_get_board_layout_info, 3474 /* TODO: use this fn in hw init?*/ 3475 .pack_data_tables = bios_parser_pack_data_tables, 3476 3477 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3478 3479 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3480 3481 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3482 3483 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3484 3485 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3486 3487 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3488 3489 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3490 }; 3491 3492 static bool bios_parser2_construct( 3493 struct bios_parser *bp, 3494 struct bp_init_data *init, 3495 enum dce_version dce_version) 3496 { 3497 uint16_t *rom_header_offset = NULL; 3498 struct atom_rom_header_v2_2 *rom_header = NULL; 3499 struct display_object_info_table_v1_4 *object_info_tbl; 3500 struct atom_data_revision tbl_rev = {0}; 3501 3502 if (!init) 3503 return false; 3504 3505 if (!init->bios) 3506 return false; 3507 3508 bp->base.funcs = &vbios_funcs; 3509 bp->base.bios = init->bios; 3510 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3511 3512 bp->base.ctx = init->ctx; 3513 3514 bp->base.bios_local_image = NULL; 3515 3516 rom_header_offset = 3517 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3518 3519 if (!rom_header_offset) 3520 return false; 3521 3522 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3523 3524 if (!rom_header) 3525 return false; 3526 3527 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3528 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3529 return false; 3530 3531 bp->master_data_tbl = 3532 GET_IMAGE(struct atom_master_data_table_v2_1, 3533 rom_header->masterdatatable_offset); 3534 3535 if (!bp->master_data_tbl) 3536 return false; 3537 3538 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3539 3540 if (!bp->object_info_tbl_offset) 3541 return false; 3542 3543 object_info_tbl = 3544 GET_IMAGE(struct display_object_info_table_v1_4, 3545 bp->object_info_tbl_offset); 3546 3547 if (!object_info_tbl) 3548 return false; 3549 3550 get_atom_data_table_revision(&object_info_tbl->table_header, 3551 &bp->object_info_tbl.revision); 3552 3553 if (bp->object_info_tbl.revision.major == 1 3554 && bp->object_info_tbl.revision.minor == 4) { 3555 struct display_object_info_table_v1_4 *tbl_v1_4; 3556 3557 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3558 bp->object_info_tbl_offset); 3559 if (!tbl_v1_4) 3560 return false; 3561 3562 bp->object_info_tbl.v1_4 = tbl_v1_4; 3563 } else if (bp->object_info_tbl.revision.major == 1 3564 && bp->object_info_tbl.revision.minor == 5) { 3565 struct display_object_info_table_v1_5 *tbl_v1_5; 3566 3567 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3568 bp->object_info_tbl_offset); 3569 if (!tbl_v1_5) 3570 return false; 3571 3572 bp->object_info_tbl.v1_5 = tbl_v1_5; 3573 } else { 3574 ASSERT(0); 3575 return false; 3576 } 3577 3578 dal_firmware_parser_init_cmd_tbl(bp); 3579 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3580 3581 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3582 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3583 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3584 3585 return true; 3586 } 3587 3588 struct dc_bios *firmware_parser_create( 3589 struct bp_init_data *init, 3590 enum dce_version dce_version) 3591 { 3592 struct bios_parser *bp = NULL; 3593 3594 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 3595 if (!bp) 3596 return NULL; 3597 3598 if (bios_parser2_construct(bp, init, dce_version)) 3599 return &bp->base; 3600 3601 kfree(bp); 3602 return NULL; 3603 } 3604 3605 3606