1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @dcb: pointer to the DC BIOS 489 * @gpio_id: GPIO ID 490 * @info: GpioPin information structure 491 * return: Bios parser result code 492 * note: 493 * to get the GPIO PIN INFO, we need: 494 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 495 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 496 * to get the registerA offset/mask 497 */ 498 static enum bp_result bios_parser_get_gpio_pin_info( 499 struct dc_bios *dcb, 500 uint32_t gpio_id, 501 struct gpio_pin_info *info) 502 { 503 struct bios_parser *bp = BP_FROM_DCB(dcb); 504 struct atom_gpio_pin_lut_v2_1 *header; 505 uint32_t count = 0; 506 uint32_t i = 0; 507 508 if (!DATA_TABLES(gpio_pin_lut)) 509 return BP_RESULT_BADBIOSTABLE; 510 511 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 512 DATA_TABLES(gpio_pin_lut)); 513 if (!header) 514 return BP_RESULT_BADBIOSTABLE; 515 516 if (sizeof(struct atom_common_table_header) + 517 sizeof(struct atom_gpio_pin_assignment) 518 > le16_to_cpu(header->table_header.structuresize)) 519 return BP_RESULT_BADBIOSTABLE; 520 521 if (header->table_header.content_revision != 1) 522 return BP_RESULT_UNSUPPORTED; 523 524 /* Temporary hard code gpio pin info */ 525 #if defined(FOR_SIMNOW_BOOT) 526 { 527 struct atom_gpio_pin_assignment gpio_pin[8] = { 528 {0x5db5, 0, 0, 1, 0}, 529 {0x5db5, 8, 8, 2, 0}, 530 {0x5db5, 0x10, 0x10, 3, 0}, 531 {0x5db5, 0x18, 0x14, 4, 0}, 532 {0x5db5, 0x1A, 0x18, 5, 0}, 533 {0x5db5, 0x1C, 0x1C, 6, 0}, 534 }; 535 536 count = 6; 537 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 538 } 539 #else 540 count = (le16_to_cpu(header->table_header.structuresize) 541 - sizeof(struct atom_common_table_header)) 542 / sizeof(struct atom_gpio_pin_assignment); 543 #endif 544 for (i = 0; i < count; ++i) { 545 if (header->gpio_pin[i].gpio_id != gpio_id) 546 continue; 547 548 info->offset = 549 (uint32_t) le16_to_cpu( 550 header->gpio_pin[i].data_a_reg_index); 551 info->offset_y = info->offset + 2; 552 info->offset_en = info->offset + 1; 553 info->offset_mask = info->offset - 1; 554 555 info->mask = (uint32_t) (1 << 556 header->gpio_pin[i].gpio_bitshift); 557 info->mask_y = info->mask + 2; 558 info->mask_en = info->mask + 1; 559 info->mask_mask = info->mask - 1; 560 561 return BP_RESULT_OK; 562 } 563 564 return BP_RESULT_NORECORD; 565 } 566 567 static struct device_id device_type_from_device_id(uint16_t device_id) 568 { 569 570 struct device_id result_device_id; 571 572 result_device_id.raw_device_tag = device_id; 573 574 switch (device_id) { 575 case ATOM_DISPLAY_LCD1_SUPPORT: 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 result_device_id.enum_id = 1; 578 break; 579 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 580 581 case ATOM_DISPLAY_LCD2_SUPPORT: 582 result_device_id.device_type = DEVICE_TYPE_LCD; 583 result_device_id.enum_id = 2; 584 break; 585 #endif 586 587 case ATOM_DISPLAY_DFP1_SUPPORT: 588 result_device_id.device_type = DEVICE_TYPE_DFP; 589 result_device_id.enum_id = 1; 590 break; 591 592 case ATOM_DISPLAY_DFP2_SUPPORT: 593 result_device_id.device_type = DEVICE_TYPE_DFP; 594 result_device_id.enum_id = 2; 595 break; 596 597 case ATOM_DISPLAY_DFP3_SUPPORT: 598 result_device_id.device_type = DEVICE_TYPE_DFP; 599 result_device_id.enum_id = 3; 600 break; 601 602 case ATOM_DISPLAY_DFP4_SUPPORT: 603 result_device_id.device_type = DEVICE_TYPE_DFP; 604 result_device_id.enum_id = 4; 605 break; 606 607 case ATOM_DISPLAY_DFP5_SUPPORT: 608 result_device_id.device_type = DEVICE_TYPE_DFP; 609 result_device_id.enum_id = 5; 610 break; 611 612 case ATOM_DISPLAY_DFP6_SUPPORT: 613 result_device_id.device_type = DEVICE_TYPE_DFP; 614 result_device_id.enum_id = 6; 615 break; 616 617 default: 618 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 619 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 620 result_device_id.enum_id = 0; 621 } 622 return result_device_id; 623 } 624 625 static enum bp_result bios_parser_get_device_tag( 626 struct dc_bios *dcb, 627 struct graphics_object_id connector_object_id, 628 uint32_t device_tag_index, 629 struct connector_device_tag_info *info) 630 { 631 struct bios_parser *bp = BP_FROM_DCB(dcb); 632 struct atom_display_object_path_v2 *object; 633 634 if (!info) 635 return BP_RESULT_BADINPUT; 636 637 /* getBiosObject will return MXM object */ 638 object = get_bios_object(bp, connector_object_id); 639 640 if (!object) { 641 BREAK_TO_DEBUGGER(); /* Invalid object id */ 642 return BP_RESULT_BADINPUT; 643 } 644 645 info->acpi_device = 0; /* BIOS no longer provides this */ 646 info->dev_id = device_type_from_device_id(object->device_tag); 647 648 return BP_RESULT_OK; 649 } 650 651 static enum bp_result get_ss_info_v4_1( 652 struct bios_parser *bp, 653 uint32_t id, 654 uint32_t index, 655 struct spread_spectrum_info *ss_info) 656 { 657 enum bp_result result = BP_RESULT_OK; 658 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 659 struct atom_smu_info_v3_3 *smu_info = NULL; 660 661 if (!ss_info) 662 return BP_RESULT_BADINPUT; 663 664 if (!DATA_TABLES(dce_info)) 665 return BP_RESULT_BADBIOSTABLE; 666 667 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 668 DATA_TABLES(dce_info)); 669 if (!disp_cntl_tbl) 670 return BP_RESULT_BADBIOSTABLE; 671 672 673 ss_info->type.STEP_AND_DELAY_INFO = false; 674 ss_info->spread_percentage_divider = 1000; 675 /* BIOS no longer uses target clock. Always enable for now */ 676 ss_info->target_clock_range = 0xffffffff; 677 678 switch (id) { 679 case AS_SIGNAL_TYPE_DVI: 680 ss_info->spread_spectrum_percentage = 681 disp_cntl_tbl->dvi_ss_percentage; 682 ss_info->spread_spectrum_range = 683 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 684 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 685 ss_info->type.CENTER_MODE = true; 686 break; 687 case AS_SIGNAL_TYPE_HDMI: 688 ss_info->spread_spectrum_percentage = 689 disp_cntl_tbl->hdmi_ss_percentage; 690 ss_info->spread_spectrum_range = 691 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 692 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 693 ss_info->type.CENTER_MODE = true; 694 break; 695 /* TODO LVDS not support anymore? */ 696 case AS_SIGNAL_TYPE_DISPLAY_PORT: 697 ss_info->spread_spectrum_percentage = 698 disp_cntl_tbl->dp_ss_percentage; 699 ss_info->spread_spectrum_range = 700 disp_cntl_tbl->dp_ss_rate_10hz * 10; 701 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 702 ss_info->type.CENTER_MODE = true; 703 break; 704 case AS_SIGNAL_TYPE_GPU_PLL: 705 /* atom_firmware: DAL only get data from dce_info table. 706 * if data within smu_info is needed for DAL, VBIOS should 707 * copy it into dce_info 708 */ 709 result = BP_RESULT_UNSUPPORTED; 710 break; 711 case AS_SIGNAL_TYPE_XGMI: 712 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 713 DATA_TABLES(smu_info)); 714 if (!smu_info) 715 return BP_RESULT_BADBIOSTABLE; 716 717 ss_info->spread_spectrum_percentage = 718 smu_info->waflclk_ss_percentage; 719 ss_info->spread_spectrum_range = 720 smu_info->gpuclk_ss_rate_10hz * 10; 721 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 722 ss_info->type.CENTER_MODE = true; 723 break; 724 default: 725 result = BP_RESULT_UNSUPPORTED; 726 } 727 728 return result; 729 } 730 731 static enum bp_result get_ss_info_v4_2( 732 struct bios_parser *bp, 733 uint32_t id, 734 uint32_t index, 735 struct spread_spectrum_info *ss_info) 736 { 737 enum bp_result result = BP_RESULT_OK; 738 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 739 struct atom_smu_info_v3_1 *smu_info = NULL; 740 741 if (!ss_info) 742 return BP_RESULT_BADINPUT; 743 744 if (!DATA_TABLES(dce_info)) 745 return BP_RESULT_BADBIOSTABLE; 746 747 if (!DATA_TABLES(smu_info)) 748 return BP_RESULT_BADBIOSTABLE; 749 750 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 751 DATA_TABLES(dce_info)); 752 if (!disp_cntl_tbl) 753 return BP_RESULT_BADBIOSTABLE; 754 755 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 756 if (!smu_info) 757 return BP_RESULT_BADBIOSTABLE; 758 759 ss_info->type.STEP_AND_DELAY_INFO = false; 760 ss_info->spread_percentage_divider = 1000; 761 /* BIOS no longer uses target clock. Always enable for now */ 762 ss_info->target_clock_range = 0xffffffff; 763 764 switch (id) { 765 case AS_SIGNAL_TYPE_DVI: 766 ss_info->spread_spectrum_percentage = 767 disp_cntl_tbl->dvi_ss_percentage; 768 ss_info->spread_spectrum_range = 769 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 770 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 771 ss_info->type.CENTER_MODE = true; 772 break; 773 case AS_SIGNAL_TYPE_HDMI: 774 ss_info->spread_spectrum_percentage = 775 disp_cntl_tbl->hdmi_ss_percentage; 776 ss_info->spread_spectrum_range = 777 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 778 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 779 ss_info->type.CENTER_MODE = true; 780 break; 781 /* TODO LVDS not support anymore? */ 782 case AS_SIGNAL_TYPE_DISPLAY_PORT: 783 ss_info->spread_spectrum_percentage = 784 smu_info->gpuclk_ss_percentage; 785 ss_info->spread_spectrum_range = 786 smu_info->gpuclk_ss_rate_10hz * 10; 787 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 788 ss_info->type.CENTER_MODE = true; 789 break; 790 case AS_SIGNAL_TYPE_GPU_PLL: 791 /* atom_firmware: DAL only get data from dce_info table. 792 * if data within smu_info is needed for DAL, VBIOS should 793 * copy it into dce_info 794 */ 795 result = BP_RESULT_UNSUPPORTED; 796 break; 797 default: 798 result = BP_RESULT_UNSUPPORTED; 799 } 800 801 return result; 802 } 803 804 /** 805 * bios_parser_get_spread_spectrum_info 806 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 807 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 808 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 809 * ver 3.1, 810 * there is only one entry for each signal /ss id. However, there is 811 * no planning of supporting multiple spread Sprectum entry for EverGreen 812 * @dcb: pointer to the DC BIOS 813 * @signal: ASSignalType to be converted to info index 814 * @index: number of entries that match the converted info index 815 * @ss_info: sprectrum information structure, 816 * return: Bios parser result code 817 */ 818 static enum bp_result bios_parser_get_spread_spectrum_info( 819 struct dc_bios *dcb, 820 enum as_signal_type signal, 821 uint32_t index, 822 struct spread_spectrum_info *ss_info) 823 { 824 struct bios_parser *bp = BP_FROM_DCB(dcb); 825 enum bp_result result = BP_RESULT_UNSUPPORTED; 826 struct atom_common_table_header *header; 827 struct atom_data_revision tbl_revision; 828 829 if (!ss_info) /* check for bad input */ 830 return BP_RESULT_BADINPUT; 831 832 if (!DATA_TABLES(dce_info)) 833 return BP_RESULT_UNSUPPORTED; 834 835 header = GET_IMAGE(struct atom_common_table_header, 836 DATA_TABLES(dce_info)); 837 get_atom_data_table_revision(header, &tbl_revision); 838 839 switch (tbl_revision.major) { 840 case 4: 841 switch (tbl_revision.minor) { 842 case 1: 843 return get_ss_info_v4_1(bp, signal, index, ss_info); 844 case 2: 845 case 3: 846 case 4: 847 return get_ss_info_v4_2(bp, signal, index, ss_info); 848 default: 849 ASSERT(0); 850 break; 851 } 852 break; 853 default: 854 break; 855 } 856 /* there can not be more then one entry for SS Info table */ 857 return result; 858 } 859 860 static enum bp_result get_soc_bb_info_v4_4( 861 struct bios_parser *bp, 862 struct bp_soc_bb_info *soc_bb_info) 863 { 864 enum bp_result result = BP_RESULT_OK; 865 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 866 867 if (!soc_bb_info) 868 return BP_RESULT_BADINPUT; 869 870 if (!DATA_TABLES(dce_info)) 871 return BP_RESULT_BADBIOSTABLE; 872 873 if (!DATA_TABLES(smu_info)) 874 return BP_RESULT_BADBIOSTABLE; 875 876 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 877 DATA_TABLES(dce_info)); 878 if (!disp_cntl_tbl) 879 return BP_RESULT_BADBIOSTABLE; 880 881 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 882 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 883 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 884 885 return result; 886 } 887 888 static enum bp_result bios_parser_get_soc_bb_info( 889 struct dc_bios *dcb, 890 struct bp_soc_bb_info *soc_bb_info) 891 { 892 struct bios_parser *bp = BP_FROM_DCB(dcb); 893 enum bp_result result = BP_RESULT_UNSUPPORTED; 894 struct atom_common_table_header *header; 895 struct atom_data_revision tbl_revision; 896 897 if (!soc_bb_info) /* check for bad input */ 898 return BP_RESULT_BADINPUT; 899 900 if (!DATA_TABLES(dce_info)) 901 return BP_RESULT_UNSUPPORTED; 902 903 header = GET_IMAGE(struct atom_common_table_header, 904 DATA_TABLES(dce_info)); 905 get_atom_data_table_revision(header, &tbl_revision); 906 907 switch (tbl_revision.major) { 908 case 4: 909 switch (tbl_revision.minor) { 910 case 1: 911 case 2: 912 case 3: 913 break; 914 case 4: 915 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 916 break; 917 default: 918 break; 919 } 920 break; 921 default: 922 break; 923 } 924 925 return result; 926 } 927 928 static enum bp_result get_disp_caps_v4_1( 929 struct bios_parser *bp, 930 uint8_t *dce_caps) 931 { 932 enum bp_result result = BP_RESULT_OK; 933 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 934 935 if (!dce_caps) 936 return BP_RESULT_BADINPUT; 937 938 if (!DATA_TABLES(dce_info)) 939 return BP_RESULT_BADBIOSTABLE; 940 941 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 942 DATA_TABLES(dce_info)); 943 944 if (!disp_cntl_tbl) 945 return BP_RESULT_BADBIOSTABLE; 946 947 *dce_caps = disp_cntl_tbl->display_caps; 948 949 return result; 950 } 951 952 static enum bp_result get_disp_caps_v4_2( 953 struct bios_parser *bp, 954 uint8_t *dce_caps) 955 { 956 enum bp_result result = BP_RESULT_OK; 957 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 958 959 if (!dce_caps) 960 return BP_RESULT_BADINPUT; 961 962 if (!DATA_TABLES(dce_info)) 963 return BP_RESULT_BADBIOSTABLE; 964 965 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 966 DATA_TABLES(dce_info)); 967 968 if (!disp_cntl_tbl) 969 return BP_RESULT_BADBIOSTABLE; 970 971 *dce_caps = disp_cntl_tbl->display_caps; 972 973 return result; 974 } 975 976 static enum bp_result get_disp_caps_v4_3( 977 struct bios_parser *bp, 978 uint8_t *dce_caps) 979 { 980 enum bp_result result = BP_RESULT_OK; 981 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 982 983 if (!dce_caps) 984 return BP_RESULT_BADINPUT; 985 986 if (!DATA_TABLES(dce_info)) 987 return BP_RESULT_BADBIOSTABLE; 988 989 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 990 DATA_TABLES(dce_info)); 991 992 if (!disp_cntl_tbl) 993 return BP_RESULT_BADBIOSTABLE; 994 995 *dce_caps = disp_cntl_tbl->display_caps; 996 997 return result; 998 } 999 1000 static enum bp_result get_disp_caps_v4_4( 1001 struct bios_parser *bp, 1002 uint8_t *dce_caps) 1003 { 1004 enum bp_result result = BP_RESULT_OK; 1005 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1006 1007 if (!dce_caps) 1008 return BP_RESULT_BADINPUT; 1009 1010 if (!DATA_TABLES(dce_info)) 1011 return BP_RESULT_BADBIOSTABLE; 1012 1013 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1014 DATA_TABLES(dce_info)); 1015 1016 if (!disp_cntl_tbl) 1017 return BP_RESULT_BADBIOSTABLE; 1018 1019 *dce_caps = disp_cntl_tbl->display_caps; 1020 1021 return result; 1022 } 1023 1024 static enum bp_result bios_parser_get_lttpr_interop( 1025 struct dc_bios *dcb, 1026 uint8_t *dce_caps) 1027 { 1028 struct bios_parser *bp = BP_FROM_DCB(dcb); 1029 enum bp_result result = BP_RESULT_UNSUPPORTED; 1030 struct atom_common_table_header *header; 1031 struct atom_data_revision tbl_revision; 1032 1033 if (!DATA_TABLES(dce_info)) 1034 return BP_RESULT_UNSUPPORTED; 1035 1036 header = GET_IMAGE(struct atom_common_table_header, 1037 DATA_TABLES(dce_info)); 1038 get_atom_data_table_revision(header, &tbl_revision); 1039 switch (tbl_revision.major) { 1040 case 4: 1041 switch (tbl_revision.minor) { 1042 case 1: 1043 result = get_disp_caps_v4_1(bp, dce_caps); 1044 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1045 break; 1046 case 2: 1047 result = get_disp_caps_v4_2(bp, dce_caps); 1048 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1049 break; 1050 case 3: 1051 result = get_disp_caps_v4_3(bp, dce_caps); 1052 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1053 break; 1054 case 4: 1055 result = get_disp_caps_v4_4(bp, dce_caps); 1056 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1057 break; 1058 default: 1059 break; 1060 } 1061 break; 1062 default: 1063 break; 1064 } 1065 1066 return result; 1067 } 1068 1069 static enum bp_result bios_parser_get_lttpr_caps( 1070 struct dc_bios *dcb, 1071 uint8_t *dce_caps) 1072 { 1073 struct bios_parser *bp = BP_FROM_DCB(dcb); 1074 enum bp_result result = BP_RESULT_UNSUPPORTED; 1075 struct atom_common_table_header *header; 1076 struct atom_data_revision tbl_revision; 1077 1078 if (!DATA_TABLES(dce_info)) 1079 return BP_RESULT_UNSUPPORTED; 1080 1081 header = GET_IMAGE(struct atom_common_table_header, 1082 DATA_TABLES(dce_info)); 1083 get_atom_data_table_revision(header, &tbl_revision); 1084 switch (tbl_revision.major) { 1085 case 4: 1086 switch (tbl_revision.minor) { 1087 case 1: 1088 result = get_disp_caps_v4_1(bp, dce_caps); 1089 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1090 break; 1091 case 2: 1092 result = get_disp_caps_v4_2(bp, dce_caps); 1093 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1094 break; 1095 case 3: 1096 result = get_disp_caps_v4_3(bp, dce_caps); 1097 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1098 break; 1099 case 4: 1100 result = get_disp_caps_v4_4(bp, dce_caps); 1101 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1102 break; 1103 default: 1104 break; 1105 } 1106 break; 1107 default: 1108 break; 1109 } 1110 1111 return result; 1112 } 1113 1114 static enum bp_result get_embedded_panel_info_v2_1( 1115 struct bios_parser *bp, 1116 struct embedded_panel_info *info) 1117 { 1118 struct lcd_info_v2_1 *lvds; 1119 1120 if (!info) 1121 return BP_RESULT_BADINPUT; 1122 1123 if (!DATA_TABLES(lcd_info)) 1124 return BP_RESULT_UNSUPPORTED; 1125 1126 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1127 1128 if (!lvds) 1129 return BP_RESULT_BADBIOSTABLE; 1130 1131 /* TODO: previous vv1_3, should v2_1 */ 1132 if (!((lvds->table_header.format_revision == 2) 1133 && (lvds->table_header.content_revision >= 1))) 1134 return BP_RESULT_UNSUPPORTED; 1135 1136 memset(info, 0, sizeof(struct embedded_panel_info)); 1137 1138 /* We need to convert from 10KHz units into KHz units */ 1139 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1140 /* usHActive does not include borders, according to VBIOS team */ 1141 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1142 /* usHBlanking_Time includes borders, so we should really be 1143 * subtractingborders duing this translation, but LVDS generally 1144 * doesn't have borders, so we should be okay leaving this as is for 1145 * now. May need to revisit if we ever have LVDS with borders 1146 */ 1147 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1148 /* usVActive does not include borders, according to VBIOS team*/ 1149 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1150 /* usVBlanking_Time includes borders, so we should really be 1151 * subtracting borders duing this translation, but LVDS generally 1152 * doesn't have borders, so we should be okay leaving this as is for 1153 * now. May need to revisit if we ever have LVDS with borders 1154 */ 1155 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1156 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1157 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1158 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1159 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1160 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1161 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1162 1163 /* not provided by VBIOS */ 1164 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1165 1166 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1167 & ATOM_HSYNC_POLARITY); 1168 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1169 & ATOM_VSYNC_POLARITY); 1170 1171 /* not provided by VBIOS */ 1172 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1173 1174 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1175 & ATOM_H_REPLICATIONBY2); 1176 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1177 & ATOM_V_REPLICATIONBY2); 1178 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1179 & ATOM_COMPOSITESYNC); 1180 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1181 1182 /* not provided by VBIOS*/ 1183 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1184 /* not provided by VBIOS*/ 1185 info->ss_id = 0; 1186 1187 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1188 1189 return BP_RESULT_OK; 1190 } 1191 1192 static enum bp_result bios_parser_get_embedded_panel_info( 1193 struct dc_bios *dcb, 1194 struct embedded_panel_info *info) 1195 { 1196 struct bios_parser 1197 *bp = BP_FROM_DCB(dcb); 1198 struct atom_common_table_header *header; 1199 struct atom_data_revision tbl_revision; 1200 1201 if (!DATA_TABLES(lcd_info)) 1202 return BP_RESULT_FAILURE; 1203 1204 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1205 1206 if (!header) 1207 return BP_RESULT_BADBIOSTABLE; 1208 1209 get_atom_data_table_revision(header, &tbl_revision); 1210 1211 switch (tbl_revision.major) { 1212 case 2: 1213 switch (tbl_revision.minor) { 1214 case 1: 1215 return get_embedded_panel_info_v2_1(bp, info); 1216 default: 1217 break; 1218 } 1219 break; 1220 default: 1221 break; 1222 } 1223 1224 return BP_RESULT_FAILURE; 1225 } 1226 1227 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1228 { 1229 enum dal_device_type device_type = device_id.device_type; 1230 uint32_t enum_id = device_id.enum_id; 1231 1232 switch (device_type) { 1233 case DEVICE_TYPE_LCD: 1234 switch (enum_id) { 1235 case 1: 1236 return ATOM_DISPLAY_LCD1_SUPPORT; 1237 default: 1238 break; 1239 } 1240 break; 1241 case DEVICE_TYPE_DFP: 1242 switch (enum_id) { 1243 case 1: 1244 return ATOM_DISPLAY_DFP1_SUPPORT; 1245 case 2: 1246 return ATOM_DISPLAY_DFP2_SUPPORT; 1247 case 3: 1248 return ATOM_DISPLAY_DFP3_SUPPORT; 1249 case 4: 1250 return ATOM_DISPLAY_DFP4_SUPPORT; 1251 case 5: 1252 return ATOM_DISPLAY_DFP5_SUPPORT; 1253 case 6: 1254 return ATOM_DISPLAY_DFP6_SUPPORT; 1255 default: 1256 break; 1257 } 1258 break; 1259 default: 1260 break; 1261 } 1262 1263 /* Unidentified device ID, return empty support mask. */ 1264 return 0; 1265 } 1266 1267 static bool bios_parser_is_device_id_supported( 1268 struct dc_bios *dcb, 1269 struct device_id id) 1270 { 1271 struct bios_parser *bp = BP_FROM_DCB(dcb); 1272 1273 uint32_t mask = get_support_mask_for_device_id(id); 1274 1275 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1276 mask) != 0; 1277 } 1278 1279 static uint32_t bios_parser_get_ss_entry_number( 1280 struct dc_bios *dcb, 1281 enum as_signal_type signal) 1282 { 1283 /* TODO: DAL2 atomfirmware implementation does not need this. 1284 * why DAL3 need this? 1285 */ 1286 return 1; 1287 } 1288 1289 static enum bp_result bios_parser_transmitter_control( 1290 struct dc_bios *dcb, 1291 struct bp_transmitter_control *cntl) 1292 { 1293 struct bios_parser *bp = BP_FROM_DCB(dcb); 1294 1295 if (!bp->cmd_tbl.transmitter_control) 1296 return BP_RESULT_FAILURE; 1297 1298 return bp->cmd_tbl.transmitter_control(bp, cntl); 1299 } 1300 1301 static enum bp_result bios_parser_encoder_control( 1302 struct dc_bios *dcb, 1303 struct bp_encoder_control *cntl) 1304 { 1305 struct bios_parser *bp = BP_FROM_DCB(dcb); 1306 1307 if (!bp->cmd_tbl.dig_encoder_control) 1308 return BP_RESULT_FAILURE; 1309 1310 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1311 } 1312 1313 static enum bp_result bios_parser_set_pixel_clock( 1314 struct dc_bios *dcb, 1315 struct bp_pixel_clock_parameters *bp_params) 1316 { 1317 struct bios_parser *bp = BP_FROM_DCB(dcb); 1318 1319 if (!bp->cmd_tbl.set_pixel_clock) 1320 return BP_RESULT_FAILURE; 1321 1322 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1323 } 1324 1325 static enum bp_result bios_parser_set_dce_clock( 1326 struct dc_bios *dcb, 1327 struct bp_set_dce_clock_parameters *bp_params) 1328 { 1329 struct bios_parser *bp = BP_FROM_DCB(dcb); 1330 1331 if (!bp->cmd_tbl.set_dce_clock) 1332 return BP_RESULT_FAILURE; 1333 1334 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1335 } 1336 1337 static enum bp_result bios_parser_program_crtc_timing( 1338 struct dc_bios *dcb, 1339 struct bp_hw_crtc_timing_parameters *bp_params) 1340 { 1341 struct bios_parser *bp = BP_FROM_DCB(dcb); 1342 1343 if (!bp->cmd_tbl.set_crtc_timing) 1344 return BP_RESULT_FAILURE; 1345 1346 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1347 } 1348 1349 static enum bp_result bios_parser_enable_crtc( 1350 struct dc_bios *dcb, 1351 enum controller_id id, 1352 bool enable) 1353 { 1354 struct bios_parser *bp = BP_FROM_DCB(dcb); 1355 1356 if (!bp->cmd_tbl.enable_crtc) 1357 return BP_RESULT_FAILURE; 1358 1359 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1360 } 1361 1362 static enum bp_result bios_parser_enable_disp_power_gating( 1363 struct dc_bios *dcb, 1364 enum controller_id controller_id, 1365 enum bp_pipe_control_action action) 1366 { 1367 struct bios_parser *bp = BP_FROM_DCB(dcb); 1368 1369 if (!bp->cmd_tbl.enable_disp_power_gating) 1370 return BP_RESULT_FAILURE; 1371 1372 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1373 action); 1374 } 1375 1376 static enum bp_result bios_parser_enable_lvtma_control( 1377 struct dc_bios *dcb, 1378 uint8_t uc_pwr_on, 1379 uint8_t panel_instance) 1380 { 1381 struct bios_parser *bp = BP_FROM_DCB(dcb); 1382 1383 if (!bp->cmd_tbl.enable_lvtma_control) 1384 return BP_RESULT_FAILURE; 1385 1386 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1387 } 1388 1389 static bool bios_parser_is_accelerated_mode( 1390 struct dc_bios *dcb) 1391 { 1392 return bios_is_accelerated_mode(dcb); 1393 } 1394 1395 /** 1396 * bios_parser_set_scratch_critical_state - update critical state bit 1397 * in VBIOS scratch register 1398 * 1399 * @dcb: pointer to the DC BIO 1400 * @state: set or reset state 1401 */ 1402 static void bios_parser_set_scratch_critical_state( 1403 struct dc_bios *dcb, 1404 bool state) 1405 { 1406 bios_set_scratch_critical_state(dcb, state); 1407 } 1408 1409 static enum bp_result bios_parser_get_firmware_info( 1410 struct dc_bios *dcb, 1411 struct dc_firmware_info *info) 1412 { 1413 struct bios_parser *bp = BP_FROM_DCB(dcb); 1414 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1415 struct atom_common_table_header *header; 1416 1417 struct atom_data_revision revision; 1418 1419 if (info && DATA_TABLES(firmwareinfo)) { 1420 header = GET_IMAGE(struct atom_common_table_header, 1421 DATA_TABLES(firmwareinfo)); 1422 get_atom_data_table_revision(header, &revision); 1423 switch (revision.major) { 1424 case 3: 1425 switch (revision.minor) { 1426 case 1: 1427 result = get_firmware_info_v3_1(bp, info); 1428 break; 1429 case 2: 1430 case 3: 1431 case 4: 1432 result = get_firmware_info_v3_2(bp, info); 1433 break; 1434 default: 1435 break; 1436 } 1437 break; 1438 default: 1439 break; 1440 } 1441 } 1442 1443 return result; 1444 } 1445 1446 static enum bp_result get_firmware_info_v3_1( 1447 struct bios_parser *bp, 1448 struct dc_firmware_info *info) 1449 { 1450 struct atom_firmware_info_v3_1 *firmware_info; 1451 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1452 1453 if (!info) 1454 return BP_RESULT_BADINPUT; 1455 1456 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1457 DATA_TABLES(firmwareinfo)); 1458 1459 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1460 DATA_TABLES(dce_info)); 1461 1462 if (!firmware_info || !dce_info) 1463 return BP_RESULT_BADBIOSTABLE; 1464 1465 memset(info, 0, sizeof(*info)); 1466 1467 /* Pixel clock pll information. */ 1468 /* We need to convert from 10KHz units into KHz units */ 1469 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1470 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1471 1472 /* 27MHz for Vega10: */ 1473 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1474 1475 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1476 if (info->pll_info.crystal_frequency == 0) 1477 info->pll_info.crystal_frequency = 27000; 1478 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1479 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1480 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1481 1482 /* Get GPU PLL VCO Clock */ 1483 1484 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1485 /* VBIOS gives in 10KHz */ 1486 info->smu_gpu_pll_output_freq = 1487 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1488 } 1489 1490 info->oem_i2c_present = false; 1491 1492 return BP_RESULT_OK; 1493 } 1494 1495 static enum bp_result get_firmware_info_v3_2( 1496 struct bios_parser *bp, 1497 struct dc_firmware_info *info) 1498 { 1499 struct atom_firmware_info_v3_2 *firmware_info; 1500 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1501 struct atom_common_table_header *header; 1502 struct atom_data_revision revision; 1503 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1504 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1505 1506 if (!info) 1507 return BP_RESULT_BADINPUT; 1508 1509 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1510 DATA_TABLES(firmwareinfo)); 1511 1512 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1513 DATA_TABLES(dce_info)); 1514 1515 if (!firmware_info || !dce_info) 1516 return BP_RESULT_BADBIOSTABLE; 1517 1518 memset(info, 0, sizeof(*info)); 1519 1520 header = GET_IMAGE(struct atom_common_table_header, 1521 DATA_TABLES(smu_info)); 1522 get_atom_data_table_revision(header, &revision); 1523 1524 if (revision.minor == 2) { 1525 /* Vega12 */ 1526 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1527 DATA_TABLES(smu_info)); 1528 1529 if (!smu_info_v3_2) 1530 return BP_RESULT_BADBIOSTABLE; 1531 1532 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1533 } else if (revision.minor == 3) { 1534 /* Vega20 */ 1535 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1536 DATA_TABLES(smu_info)); 1537 1538 if (!smu_info_v3_3) 1539 return BP_RESULT_BADBIOSTABLE; 1540 1541 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1542 } 1543 1544 // We need to convert from 10KHz units into KHz units. 1545 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1546 1547 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1548 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1549 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1550 if (info->pll_info.crystal_frequency == 0) { 1551 if (revision.minor == 2) 1552 info->pll_info.crystal_frequency = 27000; 1553 else if (revision.minor == 3) 1554 info->pll_info.crystal_frequency = 100000; 1555 } 1556 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1557 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1558 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1559 1560 /* Get GPU PLL VCO Clock */ 1561 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1562 if (revision.minor == 2) 1563 info->smu_gpu_pll_output_freq = 1564 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1565 else if (revision.minor == 3) 1566 info->smu_gpu_pll_output_freq = 1567 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1568 } 1569 1570 if (firmware_info->board_i2c_feature_id == 0x2) { 1571 info->oem_i2c_present = true; 1572 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1573 } else { 1574 info->oem_i2c_present = false; 1575 } 1576 1577 return BP_RESULT_OK; 1578 } 1579 1580 static enum bp_result bios_parser_get_encoder_cap_info( 1581 struct dc_bios *dcb, 1582 struct graphics_object_id object_id, 1583 struct bp_encoder_cap_info *info) 1584 { 1585 struct bios_parser *bp = BP_FROM_DCB(dcb); 1586 struct atom_display_object_path_v2 *object; 1587 struct atom_encoder_caps_record *record = NULL; 1588 1589 if (!info) 1590 return BP_RESULT_BADINPUT; 1591 1592 object = get_bios_object(bp, object_id); 1593 1594 if (!object) 1595 return BP_RESULT_BADINPUT; 1596 1597 record = get_encoder_cap_record(bp, object); 1598 if (!record) 1599 return BP_RESULT_NORECORD; 1600 1601 info->DP_HBR2_CAP = (record->encodercaps & 1602 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1603 info->DP_HBR2_EN = (record->encodercaps & 1604 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1605 info->DP_HBR3_EN = (record->encodercaps & 1606 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1607 info->HDMI_6GB_EN = (record->encodercaps & 1608 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1609 info->DP_IS_USB_C = (record->encodercaps & 1610 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1611 1612 return BP_RESULT_OK; 1613 } 1614 1615 1616 static struct atom_encoder_caps_record *get_encoder_cap_record( 1617 struct bios_parser *bp, 1618 struct atom_display_object_path_v2 *object) 1619 { 1620 struct atom_common_record_header *header; 1621 uint32_t offset; 1622 1623 if (!object) { 1624 BREAK_TO_DEBUGGER(); /* Invalid object */ 1625 return NULL; 1626 } 1627 1628 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1629 1630 for (;;) { 1631 header = GET_IMAGE(struct atom_common_record_header, offset); 1632 1633 if (!header) 1634 return NULL; 1635 1636 offset += header->record_size; 1637 1638 if (header->record_type == LAST_RECORD_TYPE || 1639 !header->record_size) 1640 break; 1641 1642 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1643 continue; 1644 1645 if (sizeof(struct atom_encoder_caps_record) <= 1646 header->record_size) 1647 return (struct atom_encoder_caps_record *)header; 1648 } 1649 1650 return NULL; 1651 } 1652 1653 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 1654 struct bios_parser *bp, 1655 struct atom_display_object_path_v2 *object) 1656 { 1657 struct atom_common_record_header *header; 1658 uint32_t offset; 1659 1660 if (!object) { 1661 BREAK_TO_DEBUGGER(); /* Invalid object */ 1662 return NULL; 1663 } 1664 1665 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 1666 1667 for (;;) { 1668 header = GET_IMAGE(struct atom_common_record_header, offset); 1669 1670 if (!header) 1671 return NULL; 1672 1673 offset += header->record_size; 1674 1675 if (header->record_type == LAST_RECORD_TYPE || 1676 !header->record_size) 1677 break; 1678 1679 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 1680 continue; 1681 1682 if (sizeof(struct atom_disp_connector_caps_record) <= 1683 header->record_size) 1684 return (struct atom_disp_connector_caps_record *)header; 1685 } 1686 1687 return NULL; 1688 } 1689 1690 static enum bp_result bios_parser_get_disp_connector_caps_info( 1691 struct dc_bios *dcb, 1692 struct graphics_object_id object_id, 1693 struct bp_disp_connector_caps_info *info) 1694 { 1695 struct bios_parser *bp = BP_FROM_DCB(dcb); 1696 struct atom_display_object_path_v2 *object; 1697 struct atom_disp_connector_caps_record *record = NULL; 1698 1699 if (!info) 1700 return BP_RESULT_BADINPUT; 1701 1702 object = get_bios_object(bp, object_id); 1703 1704 if (!object) 1705 return BP_RESULT_BADINPUT; 1706 1707 record = get_disp_connector_caps_record(bp, object); 1708 if (!record) 1709 return BP_RESULT_NORECORD; 1710 1711 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 1712 ? 1 : 0; 1713 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 1714 ? 1 : 0; 1715 1716 return BP_RESULT_OK; 1717 } 1718 1719 static enum bp_result get_vram_info_v23( 1720 struct bios_parser *bp, 1721 struct dc_vram_info *info) 1722 { 1723 struct atom_vram_info_header_v2_3 *info_v23; 1724 enum bp_result result = BP_RESULT_OK; 1725 1726 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1727 DATA_TABLES(vram_info)); 1728 1729 if (info_v23 == NULL) 1730 return BP_RESULT_BADBIOSTABLE; 1731 1732 info->num_chans = info_v23->vram_module[0].channel_num; 1733 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1734 1735 return result; 1736 } 1737 1738 static enum bp_result get_vram_info_v24( 1739 struct bios_parser *bp, 1740 struct dc_vram_info *info) 1741 { 1742 struct atom_vram_info_header_v2_4 *info_v24; 1743 enum bp_result result = BP_RESULT_OK; 1744 1745 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1746 DATA_TABLES(vram_info)); 1747 1748 if (info_v24 == NULL) 1749 return BP_RESULT_BADBIOSTABLE; 1750 1751 info->num_chans = info_v24->vram_module[0].channel_num; 1752 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1753 1754 return result; 1755 } 1756 1757 static enum bp_result get_vram_info_v25( 1758 struct bios_parser *bp, 1759 struct dc_vram_info *info) 1760 { 1761 struct atom_vram_info_header_v2_5 *info_v25; 1762 enum bp_result result = BP_RESULT_OK; 1763 1764 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1765 DATA_TABLES(vram_info)); 1766 1767 if (info_v25 == NULL) 1768 return BP_RESULT_BADBIOSTABLE; 1769 1770 info->num_chans = info_v25->vram_module[0].channel_num; 1771 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1772 1773 return result; 1774 } 1775 1776 /* 1777 * get_integrated_info_v11 1778 * 1779 * @brief 1780 * Get V8 integrated BIOS information 1781 * 1782 * @param 1783 * bios_parser *bp - [in]BIOS parser handler to get master data table 1784 * integrated_info *info - [out] store and output integrated info 1785 * 1786 * @return 1787 * enum bp_result - BP_RESULT_OK if information is available, 1788 * BP_RESULT_BADBIOSTABLE otherwise. 1789 */ 1790 static enum bp_result get_integrated_info_v11( 1791 struct bios_parser *bp, 1792 struct integrated_info *info) 1793 { 1794 struct atom_integrated_system_info_v1_11 *info_v11; 1795 uint32_t i; 1796 1797 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1798 DATA_TABLES(integratedsysteminfo)); 1799 1800 if (info_v11 == NULL) 1801 return BP_RESULT_BADBIOSTABLE; 1802 1803 info->gpu_cap_info = 1804 le32_to_cpu(info_v11->gpucapinfo); 1805 /* 1806 * system_config: Bit[0] = 0 : PCIE power gating disabled 1807 * = 1 : PCIE power gating enabled 1808 * Bit[1] = 0 : DDR-PLL shut down disabled 1809 * = 1 : DDR-PLL shut down enabled 1810 * Bit[2] = 0 : DDR-PLL power down disabled 1811 * = 1 : DDR-PLL power down enabled 1812 */ 1813 info->system_config = le32_to_cpu(info_v11->system_config); 1814 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1815 info->memory_type = info_v11->memorytype; 1816 info->ma_channel_number = info_v11->umachannelnumber; 1817 info->lvds_ss_percentage = 1818 le16_to_cpu(info_v11->lvds_ss_percentage); 1819 info->dp_ss_control = 1820 le16_to_cpu(info_v11->reserved1); 1821 info->lvds_sspread_rate_in_10hz = 1822 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1823 info->hdmi_ss_percentage = 1824 le16_to_cpu(info_v11->hdmi_ss_percentage); 1825 info->hdmi_sspread_rate_in_10hz = 1826 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1827 info->dvi_ss_percentage = 1828 le16_to_cpu(info_v11->dvi_ss_percentage); 1829 info->dvi_sspread_rate_in_10_hz = 1830 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1831 info->lvds_misc = info_v11->lvds_misc; 1832 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1833 info->ext_disp_conn_info.gu_id[i] = 1834 info_v11->extdispconninfo.guid[i]; 1835 } 1836 1837 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1838 info->ext_disp_conn_info.path[i].device_connector_id = 1839 object_id_from_bios_object_id( 1840 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1841 1842 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1843 object_id_from_bios_object_id( 1844 le16_to_cpu( 1845 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1846 1847 info->ext_disp_conn_info.path[i].device_tag = 1848 le16_to_cpu( 1849 info_v11->extdispconninfo.path[i].device_tag); 1850 info->ext_disp_conn_info.path[i].device_acpi_enum = 1851 le16_to_cpu( 1852 info_v11->extdispconninfo.path[i].device_acpi_enum); 1853 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1854 info_v11->extdispconninfo.path[i].auxddclut_index; 1855 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1856 info_v11->extdispconninfo.path[i].hpdlut_index; 1857 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1858 info_v11->extdispconninfo.path[i].channelmapping; 1859 info->ext_disp_conn_info.path[i].caps = 1860 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1861 } 1862 info->ext_disp_conn_info.checksum = 1863 info_v11->extdispconninfo.checksum; 1864 1865 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1866 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1867 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1868 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1869 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1870 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1871 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1872 } 1873 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1874 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1875 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1876 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1877 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1878 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1879 } 1880 1881 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1882 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1883 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1884 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1885 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1886 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1887 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1888 } 1889 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1890 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1891 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1892 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1893 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1894 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1895 } 1896 1897 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1898 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1899 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1900 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1901 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1902 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1903 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1904 } 1905 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1906 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1907 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1908 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1909 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1910 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1911 } 1912 1913 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1914 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1915 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1916 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1917 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1918 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1919 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1920 } 1921 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1922 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1923 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1924 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1925 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1926 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1927 } 1928 1929 1930 /** TODO - review **/ 1931 #if 0 1932 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1933 * 10; 1934 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1935 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1936 1937 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1938 /* Convert [10KHz] into [KHz] */ 1939 info->disp_clk_voltage[i].max_supported_clk = 1940 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1941 ulMaximumSupportedCLK) * 10; 1942 info->disp_clk_voltage[i].voltage_index = 1943 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1944 } 1945 1946 info->boot_up_req_display_vector = 1947 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1948 info->boot_up_nb_voltage = 1949 le16_to_cpu(info_v11->usBootUpNBVoltage); 1950 info->ext_disp_conn_info_offset = 1951 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1952 info->gmc_restore_reset_time = 1953 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1954 info->minimum_n_clk = 1955 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1956 for (i = 1; i < 4; ++i) 1957 info->minimum_n_clk = 1958 info->minimum_n_clk < 1959 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1960 info->minimum_n_clk : le32_to_cpu( 1961 info_v11->ulNbpStateNClkFreq[i]); 1962 1963 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1964 info->ddr_dll_power_up_time = 1965 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1966 info->ddr_pll_power_up_time = 1967 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1968 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1969 info->max_lvds_pclk_freq_in_single_link = 1970 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1971 info->max_lvds_pclk_freq_in_single_link = 1972 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1973 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1974 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1975 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1976 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1977 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1978 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1979 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1980 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1981 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1982 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1983 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1984 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1985 info->lvds_off_to_on_delay_in_4ms = 1986 info_v11->ucLVDSOffToOnDelay_in4Ms; 1987 info->lvds_bit_depth_control_val = 1988 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1989 1990 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1991 /* Convert [10KHz] into [KHz] */ 1992 info->avail_s_clk[i].supported_s_clk = 1993 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1994 * 10; 1995 info->avail_s_clk[i].voltage_index = 1996 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1997 info->avail_s_clk[i].voltage_id = 1998 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1999 } 2000 #endif /* TODO*/ 2001 2002 return BP_RESULT_OK; 2003 } 2004 2005 static enum bp_result get_integrated_info_v2_1( 2006 struct bios_parser *bp, 2007 struct integrated_info *info) 2008 { 2009 struct atom_integrated_system_info_v2_1 *info_v2_1; 2010 uint32_t i; 2011 2012 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2013 DATA_TABLES(integratedsysteminfo)); 2014 2015 if (info_v2_1 == NULL) 2016 return BP_RESULT_BADBIOSTABLE; 2017 2018 info->gpu_cap_info = 2019 le32_to_cpu(info_v2_1->gpucapinfo); 2020 /* 2021 * system_config: Bit[0] = 0 : PCIE power gating disabled 2022 * = 1 : PCIE power gating enabled 2023 * Bit[1] = 0 : DDR-PLL shut down disabled 2024 * = 1 : DDR-PLL shut down enabled 2025 * Bit[2] = 0 : DDR-PLL power down disabled 2026 * = 1 : DDR-PLL power down enabled 2027 */ 2028 info->system_config = le32_to_cpu(info_v2_1->system_config); 2029 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2030 info->memory_type = info_v2_1->memorytype; 2031 info->ma_channel_number = info_v2_1->umachannelnumber; 2032 info->dp_ss_control = 2033 le16_to_cpu(info_v2_1->reserved1); 2034 2035 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2036 info->ext_disp_conn_info.gu_id[i] = 2037 info_v2_1->extdispconninfo.guid[i]; 2038 } 2039 2040 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2041 info->ext_disp_conn_info.path[i].device_connector_id = 2042 object_id_from_bios_object_id( 2043 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2044 2045 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2046 object_id_from_bios_object_id( 2047 le16_to_cpu( 2048 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2049 2050 info->ext_disp_conn_info.path[i].device_tag = 2051 le16_to_cpu( 2052 info_v2_1->extdispconninfo.path[i].device_tag); 2053 info->ext_disp_conn_info.path[i].device_acpi_enum = 2054 le16_to_cpu( 2055 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2056 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2057 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2058 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2059 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2060 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2061 info_v2_1->extdispconninfo.path[i].channelmapping; 2062 info->ext_disp_conn_info.path[i].caps = 2063 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2064 } 2065 2066 info->ext_disp_conn_info.checksum = 2067 info_v2_1->extdispconninfo.checksum; 2068 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2069 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2070 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2071 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2072 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2073 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2074 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2075 } 2076 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2077 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2078 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2079 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2080 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2081 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2082 } 2083 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2084 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2085 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2086 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2087 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2088 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2089 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2090 } 2091 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2092 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2093 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2094 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2095 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2096 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2097 } 2098 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2099 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2100 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2101 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2102 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2103 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2104 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2105 } 2106 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2107 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2108 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2109 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2110 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2111 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2112 } 2113 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2114 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2115 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2116 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2117 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2118 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2119 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2120 } 2121 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2122 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2123 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2124 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2125 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2126 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2127 } 2128 2129 info->edp1_info.edp_backlight_pwm_hz = 2130 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2131 info->edp1_info.edp_ss_percentage = 2132 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2133 info->edp1_info.edp_ss_rate_10hz = 2134 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2135 info->edp1_info.edp_pwr_on_off_delay = 2136 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2137 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2138 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2139 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2140 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2141 info->edp1_info.edp_panel_bpc = 2142 info_v2_1->edp1_info.edp_panel_bpc; 2143 info->edp1_info.edp_bootup_bl_level = 2144 2145 info->edp2_info.edp_backlight_pwm_hz = 2146 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2147 info->edp2_info.edp_ss_percentage = 2148 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2149 info->edp2_info.edp_ss_rate_10hz = 2150 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2151 info->edp2_info.edp_pwr_on_off_delay = 2152 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2153 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2154 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2155 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2156 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2157 info->edp2_info.edp_panel_bpc = 2158 info_v2_1->edp2_info.edp_panel_bpc; 2159 info->edp2_info.edp_bootup_bl_level = 2160 info_v2_1->edp2_info.edp_bootup_bl_level; 2161 2162 return BP_RESULT_OK; 2163 } 2164 2165 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2166 static enum bp_result get_integrated_info_v2_2( 2167 struct bios_parser *bp, 2168 struct integrated_info *info) 2169 { 2170 struct atom_integrated_system_info_v2_2 *info_v2_2; 2171 uint32_t i; 2172 2173 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2174 DATA_TABLES(integratedsysteminfo)); 2175 2176 if (info_v2_2 == NULL) 2177 return BP_RESULT_BADBIOSTABLE; 2178 2179 info->gpu_cap_info = 2180 le32_to_cpu(info_v2_2->gpucapinfo); 2181 /* 2182 * system_config: Bit[0] = 0 : PCIE power gating disabled 2183 * = 1 : PCIE power gating enabled 2184 * Bit[1] = 0 : DDR-PLL shut down disabled 2185 * = 1 : DDR-PLL shut down enabled 2186 * Bit[2] = 0 : DDR-PLL power down disabled 2187 * = 1 : DDR-PLL power down enabled 2188 */ 2189 info->system_config = le32_to_cpu(info_v2_2->system_config); 2190 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2191 info->memory_type = info_v2_2->memorytype; 2192 info->ma_channel_number = info_v2_2->umachannelnumber; 2193 info->dp_ss_control = 2194 le16_to_cpu(info_v2_2->reserved1); 2195 2196 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2197 info->ext_disp_conn_info.gu_id[i] = 2198 info_v2_2->extdispconninfo.guid[i]; 2199 } 2200 2201 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2202 info->ext_disp_conn_info.path[i].device_connector_id = 2203 object_id_from_bios_object_id( 2204 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2205 2206 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2207 object_id_from_bios_object_id( 2208 le16_to_cpu( 2209 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2210 2211 info->ext_disp_conn_info.path[i].device_tag = 2212 le16_to_cpu( 2213 info_v2_2->extdispconninfo.path[i].device_tag); 2214 info->ext_disp_conn_info.path[i].device_acpi_enum = 2215 le16_to_cpu( 2216 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2217 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2218 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2219 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2220 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2221 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2222 info_v2_2->extdispconninfo.path[i].channelmapping; 2223 info->ext_disp_conn_info.path[i].caps = 2224 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2225 } 2226 2227 info->ext_disp_conn_info.checksum = 2228 info_v2_2->extdispconninfo.checksum; 2229 2230 info->edp1_info.edp_backlight_pwm_hz = 2231 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2232 info->edp1_info.edp_ss_percentage = 2233 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2234 info->edp1_info.edp_ss_rate_10hz = 2235 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2236 info->edp1_info.edp_pwr_on_off_delay = 2237 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2238 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2239 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2240 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2241 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2242 info->edp1_info.edp_panel_bpc = 2243 info_v2_2->edp1_info.edp_panel_bpc; 2244 info->edp1_info.edp_bootup_bl_level = 2245 2246 info->edp2_info.edp_backlight_pwm_hz = 2247 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2248 info->edp2_info.edp_ss_percentage = 2249 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2250 info->edp2_info.edp_ss_rate_10hz = 2251 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2252 info->edp2_info.edp_pwr_on_off_delay = 2253 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2254 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2255 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2256 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2257 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2258 info->edp2_info.edp_panel_bpc = 2259 info_v2_2->edp2_info.edp_panel_bpc; 2260 info->edp2_info.edp_bootup_bl_level = 2261 info_v2_2->edp2_info.edp_bootup_bl_level; 2262 2263 return BP_RESULT_OK; 2264 } 2265 #endif 2266 /* 2267 * construct_integrated_info 2268 * 2269 * @brief 2270 * Get integrated BIOS information based on table revision 2271 * 2272 * @param 2273 * bios_parser *bp - [in]BIOS parser handler to get master data table 2274 * integrated_info *info - [out] store and output integrated info 2275 * 2276 * @return 2277 * enum bp_result - BP_RESULT_OK if information is available, 2278 * BP_RESULT_BADBIOSTABLE otherwise. 2279 */ 2280 static enum bp_result construct_integrated_info( 2281 struct bios_parser *bp, 2282 struct integrated_info *info) 2283 { 2284 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2285 2286 struct atom_common_table_header *header; 2287 struct atom_data_revision revision; 2288 uint32_t i; 2289 uint32_t j; 2290 2291 if (info && DATA_TABLES(integratedsysteminfo)) { 2292 header = GET_IMAGE(struct atom_common_table_header, 2293 DATA_TABLES(integratedsysteminfo)); 2294 2295 get_atom_data_table_revision(header, &revision); 2296 2297 switch (revision.major) { 2298 case 1: 2299 switch (revision.minor) { 2300 case 11: 2301 case 12: 2302 result = get_integrated_info_v11(bp, info); 2303 break; 2304 default: 2305 return result; 2306 } 2307 break; 2308 case 2: 2309 switch (revision.minor) { 2310 case 1: 2311 result = get_integrated_info_v2_1(bp, info); 2312 break; 2313 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 2314 case 2: 2315 result = get_integrated_info_v2_2(bp, info); 2316 break; 2317 #endif 2318 default: 2319 return result; 2320 } 2321 break; 2322 default: 2323 return result; 2324 } 2325 } 2326 2327 if (result != BP_RESULT_OK) 2328 return result; 2329 2330 /* Sort voltage table from low to high*/ 2331 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2332 for (j = i; j > 0; --j) { 2333 if (info->disp_clk_voltage[j].max_supported_clk < 2334 info->disp_clk_voltage[j-1].max_supported_clk 2335 ) { 2336 /* swap j and j - 1*/ 2337 swap(info->disp_clk_voltage[j - 1], 2338 info->disp_clk_voltage[j]); 2339 } 2340 } 2341 } 2342 2343 return result; 2344 } 2345 2346 static enum bp_result bios_parser_get_vram_info( 2347 struct dc_bios *dcb, 2348 struct dc_vram_info *info) 2349 { 2350 struct bios_parser *bp = BP_FROM_DCB(dcb); 2351 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2352 struct atom_common_table_header *header; 2353 struct atom_data_revision revision; 2354 2355 if (info && DATA_TABLES(vram_info)) { 2356 header = GET_IMAGE(struct atom_common_table_header, 2357 DATA_TABLES(vram_info)); 2358 2359 get_atom_data_table_revision(header, &revision); 2360 2361 switch (revision.major) { 2362 case 2: 2363 switch (revision.minor) { 2364 case 3: 2365 result = get_vram_info_v23(bp, info); 2366 break; 2367 case 4: 2368 result = get_vram_info_v24(bp, info); 2369 break; 2370 case 5: 2371 result = get_vram_info_v25(bp, info); 2372 break; 2373 default: 2374 break; 2375 } 2376 break; 2377 2378 default: 2379 return result; 2380 } 2381 2382 } 2383 return result; 2384 } 2385 2386 static struct integrated_info *bios_parser_create_integrated_info( 2387 struct dc_bios *dcb) 2388 { 2389 struct bios_parser *bp = BP_FROM_DCB(dcb); 2390 struct integrated_info *info = NULL; 2391 2392 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2393 2394 if (info == NULL) { 2395 ASSERT_CRITICAL(0); 2396 return NULL; 2397 } 2398 2399 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2400 return info; 2401 2402 kfree(info); 2403 2404 return NULL; 2405 } 2406 2407 static enum bp_result update_slot_layout_info( 2408 struct dc_bios *dcb, 2409 unsigned int i, 2410 struct slot_layout_info *slot_layout_info) 2411 { 2412 unsigned int record_offset; 2413 unsigned int j; 2414 struct atom_display_object_path_v2 *object; 2415 struct atom_bracket_layout_record *record; 2416 struct atom_common_record_header *record_header; 2417 enum bp_result result; 2418 struct bios_parser *bp; 2419 struct object_info_table *tbl; 2420 struct display_object_info_table_v1_4 *v1_4; 2421 2422 record = NULL; 2423 record_header = NULL; 2424 result = BP_RESULT_NORECORD; 2425 2426 bp = BP_FROM_DCB(dcb); 2427 tbl = &bp->object_info_tbl; 2428 v1_4 = tbl->v1_4; 2429 2430 object = &v1_4->display_path[i]; 2431 record_offset = (unsigned int) 2432 (object->disp_recordoffset) + 2433 (unsigned int)(bp->object_info_tbl_offset); 2434 2435 for (;;) { 2436 2437 record_header = (struct atom_common_record_header *) 2438 GET_IMAGE(struct atom_common_record_header, 2439 record_offset); 2440 if (record_header == NULL) { 2441 result = BP_RESULT_BADBIOSTABLE; 2442 break; 2443 } 2444 2445 /* the end of the list */ 2446 if (record_header->record_type == 0xff || 2447 record_header->record_size == 0) { 2448 break; 2449 } 2450 2451 if (record_header->record_type == 2452 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2453 sizeof(struct atom_bracket_layout_record) 2454 <= record_header->record_size) { 2455 record = (struct atom_bracket_layout_record *) 2456 (record_header); 2457 result = BP_RESULT_OK; 2458 break; 2459 } 2460 2461 record_offset += record_header->record_size; 2462 } 2463 2464 /* return if the record not found */ 2465 if (result != BP_RESULT_OK) 2466 return result; 2467 2468 /* get slot sizes */ 2469 slot_layout_info->length = record->bracketlen; 2470 slot_layout_info->width = record->bracketwidth; 2471 2472 /* get info for each connector in the slot */ 2473 slot_layout_info->num_of_connectors = record->conn_num; 2474 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2475 slot_layout_info->connectors[j].connector_type = 2476 (enum connector_layout_type) 2477 (record->conn_info[j].connector_type); 2478 switch (record->conn_info[j].connector_type) { 2479 case CONNECTOR_TYPE_DVI_D: 2480 slot_layout_info->connectors[j].connector_type = 2481 CONNECTOR_LAYOUT_TYPE_DVI_D; 2482 slot_layout_info->connectors[j].length = 2483 CONNECTOR_SIZE_DVI; 2484 break; 2485 2486 case CONNECTOR_TYPE_HDMI: 2487 slot_layout_info->connectors[j].connector_type = 2488 CONNECTOR_LAYOUT_TYPE_HDMI; 2489 slot_layout_info->connectors[j].length = 2490 CONNECTOR_SIZE_HDMI; 2491 break; 2492 2493 case CONNECTOR_TYPE_DISPLAY_PORT: 2494 slot_layout_info->connectors[j].connector_type = 2495 CONNECTOR_LAYOUT_TYPE_DP; 2496 slot_layout_info->connectors[j].length = 2497 CONNECTOR_SIZE_DP; 2498 break; 2499 2500 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2501 slot_layout_info->connectors[j].connector_type = 2502 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2503 slot_layout_info->connectors[j].length = 2504 CONNECTOR_SIZE_MINI_DP; 2505 break; 2506 2507 default: 2508 slot_layout_info->connectors[j].connector_type = 2509 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2510 slot_layout_info->connectors[j].length = 2511 CONNECTOR_SIZE_UNKNOWN; 2512 } 2513 2514 slot_layout_info->connectors[j].position = 2515 record->conn_info[j].position; 2516 slot_layout_info->connectors[j].connector_id = 2517 object_id_from_bios_object_id( 2518 record->conn_info[j].connectorobjid); 2519 } 2520 return result; 2521 } 2522 2523 2524 static enum bp_result get_bracket_layout_record( 2525 struct dc_bios *dcb, 2526 unsigned int bracket_layout_id, 2527 struct slot_layout_info *slot_layout_info) 2528 { 2529 unsigned int i; 2530 struct bios_parser *bp = BP_FROM_DCB(dcb); 2531 enum bp_result result; 2532 struct object_info_table *tbl; 2533 struct display_object_info_table_v1_4 *v1_4; 2534 2535 if (slot_layout_info == NULL) { 2536 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2537 return BP_RESULT_BADINPUT; 2538 } 2539 tbl = &bp->object_info_tbl; 2540 v1_4 = tbl->v1_4; 2541 2542 result = BP_RESULT_NORECORD; 2543 for (i = 0; i < v1_4->number_of_path; ++i) { 2544 2545 if (bracket_layout_id == 2546 v1_4->display_path[i].display_objid) { 2547 result = update_slot_layout_info(dcb, i, 2548 slot_layout_info); 2549 break; 2550 } 2551 } 2552 return result; 2553 } 2554 2555 static enum bp_result bios_get_board_layout_info( 2556 struct dc_bios *dcb, 2557 struct board_layout_info *board_layout_info) 2558 { 2559 unsigned int i; 2560 enum bp_result record_result; 2561 2562 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2563 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2564 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2565 0, 0 2566 }; 2567 2568 if (board_layout_info == NULL) { 2569 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2570 return BP_RESULT_BADINPUT; 2571 } 2572 2573 board_layout_info->num_of_slots = 0; 2574 2575 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2576 record_result = get_bracket_layout_record(dcb, 2577 slot_index_to_vbios_id[i], 2578 &board_layout_info->slots[i]); 2579 2580 if (record_result == BP_RESULT_NORECORD && i > 0) 2581 break; /* no more slots present in bios */ 2582 else if (record_result != BP_RESULT_OK) 2583 return record_result; /* fail */ 2584 2585 ++board_layout_info->num_of_slots; 2586 } 2587 2588 /* all data is valid */ 2589 board_layout_info->is_number_of_slots_valid = 1; 2590 board_layout_info->is_slots_size_valid = 1; 2591 board_layout_info->is_connector_offsets_valid = 1; 2592 board_layout_info->is_connector_lengths_valid = 1; 2593 2594 return BP_RESULT_OK; 2595 } 2596 2597 2598 static uint16_t bios_parser_pack_data_tables( 2599 struct dc_bios *dcb, 2600 void *dst) 2601 { 2602 #ifdef PACK_BIOS_DATA 2603 struct bios_parser *bp = BP_FROM_DCB(dcb); 2604 struct atom_rom_header_v2_2 *rom_header = NULL; 2605 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2606 struct atom_common_table_header *data_tbl_header = NULL; 2607 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2608 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2609 struct atom_data_revision tbl_rev = {0}; 2610 uint16_t *rom_header_offset = NULL; 2611 const uint8_t *bios = bp->base.bios; 2612 uint8_t *bios_dst = (uint8_t *)dst; 2613 uint16_t packed_rom_header_offset; 2614 uint16_t packed_masterdatatable_offset; 2615 uint16_t packed_data_tbl_offset; 2616 uint16_t data_tbl_offset; 2617 unsigned int i; 2618 2619 rom_header_offset = 2620 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2621 2622 if (!rom_header_offset) 2623 return 0; 2624 2625 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2626 2627 if (!rom_header) 2628 return 0; 2629 2630 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2631 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2632 return 0; 2633 2634 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2635 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2636 return 0; 2637 2638 packed_rom_header_offset = 2639 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2640 2641 packed_masterdatatable_offset = 2642 packed_rom_header_offset + rom_header->table_header.structuresize; 2643 2644 packed_data_tbl_offset = 2645 packed_masterdatatable_offset + 2646 bp->master_data_tbl->table_header.structuresize; 2647 2648 packed_rom_header = 2649 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2650 2651 packed_master_data_tbl = 2652 (struct atom_master_data_table_v2_1 *)(bios_dst + 2653 packed_masterdatatable_offset); 2654 2655 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2656 2657 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2658 packed_rom_header_offset; 2659 2660 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2661 rom_header->table_header.structuresize); 2662 2663 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2664 2665 memcpy(&packed_master_data_tbl->table_header, 2666 &bp->master_data_tbl->table_header, 2667 sizeof(bp->master_data_tbl->table_header)); 2668 2669 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2670 2671 /* Each data table offset in data table list is 2 bytes, 2672 * we can use that to iterate through listOfdatatables 2673 * without knowing the name of each member. 2674 */ 2675 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2676 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2677 2678 if (data_tbl_offset) { 2679 data_tbl_header = 2680 (struct atom_common_table_header *)(bios + data_tbl_offset); 2681 2682 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2683 data_tbl_header->structuresize); 2684 2685 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2686 packed_data_tbl_offset; 2687 2688 packed_data_tbl_offset += data_tbl_header->structuresize; 2689 } else { 2690 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2691 } 2692 } 2693 return packed_data_tbl_offset; 2694 #endif 2695 // TODO: There is data bytes alignment issue, disable it for now. 2696 return 0; 2697 } 2698 2699 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2700 struct bios_parser *bp, 2701 uint32_t rev_major, 2702 uint32_t rev_minor, 2703 uint16_t *dc_golden_table_ver) 2704 { 2705 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2706 uint32_t dc_golden_offset = 0; 2707 *dc_golden_table_ver = 0; 2708 2709 if (!DATA_TABLES(dce_info)) 2710 return NULL; 2711 2712 /* ver.4.4 or higher */ 2713 switch (rev_major) { 2714 case 4: 2715 switch (rev_minor) { 2716 case 4: 2717 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2718 DATA_TABLES(dce_info)); 2719 if (!disp_cntl_tbl_4_4) 2720 return NULL; 2721 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2722 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2723 break; 2724 } 2725 break; 2726 } 2727 2728 if (!dc_golden_offset) 2729 return NULL; 2730 2731 if (*dc_golden_table_ver != 1) 2732 return NULL; 2733 2734 return GET_IMAGE(struct atom_dc_golden_table_v1, 2735 dc_golden_offset); 2736 } 2737 2738 static enum bp_result bios_get_atom_dc_golden_table( 2739 struct dc_bios *dcb) 2740 { 2741 struct bios_parser *bp = BP_FROM_DCB(dcb); 2742 enum bp_result result = BP_RESULT_OK; 2743 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2744 struct atom_common_table_header *header; 2745 struct atom_data_revision tbl_revision; 2746 uint16_t dc_golden_table_ver = 0; 2747 2748 header = GET_IMAGE(struct atom_common_table_header, 2749 DATA_TABLES(dce_info)); 2750 if (!header) 2751 return BP_RESULT_UNSUPPORTED; 2752 2753 get_atom_data_table_revision(header, &tbl_revision); 2754 2755 atom_dc_golden_table = bios_get_golden_table(bp, 2756 tbl_revision.major, 2757 tbl_revision.minor, 2758 &dc_golden_table_ver); 2759 2760 if (!atom_dc_golden_table) 2761 return BP_RESULT_UNSUPPORTED; 2762 2763 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2764 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2765 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2766 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2767 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2768 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2769 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2770 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2771 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2772 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2773 2774 return result; 2775 } 2776 2777 2778 static const struct dc_vbios_funcs vbios_funcs = { 2779 .get_connectors_number = bios_parser_get_connectors_number, 2780 2781 .get_connector_id = bios_parser_get_connector_id, 2782 2783 .get_src_obj = bios_parser_get_src_obj, 2784 2785 .get_i2c_info = bios_parser_get_i2c_info, 2786 2787 .get_hpd_info = bios_parser_get_hpd_info, 2788 2789 .get_device_tag = bios_parser_get_device_tag, 2790 2791 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2792 2793 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2794 2795 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2796 2797 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2798 2799 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2800 2801 .is_device_id_supported = bios_parser_is_device_id_supported, 2802 2803 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2804 2805 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2806 2807 2808 /* COMMANDS */ 2809 .encoder_control = bios_parser_encoder_control, 2810 2811 .transmitter_control = bios_parser_transmitter_control, 2812 2813 .enable_crtc = bios_parser_enable_crtc, 2814 2815 .set_pixel_clock = bios_parser_set_pixel_clock, 2816 2817 .set_dce_clock = bios_parser_set_dce_clock, 2818 2819 .program_crtc_timing = bios_parser_program_crtc_timing, 2820 2821 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2822 2823 .bios_parser_destroy = firmware_parser_destroy, 2824 2825 .get_board_layout_info = bios_get_board_layout_info, 2826 .pack_data_tables = bios_parser_pack_data_tables, 2827 2828 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2829 2830 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2831 2832 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2833 2834 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 2835 2836 .get_lttpr_caps = bios_parser_get_lttpr_caps, 2837 2838 .get_lttpr_interop = bios_parser_get_lttpr_interop, 2839 }; 2840 2841 static bool bios_parser2_construct( 2842 struct bios_parser *bp, 2843 struct bp_init_data *init, 2844 enum dce_version dce_version) 2845 { 2846 uint16_t *rom_header_offset = NULL; 2847 struct atom_rom_header_v2_2 *rom_header = NULL; 2848 struct display_object_info_table_v1_4 *object_info_tbl; 2849 struct atom_data_revision tbl_rev = {0}; 2850 2851 if (!init) 2852 return false; 2853 2854 if (!init->bios) 2855 return false; 2856 2857 bp->base.funcs = &vbios_funcs; 2858 bp->base.bios = init->bios; 2859 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2860 2861 bp->base.ctx = init->ctx; 2862 2863 bp->base.bios_local_image = NULL; 2864 2865 rom_header_offset = 2866 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2867 2868 if (!rom_header_offset) 2869 return false; 2870 2871 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2872 2873 if (!rom_header) 2874 return false; 2875 2876 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2877 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2878 return false; 2879 2880 bp->master_data_tbl = 2881 GET_IMAGE(struct atom_master_data_table_v2_1, 2882 rom_header->masterdatatable_offset); 2883 2884 if (!bp->master_data_tbl) 2885 return false; 2886 2887 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2888 2889 if (!bp->object_info_tbl_offset) 2890 return false; 2891 2892 object_info_tbl = 2893 GET_IMAGE(struct display_object_info_table_v1_4, 2894 bp->object_info_tbl_offset); 2895 2896 if (!object_info_tbl) 2897 return false; 2898 2899 get_atom_data_table_revision(&object_info_tbl->table_header, 2900 &bp->object_info_tbl.revision); 2901 2902 if (bp->object_info_tbl.revision.major == 1 2903 && bp->object_info_tbl.revision.minor >= 4) { 2904 struct display_object_info_table_v1_4 *tbl_v1_4; 2905 2906 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2907 bp->object_info_tbl_offset); 2908 if (!tbl_v1_4) 2909 return false; 2910 2911 bp->object_info_tbl.v1_4 = tbl_v1_4; 2912 } else 2913 return false; 2914 2915 dal_firmware_parser_init_cmd_tbl(bp); 2916 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2917 2918 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2919 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2920 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2921 2922 return true; 2923 } 2924 2925 struct dc_bios *firmware_parser_create( 2926 struct bp_init_data *init, 2927 enum dce_version dce_version) 2928 { 2929 struct bios_parser *bp = NULL; 2930 2931 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2932 if (!bp) 2933 return NULL; 2934 2935 if (bios_parser2_construct(bp, init, dce_version)) 2936 return &bp->base; 2937 2938 kfree(bp); 2939 return NULL; 2940 } 2941 2942 2943