1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "dc_bios_types.h" 32 #include "include/grph_object_ctrl_defs.h" 33 #include "include/bios_parser_interface.h" 34 #include "include/i2caux_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 #define DC_LOGGER \ 48 bp->base.ctx->logger 49 50 #define LAST_RECORD_TYPE 0xff 51 #define SMU9_SYSPLL0_ID 0 52 53 struct i2c_id_config_access { 54 uint8_t bfI2C_LineMux:4; 55 uint8_t bfHW_EngineID:3; 56 uint8_t bfHW_Capable:1; 57 uint8_t ucAccess; 58 }; 59 60 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 61 struct atom_i2c_record *record, 62 struct graphics_object_i2c_info *info); 63 64 static enum bp_result bios_parser_get_firmware_info( 65 struct dc_bios *dcb, 66 struct dc_firmware_info *info); 67 68 static enum bp_result bios_parser_get_encoder_cap_info( 69 struct dc_bios *dcb, 70 struct graphics_object_id object_id, 71 struct bp_encoder_cap_info *info); 72 73 static enum bp_result get_firmware_info_v3_1( 74 struct bios_parser *bp, 75 struct dc_firmware_info *info); 76 77 static enum bp_result get_firmware_info_v3_2( 78 struct bios_parser *bp, 79 struct dc_firmware_info *info); 80 81 static enum bp_result get_firmware_info_v3_4( 82 struct bios_parser *bp, 83 struct dc_firmware_info *info); 84 85 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 86 struct atom_display_object_path_v2 *object); 87 88 static struct atom_encoder_caps_record *get_encoder_cap_record( 89 struct bios_parser *bp, 90 struct atom_display_object_path_v2 *object); 91 92 #define BIOS_IMAGE_SIZE_OFFSET 2 93 #define BIOS_IMAGE_SIZE_UNIT 512 94 95 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 96 97 static void bios_parser2_destruct(struct bios_parser *bp) 98 { 99 kfree(bp->base.bios_local_image); 100 kfree(bp->base.integrated_info); 101 } 102 103 static void firmware_parser_destroy(struct dc_bios **dcb) 104 { 105 struct bios_parser *bp = BP_FROM_DCB(*dcb); 106 107 if (!bp) { 108 BREAK_TO_DEBUGGER(); 109 return; 110 } 111 112 bios_parser2_destruct(bp); 113 114 kfree(bp); 115 *dcb = NULL; 116 } 117 118 static void get_atom_data_table_revision( 119 struct atom_common_table_header *atom_data_tbl, 120 struct atom_data_revision *tbl_revision) 121 { 122 if (!tbl_revision) 123 return; 124 125 /* initialize the revision to 0 which is invalid revision */ 126 tbl_revision->major = 0; 127 tbl_revision->minor = 0; 128 129 if (!atom_data_tbl) 130 return; 131 132 tbl_revision->major = 133 (uint32_t) atom_data_tbl->format_revision & 0x3f; 134 tbl_revision->minor = 135 (uint32_t) atom_data_tbl->content_revision & 0x3f; 136 } 137 138 /* BIOS oject table displaypath is per connector. 139 * There is extra path not for connector. BIOS fill its encoderid as 0 140 */ 141 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 142 { 143 struct bios_parser *bp = BP_FROM_DCB(dcb); 144 unsigned int count = 0; 145 unsigned int i; 146 147 switch (bp->object_info_tbl.revision.minor) { 148 default: 149 case 4: 150 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 151 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 152 count++; 153 154 break; 155 156 case 5: 157 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 158 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 159 count++; 160 161 break; 162 } 163 return count; 164 } 165 166 static struct graphics_object_id bios_parser_get_connector_id( 167 struct dc_bios *dcb, 168 uint8_t i) 169 { 170 struct bios_parser *bp = BP_FROM_DCB(dcb); 171 struct graphics_object_id object_id = dal_graphics_object_id_init( 172 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 173 struct object_info_table *tbl = &bp->object_info_tbl; 174 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 175 176 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 177 178 switch (bp->object_info_tbl.revision.minor) { 179 default: 180 case 4: 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 break; 191 192 case 5: 193 if (v1_5->number_of_path > i) { 194 /* If display_objid is generic object id, the encoderObjId 195 * should be 0 196 */ 197 if (v1_5->display_path[i].encoderobjid != 0 && 198 v1_5->display_path[i].display_objid != 0) 199 object_id = object_id_from_bios_object_id( 200 v1_5->display_path[i].display_objid); 201 } 202 break; 203 } 204 return object_id; 205 } 206 207 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 208 struct graphics_object_id object_id, uint32_t index, 209 struct graphics_object_id *src_object_id) 210 { 211 struct bios_parser *bp = BP_FROM_DCB(dcb); 212 unsigned int i; 213 enum bp_result bp_result = BP_RESULT_BADINPUT; 214 struct graphics_object_id obj_id = { 0 }; 215 struct object_info_table *tbl = &bp->object_info_tbl; 216 217 if (!src_object_id) 218 return bp_result; 219 220 switch (object_id.type) { 221 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 222 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 223 */ 224 case OBJECT_TYPE_ENCODER: 225 /* TODO: since num of src must be less than 2. 226 * If found in for loop, should break. 227 * DAL2 implementation may be changed too 228 */ 229 switch (bp->object_info_tbl.revision.minor) { 230 default: 231 case 4: 232 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 233 obj_id = object_id_from_bios_object_id( 234 tbl->v1_4->display_path[i].encoderobjid); 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 0x1100); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 247 case 5: 248 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 249 obj_id = object_id_from_bios_object_id( 250 tbl->v1_5->display_path[i].encoderobjid); 251 if (object_id.type == obj_id.type && 252 object_id.id == obj_id.id && 253 object_id.enum_id == obj_id.enum_id) { 254 *src_object_id = 255 object_id_from_bios_object_id( 256 0x1100); 257 /* break; */ 258 } 259 } 260 bp_result = BP_RESULT_OK; 261 break; 262 } 263 break; 264 case OBJECT_TYPE_CONNECTOR: 265 switch (bp->object_info_tbl.revision.minor) { 266 default: 267 case 4: 268 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 269 obj_id = object_id_from_bios_object_id( 270 tbl->v1_4->display_path[i] 271 .display_objid); 272 273 if (object_id.type == obj_id.type && 274 object_id.id == obj_id.id && 275 object_id.enum_id == obj_id.enum_id) { 276 *src_object_id = 277 object_id_from_bios_object_id( 278 tbl->v1_4 279 ->display_path[i] 280 .encoderobjid); 281 /* break; */ 282 } 283 } 284 bp_result = BP_RESULT_OK; 285 break; 286 } 287 bp_result = BP_RESULT_OK; 288 break; 289 case 5: 290 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 291 obj_id = object_id_from_bios_object_id( 292 tbl->v1_5->display_path[i].display_objid); 293 294 if (object_id.type == obj_id.type && 295 object_id.id == obj_id.id && 296 object_id.enum_id == obj_id.enum_id) { 297 *src_object_id = object_id_from_bios_object_id( 298 tbl->v1_5->display_path[i].encoderobjid); 299 /* break; */ 300 } 301 } 302 bp_result = BP_RESULT_OK; 303 break; 304 305 default: 306 bp_result = BP_RESULT_OK; 307 break; 308 } 309 310 return bp_result; 311 } 312 313 /* from graphics_object_id, find display path which includes the object_id */ 314 static struct atom_display_object_path_v2 *get_bios_object( 315 struct bios_parser *bp, 316 struct graphics_object_id id) 317 { 318 unsigned int i; 319 struct graphics_object_id obj_id = {0}; 320 321 switch (id.type) { 322 case OBJECT_TYPE_ENCODER: 323 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 324 obj_id = object_id_from_bios_object_id( 325 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 326 if (id.type == obj_id.type && id.id == obj_id.id 327 && id.enum_id == obj_id.enum_id) 328 return &bp->object_info_tbl.v1_4->display_path[i]; 329 } 330 fallthrough; 331 case OBJECT_TYPE_CONNECTOR: 332 case OBJECT_TYPE_GENERIC: 333 /* Both Generic and Connector Object ID 334 * will be stored on display_objid 335 */ 336 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 337 obj_id = object_id_from_bios_object_id( 338 bp->object_info_tbl.v1_4->display_path[i].display_objid); 339 if (id.type == obj_id.type && id.id == obj_id.id 340 && id.enum_id == obj_id.enum_id) 341 return &bp->object_info_tbl.v1_4->display_path[i]; 342 } 343 fallthrough; 344 default: 345 return NULL; 346 } 347 } 348 349 /* from graphics_object_id, find display path which includes the object_id */ 350 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( 351 struct bios_parser *bp, 352 struct graphics_object_id id) 353 { 354 unsigned int i; 355 struct graphics_object_id obj_id = {0}; 356 357 switch (id.type) { 358 case OBJECT_TYPE_ENCODER: 359 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 360 obj_id = object_id_from_bios_object_id( 361 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 362 if (id.type == obj_id.type && id.id == obj_id.id 363 && id.enum_id == obj_id.enum_id) 364 return &bp->object_info_tbl.v1_5->display_path[i]; 365 } 366 break; 367 368 case OBJECT_TYPE_CONNECTOR: 369 case OBJECT_TYPE_GENERIC: 370 /* Both Generic and Connector Object ID 371 * will be stored on display_objid 372 */ 373 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 374 obj_id = object_id_from_bios_object_id( 375 bp->object_info_tbl.v1_5->display_path[i].display_objid); 376 if (id.type == obj_id.type && id.id == obj_id.id 377 && id.enum_id == obj_id.enum_id) 378 return &bp->object_info_tbl.v1_5->display_path[i]; 379 } 380 break; 381 382 default: 383 return NULL; 384 } 385 386 return NULL; 387 } 388 389 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 390 struct graphics_object_id id, 391 struct graphics_object_i2c_info *info) 392 { 393 uint32_t offset; 394 struct atom_display_object_path_v2 *object; 395 396 struct atom_display_object_path_v3 *object_path_v3; 397 398 struct atom_common_record_header *header; 399 struct atom_i2c_record *record; 400 struct atom_i2c_record dummy_record = {0}; 401 struct bios_parser *bp = BP_FROM_DCB(dcb); 402 403 if (!info) 404 return BP_RESULT_BADINPUT; 405 406 if (id.type == OBJECT_TYPE_GENERIC) { 407 dummy_record.i2c_id = id.id; 408 409 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 410 return BP_RESULT_OK; 411 else 412 return BP_RESULT_NORECORD; 413 } 414 415 switch (bp->object_info_tbl.revision.minor) { 416 case 4: 417 default: 418 object = get_bios_object(bp, id); 419 420 if (!object) 421 return BP_RESULT_BADINPUT; 422 423 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 424 break; 425 case 5: 426 object_path_v3 = get_bios_object_from_path_v3(bp, id); 427 428 if (!object_path_v3) 429 return BP_RESULT_BADINPUT; 430 431 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 432 break; 433 } 434 435 for (;;) { 436 header = GET_IMAGE(struct atom_common_record_header, offset); 437 438 if (!header) 439 return BP_RESULT_BADBIOSTABLE; 440 441 if (header->record_type == LAST_RECORD_TYPE || 442 !header->record_size) 443 break; 444 445 if (header->record_type == ATOM_I2C_RECORD_TYPE 446 && sizeof(struct atom_i2c_record) <= 447 header->record_size) { 448 /* get the I2C info */ 449 record = (struct atom_i2c_record *) header; 450 451 if (get_gpio_i2c_info(bp, record, info) == 452 BP_RESULT_OK) 453 return BP_RESULT_OK; 454 } 455 456 offset += header->record_size; 457 } 458 459 return BP_RESULT_NORECORD; 460 } 461 462 static enum bp_result get_gpio_i2c_info( 463 struct bios_parser *bp, 464 struct atom_i2c_record *record, 465 struct graphics_object_i2c_info *info) 466 { 467 struct atom_gpio_pin_lut_v2_1 *header; 468 uint32_t count = 0; 469 unsigned int table_index = 0; 470 bool find_valid = false; 471 472 if (!info) 473 return BP_RESULT_BADINPUT; 474 475 /* get the GPIO_I2C info */ 476 if (!DATA_TABLES(gpio_pin_lut)) 477 return BP_RESULT_BADBIOSTABLE; 478 479 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 480 DATA_TABLES(gpio_pin_lut)); 481 if (!header) 482 return BP_RESULT_BADBIOSTABLE; 483 484 if (sizeof(struct atom_common_table_header) + 485 sizeof(struct atom_gpio_pin_assignment) > 486 le16_to_cpu(header->table_header.structuresize)) 487 return BP_RESULT_BADBIOSTABLE; 488 489 /* TODO: is version change? */ 490 if (header->table_header.content_revision != 1) 491 return BP_RESULT_UNSUPPORTED; 492 493 /* get data count */ 494 count = (le16_to_cpu(header->table_header.structuresize) 495 - sizeof(struct atom_common_table_header)) 496 / sizeof(struct atom_gpio_pin_assignment); 497 498 for (table_index = 0; table_index < count; table_index++) { 499 if (((record->i2c_id & I2C_HW_CAP) == ( 500 header->gpio_pin[table_index].gpio_id & 501 I2C_HW_CAP)) && 502 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 503 (header->gpio_pin[table_index].gpio_id & 504 I2C_HW_ENGINE_ID_MASK)) && 505 ((record->i2c_id & I2C_HW_LANE_MUX) == 506 (header->gpio_pin[table_index].gpio_id & 507 I2C_HW_LANE_MUX))) { 508 /* still valid */ 509 find_valid = true; 510 break; 511 } 512 } 513 514 /* If we don't find the entry that we are looking for then 515 * we will return BP_Result_BadBiosTable. 516 */ 517 if (find_valid == false) 518 return BP_RESULT_BADBIOSTABLE; 519 520 /* get the GPIO_I2C_INFO */ 521 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 522 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 523 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 524 info->i2c_slave_address = record->i2c_slave_addr; 525 526 /* TODO: check how to get register offset for en, Y, etc. */ 527 info->gpio_info.clk_a_register_index = 528 le16_to_cpu( 529 header->gpio_pin[table_index].data_a_reg_index); 530 info->gpio_info.clk_a_shift = 531 header->gpio_pin[table_index].gpio_bitshift; 532 533 return BP_RESULT_OK; 534 } 535 536 static struct atom_hpd_int_record *get_hpd_record_for_path_v3( 537 struct bios_parser *bp, 538 struct atom_display_object_path_v3 *object) 539 { 540 struct atom_common_record_header *header; 541 uint32_t offset; 542 543 if (!object) { 544 BREAK_TO_DEBUGGER(); /* Invalid object */ 545 return NULL; 546 } 547 548 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 549 550 for (;;) { 551 header = GET_IMAGE(struct atom_common_record_header, offset); 552 553 if (!header) 554 return NULL; 555 556 if (header->record_type == ATOM_RECORD_END_TYPE || 557 !header->record_size) 558 break; 559 560 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 561 && sizeof(struct atom_hpd_int_record) <= 562 header->record_size) 563 return (struct atom_hpd_int_record *) header; 564 565 offset += header->record_size; 566 } 567 568 return NULL; 569 } 570 571 static enum bp_result bios_parser_get_hpd_info( 572 struct dc_bios *dcb, 573 struct graphics_object_id id, 574 struct graphics_object_hpd_info *info) 575 { 576 struct bios_parser *bp = BP_FROM_DCB(dcb); 577 struct atom_display_object_path_v2 *object; 578 struct atom_display_object_path_v3 *object_path_v3; 579 struct atom_hpd_int_record *record = NULL; 580 581 if (!info) 582 return BP_RESULT_BADINPUT; 583 584 switch (bp->object_info_tbl.revision.minor) { 585 case 4: 586 default: 587 object = get_bios_object(bp, id); 588 589 if (!object) 590 return BP_RESULT_BADINPUT; 591 592 record = get_hpd_record(bp, object); 593 594 break; 595 case 5: 596 object_path_v3 = get_bios_object_from_path_v3(bp, id); 597 598 if (!object_path_v3) 599 return BP_RESULT_BADINPUT; 600 601 record = get_hpd_record_for_path_v3(bp, object_path_v3); 602 break; 603 } 604 605 if (record != NULL) { 606 info->hpd_int_gpio_uid = record->pin_id; 607 info->hpd_active = record->plugin_pin_state; 608 return BP_RESULT_OK; 609 } 610 611 return BP_RESULT_NORECORD; 612 } 613 614 static struct atom_hpd_int_record *get_hpd_record( 615 struct bios_parser *bp, 616 struct atom_display_object_path_v2 *object) 617 { 618 struct atom_common_record_header *header; 619 uint32_t offset; 620 621 if (!object) { 622 BREAK_TO_DEBUGGER(); /* Invalid object */ 623 return NULL; 624 } 625 626 offset = le16_to_cpu(object->disp_recordoffset) 627 + bp->object_info_tbl_offset; 628 629 for (;;) { 630 header = GET_IMAGE(struct atom_common_record_header, offset); 631 632 if (!header) 633 return NULL; 634 635 if (header->record_type == LAST_RECORD_TYPE || 636 !header->record_size) 637 break; 638 639 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 640 && sizeof(struct atom_hpd_int_record) <= 641 header->record_size) 642 return (struct atom_hpd_int_record *) header; 643 644 offset += header->record_size; 645 } 646 647 return NULL; 648 } 649 650 /** 651 * bios_parser_get_gpio_pin_info 652 * Get GpioPin information of input gpio id 653 * 654 * @dcb: pointer to the DC BIOS 655 * @gpio_id: GPIO ID 656 * @info: GpioPin information structure 657 * return: Bios parser result code 658 * note: 659 * to get the GPIO PIN INFO, we need: 660 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 661 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 662 * to get the registerA offset/mask 663 */ 664 static enum bp_result bios_parser_get_gpio_pin_info( 665 struct dc_bios *dcb, 666 uint32_t gpio_id, 667 struct gpio_pin_info *info) 668 { 669 struct bios_parser *bp = BP_FROM_DCB(dcb); 670 struct atom_gpio_pin_lut_v2_1 *header; 671 uint32_t count = 0; 672 uint32_t i = 0; 673 674 if (!DATA_TABLES(gpio_pin_lut)) 675 return BP_RESULT_BADBIOSTABLE; 676 677 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 678 DATA_TABLES(gpio_pin_lut)); 679 if (!header) 680 return BP_RESULT_BADBIOSTABLE; 681 682 if (sizeof(struct atom_common_table_header) + 683 sizeof(struct atom_gpio_pin_assignment) 684 > le16_to_cpu(header->table_header.structuresize)) 685 return BP_RESULT_BADBIOSTABLE; 686 687 if (header->table_header.content_revision != 1) 688 return BP_RESULT_UNSUPPORTED; 689 690 /* Temporary hard code gpio pin info */ 691 count = (le16_to_cpu(header->table_header.structuresize) 692 - sizeof(struct atom_common_table_header)) 693 / sizeof(struct atom_gpio_pin_assignment); 694 for (i = 0; i < count; ++i) { 695 if (header->gpio_pin[i].gpio_id != gpio_id) 696 continue; 697 698 info->offset = 699 (uint32_t) le16_to_cpu( 700 header->gpio_pin[i].data_a_reg_index); 701 info->offset_y = info->offset + 2; 702 info->offset_en = info->offset + 1; 703 info->offset_mask = info->offset - 1; 704 705 info->mask = (uint32_t) (1 << 706 header->gpio_pin[i].gpio_bitshift); 707 info->mask_y = info->mask + 2; 708 info->mask_en = info->mask + 1; 709 info->mask_mask = info->mask - 1; 710 711 return BP_RESULT_OK; 712 } 713 714 return BP_RESULT_NORECORD; 715 } 716 717 static struct device_id device_type_from_device_id(uint16_t device_id) 718 { 719 720 struct device_id result_device_id; 721 722 result_device_id.raw_device_tag = device_id; 723 724 switch (device_id) { 725 case ATOM_DISPLAY_LCD1_SUPPORT: 726 result_device_id.device_type = DEVICE_TYPE_LCD; 727 result_device_id.enum_id = 1; 728 break; 729 730 case ATOM_DISPLAY_LCD2_SUPPORT: 731 result_device_id.device_type = DEVICE_TYPE_LCD; 732 result_device_id.enum_id = 2; 733 break; 734 735 case ATOM_DISPLAY_DFP1_SUPPORT: 736 result_device_id.device_type = DEVICE_TYPE_DFP; 737 result_device_id.enum_id = 1; 738 break; 739 740 case ATOM_DISPLAY_DFP2_SUPPORT: 741 result_device_id.device_type = DEVICE_TYPE_DFP; 742 result_device_id.enum_id = 2; 743 break; 744 745 case ATOM_DISPLAY_DFP3_SUPPORT: 746 result_device_id.device_type = DEVICE_TYPE_DFP; 747 result_device_id.enum_id = 3; 748 break; 749 750 case ATOM_DISPLAY_DFP4_SUPPORT: 751 result_device_id.device_type = DEVICE_TYPE_DFP; 752 result_device_id.enum_id = 4; 753 break; 754 755 case ATOM_DISPLAY_DFP5_SUPPORT: 756 result_device_id.device_type = DEVICE_TYPE_DFP; 757 result_device_id.enum_id = 5; 758 break; 759 760 case ATOM_DISPLAY_DFP6_SUPPORT: 761 result_device_id.device_type = DEVICE_TYPE_DFP; 762 result_device_id.enum_id = 6; 763 break; 764 765 default: 766 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 767 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 768 result_device_id.enum_id = 0; 769 } 770 return result_device_id; 771 } 772 773 static enum bp_result bios_parser_get_device_tag( 774 struct dc_bios *dcb, 775 struct graphics_object_id connector_object_id, 776 uint32_t device_tag_index, 777 struct connector_device_tag_info *info) 778 { 779 struct bios_parser *bp = BP_FROM_DCB(dcb); 780 struct atom_display_object_path_v2 *object; 781 782 struct atom_display_object_path_v3 *object_path_v3; 783 784 785 if (!info) 786 return BP_RESULT_BADINPUT; 787 788 switch (bp->object_info_tbl.revision.minor) { 789 case 4: 790 default: 791 /* getBiosObject will return MXM object */ 792 object = get_bios_object(bp, connector_object_id); 793 794 if (!object) { 795 BREAK_TO_DEBUGGER(); /* Invalid object id */ 796 return BP_RESULT_BADINPUT; 797 } 798 799 info->acpi_device = 0; /* BIOS no longer provides this */ 800 info->dev_id = device_type_from_device_id(object->device_tag); 801 break; 802 case 5: 803 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 804 805 if (!object_path_v3) { 806 BREAK_TO_DEBUGGER(); /* Invalid object id */ 807 return BP_RESULT_BADINPUT; 808 } 809 info->acpi_device = 0; /* BIOS no longer provides this */ 810 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 811 break; 812 } 813 814 return BP_RESULT_OK; 815 } 816 817 static enum bp_result get_ss_info_v4_1( 818 struct bios_parser *bp, 819 uint32_t id, 820 uint32_t index, 821 struct spread_spectrum_info *ss_info) 822 { 823 enum bp_result result = BP_RESULT_OK; 824 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 825 struct atom_smu_info_v3_3 *smu_info = NULL; 826 827 if (!ss_info) 828 return BP_RESULT_BADINPUT; 829 830 if (!DATA_TABLES(dce_info)) 831 return BP_RESULT_BADBIOSTABLE; 832 833 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 834 DATA_TABLES(dce_info)); 835 if (!disp_cntl_tbl) 836 return BP_RESULT_BADBIOSTABLE; 837 838 839 ss_info->type.STEP_AND_DELAY_INFO = false; 840 ss_info->spread_percentage_divider = 1000; 841 /* BIOS no longer uses target clock. Always enable for now */ 842 ss_info->target_clock_range = 0xffffffff; 843 844 switch (id) { 845 case AS_SIGNAL_TYPE_DVI: 846 ss_info->spread_spectrum_percentage = 847 disp_cntl_tbl->dvi_ss_percentage; 848 ss_info->spread_spectrum_range = 849 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 850 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 851 ss_info->type.CENTER_MODE = true; 852 853 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 854 break; 855 case AS_SIGNAL_TYPE_HDMI: 856 ss_info->spread_spectrum_percentage = 857 disp_cntl_tbl->hdmi_ss_percentage; 858 ss_info->spread_spectrum_range = 859 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 860 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 861 ss_info->type.CENTER_MODE = true; 862 863 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 864 break; 865 /* TODO LVDS not support anymore? */ 866 case AS_SIGNAL_TYPE_DISPLAY_PORT: 867 ss_info->spread_spectrum_percentage = 868 disp_cntl_tbl->dp_ss_percentage; 869 ss_info->spread_spectrum_range = 870 disp_cntl_tbl->dp_ss_rate_10hz * 10; 871 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 872 ss_info->type.CENTER_MODE = true; 873 874 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 875 break; 876 case AS_SIGNAL_TYPE_GPU_PLL: 877 /* atom_firmware: DAL only get data from dce_info table. 878 * if data within smu_info is needed for DAL, VBIOS should 879 * copy it into dce_info 880 */ 881 result = BP_RESULT_UNSUPPORTED; 882 break; 883 case AS_SIGNAL_TYPE_XGMI: 884 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 885 DATA_TABLES(smu_info)); 886 if (!smu_info) 887 return BP_RESULT_BADBIOSTABLE; 888 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 889 ss_info->spread_spectrum_percentage = 890 smu_info->waflclk_ss_percentage; 891 ss_info->spread_spectrum_range = 892 smu_info->gpuclk_ss_rate_10hz * 10; 893 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 894 ss_info->type.CENTER_MODE = true; 895 896 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 897 break; 898 default: 899 result = BP_RESULT_UNSUPPORTED; 900 } 901 902 return result; 903 } 904 905 static enum bp_result get_ss_info_v4_2( 906 struct bios_parser *bp, 907 uint32_t id, 908 uint32_t index, 909 struct spread_spectrum_info *ss_info) 910 { 911 enum bp_result result = BP_RESULT_OK; 912 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 913 struct atom_smu_info_v3_1 *smu_info = NULL; 914 915 if (!ss_info) 916 return BP_RESULT_BADINPUT; 917 918 if (!DATA_TABLES(dce_info)) 919 return BP_RESULT_BADBIOSTABLE; 920 921 if (!DATA_TABLES(smu_info)) 922 return BP_RESULT_BADBIOSTABLE; 923 924 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 925 DATA_TABLES(dce_info)); 926 if (!disp_cntl_tbl) 927 return BP_RESULT_BADBIOSTABLE; 928 929 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 930 if (!smu_info) 931 return BP_RESULT_BADBIOSTABLE; 932 933 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 934 ss_info->type.STEP_AND_DELAY_INFO = false; 935 ss_info->spread_percentage_divider = 1000; 936 /* BIOS no longer uses target clock. Always enable for now */ 937 ss_info->target_clock_range = 0xffffffff; 938 939 switch (id) { 940 case AS_SIGNAL_TYPE_DVI: 941 ss_info->spread_spectrum_percentage = 942 disp_cntl_tbl->dvi_ss_percentage; 943 ss_info->spread_spectrum_range = 944 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 945 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 946 ss_info->type.CENTER_MODE = true; 947 948 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 949 break; 950 case AS_SIGNAL_TYPE_HDMI: 951 ss_info->spread_spectrum_percentage = 952 disp_cntl_tbl->hdmi_ss_percentage; 953 ss_info->spread_spectrum_range = 954 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 955 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 956 ss_info->type.CENTER_MODE = true; 957 958 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 959 break; 960 /* TODO LVDS not support anymore? */ 961 case AS_SIGNAL_TYPE_DISPLAY_PORT: 962 ss_info->spread_spectrum_percentage = 963 smu_info->gpuclk_ss_percentage; 964 ss_info->spread_spectrum_range = 965 smu_info->gpuclk_ss_rate_10hz * 10; 966 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 967 ss_info->type.CENTER_MODE = true; 968 969 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 970 break; 971 case AS_SIGNAL_TYPE_GPU_PLL: 972 /* atom_firmware: DAL only get data from dce_info table. 973 * if data within smu_info is needed for DAL, VBIOS should 974 * copy it into dce_info 975 */ 976 result = BP_RESULT_UNSUPPORTED; 977 break; 978 default: 979 result = BP_RESULT_UNSUPPORTED; 980 } 981 982 return result; 983 } 984 985 static enum bp_result get_ss_info_v4_5( 986 struct bios_parser *bp, 987 uint32_t id, 988 uint32_t index, 989 struct spread_spectrum_info *ss_info) 990 { 991 enum bp_result result = BP_RESULT_OK; 992 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 993 994 if (!ss_info) 995 return BP_RESULT_BADINPUT; 996 997 if (!DATA_TABLES(dce_info)) 998 return BP_RESULT_BADBIOSTABLE; 999 1000 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1001 DATA_TABLES(dce_info)); 1002 if (!disp_cntl_tbl) 1003 return BP_RESULT_BADBIOSTABLE; 1004 1005 ss_info->type.STEP_AND_DELAY_INFO = false; 1006 ss_info->spread_percentage_divider = 1000; 1007 /* BIOS no longer uses target clock. Always enable for now */ 1008 ss_info->target_clock_range = 0xffffffff; 1009 1010 switch (id) { 1011 case AS_SIGNAL_TYPE_DVI: 1012 ss_info->spread_spectrum_percentage = 1013 disp_cntl_tbl->dvi_ss_percentage; 1014 ss_info->spread_spectrum_range = 1015 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1016 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1017 ss_info->type.CENTER_MODE = true; 1018 1019 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1020 break; 1021 case AS_SIGNAL_TYPE_HDMI: 1022 ss_info->spread_spectrum_percentage = 1023 disp_cntl_tbl->hdmi_ss_percentage; 1024 ss_info->spread_spectrum_range = 1025 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1026 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1027 ss_info->type.CENTER_MODE = true; 1028 1029 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1030 break; 1031 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1032 ss_info->spread_spectrum_percentage = 1033 disp_cntl_tbl->dp_ss_percentage; 1034 ss_info->spread_spectrum_range = 1035 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1036 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1037 ss_info->type.CENTER_MODE = true; 1038 1039 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1040 break; 1041 case AS_SIGNAL_TYPE_GPU_PLL: 1042 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1043 * SMU Display PLL supposed to be without spread. 1044 * Better place for it would be in atom_display_controller_info_v4_5 table. 1045 */ 1046 result = BP_RESULT_UNSUPPORTED; 1047 break; 1048 default: 1049 result = BP_RESULT_UNSUPPORTED; 1050 break; 1051 } 1052 1053 return result; 1054 } 1055 1056 /** 1057 * bios_parser_get_spread_spectrum_info 1058 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1059 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1060 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1061 * ver 3.1, 1062 * there is only one entry for each signal /ss id. However, there is 1063 * no planning of supporting multiple spread Sprectum entry for EverGreen 1064 * @dcb: pointer to the DC BIOS 1065 * @signal: ASSignalType to be converted to info index 1066 * @index: number of entries that match the converted info index 1067 * @ss_info: sprectrum information structure, 1068 * return: Bios parser result code 1069 */ 1070 static enum bp_result bios_parser_get_spread_spectrum_info( 1071 struct dc_bios *dcb, 1072 enum as_signal_type signal, 1073 uint32_t index, 1074 struct spread_spectrum_info *ss_info) 1075 { 1076 struct bios_parser *bp = BP_FROM_DCB(dcb); 1077 enum bp_result result = BP_RESULT_UNSUPPORTED; 1078 struct atom_common_table_header *header; 1079 struct atom_data_revision tbl_revision; 1080 1081 if (!ss_info) /* check for bad input */ 1082 return BP_RESULT_BADINPUT; 1083 1084 if (!DATA_TABLES(dce_info)) 1085 return BP_RESULT_UNSUPPORTED; 1086 1087 header = GET_IMAGE(struct atom_common_table_header, 1088 DATA_TABLES(dce_info)); 1089 get_atom_data_table_revision(header, &tbl_revision); 1090 1091 switch (tbl_revision.major) { 1092 case 4: 1093 switch (tbl_revision.minor) { 1094 case 1: 1095 return get_ss_info_v4_1(bp, signal, index, ss_info); 1096 case 2: 1097 case 3: 1098 case 4: 1099 return get_ss_info_v4_2(bp, signal, index, ss_info); 1100 case 5: 1101 return get_ss_info_v4_5(bp, signal, index, ss_info); 1102 1103 default: 1104 ASSERT(0); 1105 break; 1106 } 1107 break; 1108 default: 1109 break; 1110 } 1111 /* there can not be more then one entry for SS Info table */ 1112 return result; 1113 } 1114 1115 static enum bp_result get_soc_bb_info_v4_4( 1116 struct bios_parser *bp, 1117 struct bp_soc_bb_info *soc_bb_info) 1118 { 1119 enum bp_result result = BP_RESULT_OK; 1120 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1121 1122 if (!soc_bb_info) 1123 return BP_RESULT_BADINPUT; 1124 1125 if (!DATA_TABLES(dce_info)) 1126 return BP_RESULT_BADBIOSTABLE; 1127 1128 if (!DATA_TABLES(smu_info)) 1129 return BP_RESULT_BADBIOSTABLE; 1130 1131 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1132 DATA_TABLES(dce_info)); 1133 if (!disp_cntl_tbl) 1134 return BP_RESULT_BADBIOSTABLE; 1135 1136 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1137 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1138 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1139 1140 return result; 1141 } 1142 1143 static enum bp_result get_soc_bb_info_v4_5( 1144 struct bios_parser *bp, 1145 struct bp_soc_bb_info *soc_bb_info) 1146 { 1147 enum bp_result result = BP_RESULT_OK; 1148 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1149 1150 if (!soc_bb_info) 1151 return BP_RESULT_BADINPUT; 1152 1153 if (!DATA_TABLES(dce_info)) 1154 return BP_RESULT_BADBIOSTABLE; 1155 1156 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1157 DATA_TABLES(dce_info)); 1158 if (!disp_cntl_tbl) 1159 return BP_RESULT_BADBIOSTABLE; 1160 1161 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1162 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1163 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1164 1165 return result; 1166 } 1167 1168 static enum bp_result bios_parser_get_soc_bb_info( 1169 struct dc_bios *dcb, 1170 struct bp_soc_bb_info *soc_bb_info) 1171 { 1172 struct bios_parser *bp = BP_FROM_DCB(dcb); 1173 enum bp_result result = BP_RESULT_UNSUPPORTED; 1174 struct atom_common_table_header *header; 1175 struct atom_data_revision tbl_revision; 1176 1177 if (!soc_bb_info) /* check for bad input */ 1178 return BP_RESULT_BADINPUT; 1179 1180 if (!DATA_TABLES(dce_info)) 1181 return BP_RESULT_UNSUPPORTED; 1182 1183 header = GET_IMAGE(struct atom_common_table_header, 1184 DATA_TABLES(dce_info)); 1185 get_atom_data_table_revision(header, &tbl_revision); 1186 1187 switch (tbl_revision.major) { 1188 case 4: 1189 switch (tbl_revision.minor) { 1190 case 1: 1191 case 2: 1192 case 3: 1193 break; 1194 case 4: 1195 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1196 break; 1197 case 5: 1198 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1199 break; 1200 default: 1201 break; 1202 } 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 return result; 1209 } 1210 1211 static enum bp_result get_disp_caps_v4_1( 1212 struct bios_parser *bp, 1213 uint8_t *dce_caps) 1214 { 1215 enum bp_result result = BP_RESULT_OK; 1216 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1217 1218 if (!dce_caps) 1219 return BP_RESULT_BADINPUT; 1220 1221 if (!DATA_TABLES(dce_info)) 1222 return BP_RESULT_BADBIOSTABLE; 1223 1224 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1225 DATA_TABLES(dce_info)); 1226 1227 if (!disp_cntl_tbl) 1228 return BP_RESULT_BADBIOSTABLE; 1229 1230 *dce_caps = disp_cntl_tbl->display_caps; 1231 1232 return result; 1233 } 1234 1235 static enum bp_result get_disp_caps_v4_2( 1236 struct bios_parser *bp, 1237 uint8_t *dce_caps) 1238 { 1239 enum bp_result result = BP_RESULT_OK; 1240 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1241 1242 if (!dce_caps) 1243 return BP_RESULT_BADINPUT; 1244 1245 if (!DATA_TABLES(dce_info)) 1246 return BP_RESULT_BADBIOSTABLE; 1247 1248 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1249 DATA_TABLES(dce_info)); 1250 1251 if (!disp_cntl_tbl) 1252 return BP_RESULT_BADBIOSTABLE; 1253 1254 *dce_caps = disp_cntl_tbl->display_caps; 1255 1256 return result; 1257 } 1258 1259 static enum bp_result get_disp_caps_v4_3( 1260 struct bios_parser *bp, 1261 uint8_t *dce_caps) 1262 { 1263 enum bp_result result = BP_RESULT_OK; 1264 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1265 1266 if (!dce_caps) 1267 return BP_RESULT_BADINPUT; 1268 1269 if (!DATA_TABLES(dce_info)) 1270 return BP_RESULT_BADBIOSTABLE; 1271 1272 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1273 DATA_TABLES(dce_info)); 1274 1275 if (!disp_cntl_tbl) 1276 return BP_RESULT_BADBIOSTABLE; 1277 1278 *dce_caps = disp_cntl_tbl->display_caps; 1279 1280 return result; 1281 } 1282 1283 static enum bp_result get_disp_caps_v4_4( 1284 struct bios_parser *bp, 1285 uint8_t *dce_caps) 1286 { 1287 enum bp_result result = BP_RESULT_OK; 1288 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1289 1290 if (!dce_caps) 1291 return BP_RESULT_BADINPUT; 1292 1293 if (!DATA_TABLES(dce_info)) 1294 return BP_RESULT_BADBIOSTABLE; 1295 1296 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1297 DATA_TABLES(dce_info)); 1298 1299 if (!disp_cntl_tbl) 1300 return BP_RESULT_BADBIOSTABLE; 1301 1302 *dce_caps = disp_cntl_tbl->display_caps; 1303 1304 return result; 1305 } 1306 1307 static enum bp_result get_disp_caps_v4_5( 1308 struct bios_parser *bp, 1309 uint8_t *dce_caps) 1310 { 1311 enum bp_result result = BP_RESULT_OK; 1312 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1313 1314 if (!dce_caps) 1315 return BP_RESULT_BADINPUT; 1316 1317 if (!DATA_TABLES(dce_info)) 1318 return BP_RESULT_BADBIOSTABLE; 1319 1320 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1321 DATA_TABLES(dce_info)); 1322 1323 if (!disp_cntl_tbl) 1324 return BP_RESULT_BADBIOSTABLE; 1325 1326 *dce_caps = disp_cntl_tbl->display_caps; 1327 1328 return result; 1329 } 1330 1331 static enum bp_result bios_parser_get_lttpr_interop( 1332 struct dc_bios *dcb, 1333 uint8_t *dce_caps) 1334 { 1335 struct bios_parser *bp = BP_FROM_DCB(dcb); 1336 enum bp_result result = BP_RESULT_UNSUPPORTED; 1337 struct atom_common_table_header *header; 1338 struct atom_data_revision tbl_revision; 1339 1340 if (!DATA_TABLES(dce_info)) 1341 return BP_RESULT_UNSUPPORTED; 1342 1343 header = GET_IMAGE(struct atom_common_table_header, 1344 DATA_TABLES(dce_info)); 1345 get_atom_data_table_revision(header, &tbl_revision); 1346 switch (tbl_revision.major) { 1347 case 4: 1348 switch (tbl_revision.minor) { 1349 case 1: 1350 result = get_disp_caps_v4_1(bp, dce_caps); 1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1352 break; 1353 case 2: 1354 result = get_disp_caps_v4_2(bp, dce_caps); 1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1356 break; 1357 case 3: 1358 result = get_disp_caps_v4_3(bp, dce_caps); 1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1360 break; 1361 case 4: 1362 result = get_disp_caps_v4_4(bp, dce_caps); 1363 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1364 break; 1365 case 5: 1366 result = get_disp_caps_v4_5(bp, dce_caps); 1367 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1368 break; 1369 1370 default: 1371 break; 1372 } 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 return result; 1379 } 1380 1381 static enum bp_result bios_parser_get_lttpr_caps( 1382 struct dc_bios *dcb, 1383 uint8_t *dce_caps) 1384 { 1385 struct bios_parser *bp = BP_FROM_DCB(dcb); 1386 enum bp_result result = BP_RESULT_UNSUPPORTED; 1387 struct atom_common_table_header *header; 1388 struct atom_data_revision tbl_revision; 1389 1390 if (!DATA_TABLES(dce_info)) 1391 return BP_RESULT_UNSUPPORTED; 1392 1393 header = GET_IMAGE(struct atom_common_table_header, 1394 DATA_TABLES(dce_info)); 1395 get_atom_data_table_revision(header, &tbl_revision); 1396 switch (tbl_revision.major) { 1397 case 4: 1398 switch (tbl_revision.minor) { 1399 case 1: 1400 result = get_disp_caps_v4_1(bp, dce_caps); 1401 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1402 break; 1403 case 2: 1404 result = get_disp_caps_v4_2(bp, dce_caps); 1405 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1406 break; 1407 case 3: 1408 result = get_disp_caps_v4_3(bp, dce_caps); 1409 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1410 break; 1411 case 4: 1412 result = get_disp_caps_v4_4(bp, dce_caps); 1413 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1414 break; 1415 case 5: 1416 result = get_disp_caps_v4_5(bp, dce_caps); 1417 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1418 break; 1419 default: 1420 break; 1421 } 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return result; 1428 } 1429 1430 static enum bp_result get_embedded_panel_info_v2_1( 1431 struct bios_parser *bp, 1432 struct embedded_panel_info *info) 1433 { 1434 struct lcd_info_v2_1 *lvds; 1435 1436 if (!info) 1437 return BP_RESULT_BADINPUT; 1438 1439 if (!DATA_TABLES(lcd_info)) 1440 return BP_RESULT_UNSUPPORTED; 1441 1442 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1443 1444 if (!lvds) 1445 return BP_RESULT_BADBIOSTABLE; 1446 1447 /* TODO: previous vv1_3, should v2_1 */ 1448 if (!((lvds->table_header.format_revision == 2) 1449 && (lvds->table_header.content_revision >= 1))) 1450 return BP_RESULT_UNSUPPORTED; 1451 1452 memset(info, 0, sizeof(struct embedded_panel_info)); 1453 1454 /* We need to convert from 10KHz units into KHz units */ 1455 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1456 /* usHActive does not include borders, according to VBIOS team */ 1457 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1458 /* usHBlanking_Time includes borders, so we should really be 1459 * subtractingborders duing this translation, but LVDS generally 1460 * doesn't have borders, so we should be okay leaving this as is for 1461 * now. May need to revisit if we ever have LVDS with borders 1462 */ 1463 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1464 /* usVActive does not include borders, according to VBIOS team*/ 1465 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1466 /* usVBlanking_Time includes borders, so we should really be 1467 * subtracting borders duing this translation, but LVDS generally 1468 * doesn't have borders, so we should be okay leaving this as is for 1469 * now. May need to revisit if we ever have LVDS with borders 1470 */ 1471 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1472 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1473 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1474 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1475 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1476 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1477 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1478 1479 /* not provided by VBIOS */ 1480 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1481 1482 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1483 & ATOM_HSYNC_POLARITY); 1484 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1485 & ATOM_VSYNC_POLARITY); 1486 1487 /* not provided by VBIOS */ 1488 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1489 1490 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1491 & ATOM_H_REPLICATIONBY2); 1492 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1493 & ATOM_V_REPLICATIONBY2); 1494 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1495 & ATOM_COMPOSITESYNC); 1496 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1497 1498 /* not provided by VBIOS*/ 1499 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1500 /* not provided by VBIOS*/ 1501 info->ss_id = 0; 1502 1503 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1504 1505 return BP_RESULT_OK; 1506 } 1507 1508 static enum bp_result bios_parser_get_embedded_panel_info( 1509 struct dc_bios *dcb, 1510 struct embedded_panel_info *info) 1511 { 1512 struct bios_parser 1513 *bp = BP_FROM_DCB(dcb); 1514 struct atom_common_table_header *header; 1515 struct atom_data_revision tbl_revision; 1516 1517 if (!DATA_TABLES(lcd_info)) 1518 return BP_RESULT_FAILURE; 1519 1520 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1521 1522 if (!header) 1523 return BP_RESULT_BADBIOSTABLE; 1524 1525 get_atom_data_table_revision(header, &tbl_revision); 1526 1527 switch (tbl_revision.major) { 1528 case 2: 1529 switch (tbl_revision.minor) { 1530 case 1: 1531 return get_embedded_panel_info_v2_1(bp, info); 1532 default: 1533 break; 1534 } 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 return BP_RESULT_FAILURE; 1541 } 1542 1543 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1544 { 1545 enum dal_device_type device_type = device_id.device_type; 1546 uint32_t enum_id = device_id.enum_id; 1547 1548 switch (device_type) { 1549 case DEVICE_TYPE_LCD: 1550 switch (enum_id) { 1551 case 1: 1552 return ATOM_DISPLAY_LCD1_SUPPORT; 1553 default: 1554 break; 1555 } 1556 break; 1557 case DEVICE_TYPE_DFP: 1558 switch (enum_id) { 1559 case 1: 1560 return ATOM_DISPLAY_DFP1_SUPPORT; 1561 case 2: 1562 return ATOM_DISPLAY_DFP2_SUPPORT; 1563 case 3: 1564 return ATOM_DISPLAY_DFP3_SUPPORT; 1565 case 4: 1566 return ATOM_DISPLAY_DFP4_SUPPORT; 1567 case 5: 1568 return ATOM_DISPLAY_DFP5_SUPPORT; 1569 case 6: 1570 return ATOM_DISPLAY_DFP6_SUPPORT; 1571 default: 1572 break; 1573 } 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 /* Unidentified device ID, return empty support mask. */ 1580 return 0; 1581 } 1582 1583 static bool bios_parser_is_device_id_supported( 1584 struct dc_bios *dcb, 1585 struct device_id id) 1586 { 1587 struct bios_parser *bp = BP_FROM_DCB(dcb); 1588 1589 uint32_t mask = get_support_mask_for_device_id(id); 1590 1591 switch (bp->object_info_tbl.revision.minor) { 1592 case 4: 1593 default: 1594 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1595 break; 1596 case 5: 1597 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1598 break; 1599 } 1600 1601 return false; 1602 } 1603 1604 static uint32_t bios_parser_get_ss_entry_number( 1605 struct dc_bios *dcb, 1606 enum as_signal_type signal) 1607 { 1608 /* TODO: DAL2 atomfirmware implementation does not need this. 1609 * why DAL3 need this? 1610 */ 1611 return 1; 1612 } 1613 1614 static enum bp_result bios_parser_transmitter_control( 1615 struct dc_bios *dcb, 1616 struct bp_transmitter_control *cntl) 1617 { 1618 struct bios_parser *bp = BP_FROM_DCB(dcb); 1619 1620 if (!bp->cmd_tbl.transmitter_control) 1621 return BP_RESULT_FAILURE; 1622 1623 return bp->cmd_tbl.transmitter_control(bp, cntl); 1624 } 1625 1626 static enum bp_result bios_parser_encoder_control( 1627 struct dc_bios *dcb, 1628 struct bp_encoder_control *cntl) 1629 { 1630 struct bios_parser *bp = BP_FROM_DCB(dcb); 1631 1632 if (!bp->cmd_tbl.dig_encoder_control) 1633 return BP_RESULT_FAILURE; 1634 1635 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1636 } 1637 1638 static enum bp_result bios_parser_set_pixel_clock( 1639 struct dc_bios *dcb, 1640 struct bp_pixel_clock_parameters *bp_params) 1641 { 1642 struct bios_parser *bp = BP_FROM_DCB(dcb); 1643 1644 if (!bp->cmd_tbl.set_pixel_clock) 1645 return BP_RESULT_FAILURE; 1646 1647 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1648 } 1649 1650 static enum bp_result bios_parser_set_dce_clock( 1651 struct dc_bios *dcb, 1652 struct bp_set_dce_clock_parameters *bp_params) 1653 { 1654 struct bios_parser *bp = BP_FROM_DCB(dcb); 1655 1656 if (!bp->cmd_tbl.set_dce_clock) 1657 return BP_RESULT_FAILURE; 1658 1659 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1660 } 1661 1662 static enum bp_result bios_parser_program_crtc_timing( 1663 struct dc_bios *dcb, 1664 struct bp_hw_crtc_timing_parameters *bp_params) 1665 { 1666 struct bios_parser *bp = BP_FROM_DCB(dcb); 1667 1668 if (!bp->cmd_tbl.set_crtc_timing) 1669 return BP_RESULT_FAILURE; 1670 1671 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1672 } 1673 1674 static enum bp_result bios_parser_enable_crtc( 1675 struct dc_bios *dcb, 1676 enum controller_id id, 1677 bool enable) 1678 { 1679 struct bios_parser *bp = BP_FROM_DCB(dcb); 1680 1681 if (!bp->cmd_tbl.enable_crtc) 1682 return BP_RESULT_FAILURE; 1683 1684 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1685 } 1686 1687 static enum bp_result bios_parser_enable_disp_power_gating( 1688 struct dc_bios *dcb, 1689 enum controller_id controller_id, 1690 enum bp_pipe_control_action action) 1691 { 1692 struct bios_parser *bp = BP_FROM_DCB(dcb); 1693 1694 if (!bp->cmd_tbl.enable_disp_power_gating) 1695 return BP_RESULT_FAILURE; 1696 1697 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1698 action); 1699 } 1700 1701 static enum bp_result bios_parser_enable_lvtma_control( 1702 struct dc_bios *dcb, 1703 uint8_t uc_pwr_on, 1704 uint8_t panel_instance) 1705 { 1706 struct bios_parser *bp = BP_FROM_DCB(dcb); 1707 1708 if (!bp->cmd_tbl.enable_lvtma_control) 1709 return BP_RESULT_FAILURE; 1710 1711 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1712 } 1713 1714 static bool bios_parser_is_accelerated_mode( 1715 struct dc_bios *dcb) 1716 { 1717 return bios_is_accelerated_mode(dcb); 1718 } 1719 1720 /** 1721 * bios_parser_set_scratch_critical_state - update critical state bit 1722 * in VBIOS scratch register 1723 * 1724 * @dcb: pointer to the DC BIO 1725 * @state: set or reset state 1726 */ 1727 static void bios_parser_set_scratch_critical_state( 1728 struct dc_bios *dcb, 1729 bool state) 1730 { 1731 bios_set_scratch_critical_state(dcb, state); 1732 } 1733 1734 struct atom_dig_transmitter_info_header_v5_3 { 1735 struct atom_common_table_header table_header; 1736 uint16_t dpphy_hdmi_settings_offset; 1737 uint16_t dpphy_dvi_settings_offset; 1738 uint16_t dpphy_dp_setting_table_offset; 1739 uint16_t uniphy_xbar_settings_v2_table_offset; 1740 uint16_t dpphy_internal_reg_overide_offset; 1741 }; 1742 1743 static enum bp_result bios_parser_get_firmware_info( 1744 struct dc_bios *dcb, 1745 struct dc_firmware_info *info) 1746 { 1747 struct bios_parser *bp = BP_FROM_DCB(dcb); 1748 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1749 struct atom_common_table_header *header; 1750 1751 struct atom_data_revision revision; 1752 1753 if (info && DATA_TABLES(firmwareinfo)) { 1754 header = GET_IMAGE(struct atom_common_table_header, 1755 DATA_TABLES(firmwareinfo)); 1756 get_atom_data_table_revision(header, &revision); 1757 switch (revision.major) { 1758 case 3: 1759 switch (revision.minor) { 1760 case 1: 1761 result = get_firmware_info_v3_1(bp, info); 1762 break; 1763 case 2: 1764 case 3: 1765 result = get_firmware_info_v3_2(bp, info); 1766 break; 1767 case 4: 1768 result = get_firmware_info_v3_4(bp, info); 1769 break; 1770 default: 1771 break; 1772 } 1773 break; 1774 default: 1775 break; 1776 } 1777 } 1778 1779 return result; 1780 } 1781 1782 static enum bp_result get_firmware_info_v3_1( 1783 struct bios_parser *bp, 1784 struct dc_firmware_info *info) 1785 { 1786 struct atom_firmware_info_v3_1 *firmware_info; 1787 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1788 1789 if (!info) 1790 return BP_RESULT_BADINPUT; 1791 1792 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1793 DATA_TABLES(firmwareinfo)); 1794 1795 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1796 DATA_TABLES(dce_info)); 1797 1798 if (!firmware_info || !dce_info) 1799 return BP_RESULT_BADBIOSTABLE; 1800 1801 memset(info, 0, sizeof(*info)); 1802 1803 /* Pixel clock pll information. */ 1804 /* We need to convert from 10KHz units into KHz units */ 1805 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1806 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1807 1808 /* 27MHz for Vega10: */ 1809 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1810 1811 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1812 if (info->pll_info.crystal_frequency == 0) 1813 info->pll_info.crystal_frequency = 27000; 1814 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1815 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1816 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1817 1818 /* Get GPU PLL VCO Clock */ 1819 1820 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1821 /* VBIOS gives in 10KHz */ 1822 info->smu_gpu_pll_output_freq = 1823 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1824 } 1825 1826 info->oem_i2c_present = false; 1827 1828 return BP_RESULT_OK; 1829 } 1830 1831 static enum bp_result get_firmware_info_v3_2( 1832 struct bios_parser *bp, 1833 struct dc_firmware_info *info) 1834 { 1835 struct atom_firmware_info_v3_2 *firmware_info; 1836 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1837 struct atom_common_table_header *header; 1838 struct atom_data_revision revision; 1839 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1840 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1841 1842 if (!info) 1843 return BP_RESULT_BADINPUT; 1844 1845 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1846 DATA_TABLES(firmwareinfo)); 1847 1848 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1849 DATA_TABLES(dce_info)); 1850 1851 if (!firmware_info || !dce_info) 1852 return BP_RESULT_BADBIOSTABLE; 1853 1854 memset(info, 0, sizeof(*info)); 1855 1856 header = GET_IMAGE(struct atom_common_table_header, 1857 DATA_TABLES(smu_info)); 1858 get_atom_data_table_revision(header, &revision); 1859 1860 if (revision.minor == 2) { 1861 /* Vega12 */ 1862 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1863 DATA_TABLES(smu_info)); 1864 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage); 1865 if (!smu_info_v3_2) 1866 return BP_RESULT_BADBIOSTABLE; 1867 1868 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1869 } else if (revision.minor == 3) { 1870 /* Vega20 */ 1871 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1872 DATA_TABLES(smu_info)); 1873 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage); 1874 if (!smu_info_v3_3) 1875 return BP_RESULT_BADBIOSTABLE; 1876 1877 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1878 } 1879 1880 // We need to convert from 10KHz units into KHz units. 1881 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1882 1883 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1884 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1885 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1886 if (info->pll_info.crystal_frequency == 0) { 1887 if (revision.minor == 2) 1888 info->pll_info.crystal_frequency = 27000; 1889 else if (revision.minor == 3) 1890 info->pll_info.crystal_frequency = 100000; 1891 } 1892 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1893 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1894 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1895 1896 /* Get GPU PLL VCO Clock */ 1897 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1898 if (revision.minor == 2) 1899 info->smu_gpu_pll_output_freq = 1900 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1901 else if (revision.minor == 3) 1902 info->smu_gpu_pll_output_freq = 1903 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1904 } 1905 1906 if (firmware_info->board_i2c_feature_id == 0x2) { 1907 info->oem_i2c_present = true; 1908 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1909 } else { 1910 info->oem_i2c_present = false; 1911 } 1912 1913 return BP_RESULT_OK; 1914 } 1915 1916 static enum bp_result get_firmware_info_v3_4( 1917 struct bios_parser *bp, 1918 struct dc_firmware_info *info) 1919 { 1920 struct atom_firmware_info_v3_4 *firmware_info; 1921 struct atom_common_table_header *header; 1922 struct atom_data_revision revision; 1923 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1924 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1925 1926 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1927 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1928 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1929 1930 if (!info) 1931 return BP_RESULT_BADINPUT; 1932 1933 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1934 DATA_TABLES(firmwareinfo)); 1935 1936 if (!firmware_info) 1937 return BP_RESULT_BADBIOSTABLE; 1938 1939 memset(info, 0, sizeof(*info)); 1940 1941 header = GET_IMAGE(struct atom_common_table_header, 1942 DATA_TABLES(dce_info)); 1943 1944 get_atom_data_table_revision(header, &revision); 1945 1946 switch (revision.major) { 1947 case 4: 1948 switch (revision.minor) { 1949 case 5: 1950 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1951 DATA_TABLES(dce_info)); 1952 1953 if (!dce_info_v4_5) 1954 return BP_RESULT_BADBIOSTABLE; 1955 1956 /* 100MHz expected */ 1957 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1958 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1959 /* 50MHz expected */ 1960 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1961 1962 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1963 break; 1964 1965 case 4: 1966 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1967 DATA_TABLES(dce_info)); 1968 1969 if (!dce_info_v4_4) 1970 return BP_RESULT_BADBIOSTABLE; 1971 1972 /* 100MHz expected */ 1973 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1974 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1975 /* 50MHz expected */ 1976 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1977 1978 /* Get SMU Display PLL VCO Frequency in KHz*/ 1979 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1980 break; 1981 1982 default: 1983 /* should not come here, keep as backup, as was before */ 1984 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1985 DATA_TABLES(dce_info)); 1986 1987 if (!dce_info_v4_1) 1988 return BP_RESULT_BADBIOSTABLE; 1989 1990 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 1991 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 1992 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 1993 break; 1994 } 1995 break; 1996 1997 default: 1998 ASSERT(0); 1999 break; 2000 } 2001 2002 header = GET_IMAGE(struct atom_common_table_header, 2003 DATA_TABLES(smu_info)); 2004 get_atom_data_table_revision(header, &revision); 2005 2006 switch (revision.major) { 2007 case 3: 2008 switch (revision.minor) { 2009 case 5: 2010 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2011 DATA_TABLES(smu_info)); 2012 2013 if (!smu_info_v3_5) 2014 return BP_RESULT_BADBIOSTABLE; 2015 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage); 2016 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2017 break; 2018 2019 default: 2020 break; 2021 } 2022 break; 2023 2024 case 4: 2025 switch (revision.minor) { 2026 case 0: 2027 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2028 DATA_TABLES(smu_info)); 2029 2030 if (!smu_info_v4_0) 2031 return BP_RESULT_BADBIOSTABLE; 2032 2033 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2034 break; 2035 2036 default: 2037 break; 2038 } 2039 break; 2040 2041 default: 2042 break; 2043 } 2044 2045 // We need to convert from 10KHz units into KHz units. 2046 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2047 2048 if (firmware_info->board_i2c_feature_id == 0x2) { 2049 info->oem_i2c_present = true; 2050 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2051 } else { 2052 info->oem_i2c_present = false; 2053 } 2054 2055 return BP_RESULT_OK; 2056 } 2057 2058 static enum bp_result bios_parser_get_encoder_cap_info( 2059 struct dc_bios *dcb, 2060 struct graphics_object_id object_id, 2061 struct bp_encoder_cap_info *info) 2062 { 2063 struct bios_parser *bp = BP_FROM_DCB(dcb); 2064 struct atom_display_object_path_v2 *object; 2065 struct atom_encoder_caps_record *record = NULL; 2066 2067 if (!info) 2068 return BP_RESULT_BADINPUT; 2069 2070 #if defined(CONFIG_DRM_AMD_DC_DCN) 2071 /* encoder cap record not available in v1_5 */ 2072 if (bp->object_info_tbl.revision.minor == 5) 2073 return BP_RESULT_NORECORD; 2074 #endif 2075 2076 object = get_bios_object(bp, object_id); 2077 2078 if (!object) 2079 return BP_RESULT_BADINPUT; 2080 2081 record = get_encoder_cap_record(bp, object); 2082 if (!record) 2083 return BP_RESULT_NORECORD; 2084 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id); 2085 2086 info->DP_HBR2_CAP = (record->encodercaps & 2087 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2088 info->DP_HBR2_EN = (record->encodercaps & 2089 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2090 info->DP_HBR3_EN = (record->encodercaps & 2091 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2092 info->HDMI_6GB_EN = (record->encodercaps & 2093 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2094 info->IS_DP2_CAPABLE = (record->encodercaps & 2095 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2096 info->DP_UHBR10_EN = (record->encodercaps & 2097 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2098 info->DP_UHBR13_5_EN = (record->encodercaps & 2099 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2100 info->DP_UHBR20_EN = (record->encodercaps & 2101 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2102 info->DP_IS_USB_C = (record->encodercaps & 2103 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2104 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C); 2105 2106 return BP_RESULT_OK; 2107 } 2108 2109 2110 static struct atom_encoder_caps_record *get_encoder_cap_record( 2111 struct bios_parser *bp, 2112 struct atom_display_object_path_v2 *object) 2113 { 2114 struct atom_common_record_header *header; 2115 uint32_t offset; 2116 2117 if (!object) { 2118 BREAK_TO_DEBUGGER(); /* Invalid object */ 2119 return NULL; 2120 } 2121 2122 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2123 2124 for (;;) { 2125 header = GET_IMAGE(struct atom_common_record_header, offset); 2126 2127 if (!header) 2128 return NULL; 2129 2130 offset += header->record_size; 2131 2132 if (header->record_type == LAST_RECORD_TYPE || 2133 !header->record_size) 2134 break; 2135 2136 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2137 continue; 2138 2139 if (sizeof(struct atom_encoder_caps_record) <= 2140 header->record_size) 2141 return (struct atom_encoder_caps_record *)header; 2142 } 2143 2144 return NULL; 2145 } 2146 2147 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2148 struct bios_parser *bp, 2149 struct atom_display_object_path_v2 *object) 2150 { 2151 struct atom_common_record_header *header; 2152 uint32_t offset; 2153 2154 if (!object) { 2155 BREAK_TO_DEBUGGER(); /* Invalid object */ 2156 return NULL; 2157 } 2158 2159 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2160 2161 for (;;) { 2162 header = GET_IMAGE(struct atom_common_record_header, offset); 2163 2164 if (!header) 2165 return NULL; 2166 2167 offset += header->record_size; 2168 2169 if (header->record_type == LAST_RECORD_TYPE || 2170 !header->record_size) 2171 break; 2172 2173 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2174 continue; 2175 2176 if (sizeof(struct atom_disp_connector_caps_record) <= 2177 header->record_size) 2178 return (struct atom_disp_connector_caps_record *)header; 2179 } 2180 2181 return NULL; 2182 } 2183 2184 static struct atom_connector_caps_record *get_connector_caps_record( 2185 struct bios_parser *bp, 2186 struct atom_display_object_path_v3 *object) 2187 { 2188 struct atom_common_record_header *header; 2189 uint32_t offset; 2190 2191 if (!object) { 2192 BREAK_TO_DEBUGGER(); /* Invalid object */ 2193 return NULL; 2194 } 2195 2196 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2197 2198 for (;;) { 2199 header = GET_IMAGE(struct atom_common_record_header, offset); 2200 2201 if (!header) 2202 return NULL; 2203 2204 offset += header->record_size; 2205 2206 if (header->record_type == ATOM_RECORD_END_TYPE || 2207 !header->record_size) 2208 break; 2209 2210 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2211 continue; 2212 2213 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2214 return (struct atom_connector_caps_record *)header; 2215 } 2216 2217 return NULL; 2218 } 2219 2220 static enum bp_result bios_parser_get_disp_connector_caps_info( 2221 struct dc_bios *dcb, 2222 struct graphics_object_id object_id, 2223 struct bp_disp_connector_caps_info *info) 2224 { 2225 struct bios_parser *bp = BP_FROM_DCB(dcb); 2226 struct atom_display_object_path_v2 *object; 2227 2228 struct atom_display_object_path_v3 *object_path_v3; 2229 struct atom_connector_caps_record *record_path_v3; 2230 2231 struct atom_disp_connector_caps_record *record = NULL; 2232 2233 if (!info) 2234 return BP_RESULT_BADINPUT; 2235 2236 switch (bp->object_info_tbl.revision.minor) { 2237 case 4: 2238 default: 2239 object = get_bios_object(bp, object_id); 2240 2241 if (!object) 2242 return BP_RESULT_BADINPUT; 2243 2244 record = get_disp_connector_caps_record(bp, object); 2245 if (!record) 2246 return BP_RESULT_NORECORD; 2247 2248 info->INTERNAL_DISPLAY = 2249 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2250 info->INTERNAL_DISPLAY_BL = 2251 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2252 break; 2253 case 5: 2254 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2255 2256 if (!object_path_v3) 2257 return BP_RESULT_BADINPUT; 2258 2259 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2260 if (!record_path_v3) 2261 return BP_RESULT_NORECORD; 2262 2263 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2264 ? 1 : 0; 2265 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2266 ? 1 : 0; 2267 break; 2268 } 2269 2270 return BP_RESULT_OK; 2271 } 2272 2273 static struct atom_connector_speed_record *get_connector_speed_cap_record( 2274 struct bios_parser *bp, 2275 struct atom_display_object_path_v3 *object) 2276 { 2277 struct atom_common_record_header *header; 2278 uint32_t offset; 2279 2280 if (!object) { 2281 BREAK_TO_DEBUGGER(); /* Invalid object */ 2282 return NULL; 2283 } 2284 2285 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2286 2287 for (;;) { 2288 header = GET_IMAGE(struct atom_common_record_header, offset); 2289 2290 if (!header) 2291 return NULL; 2292 2293 offset += header->record_size; 2294 2295 if (header->record_type == ATOM_RECORD_END_TYPE || 2296 !header->record_size) 2297 break; 2298 2299 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2300 continue; 2301 2302 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2303 return (struct atom_connector_speed_record *)header; 2304 } 2305 2306 return NULL; 2307 } 2308 2309 static enum bp_result bios_parser_get_connector_speed_cap_info( 2310 struct dc_bios *dcb, 2311 struct graphics_object_id object_id, 2312 struct bp_connector_speed_cap_info *info) 2313 { 2314 struct bios_parser *bp = BP_FROM_DCB(dcb); 2315 struct atom_display_object_path_v3 *object_path_v3; 2316 //struct atom_connector_speed_record *record = NULL; 2317 struct atom_connector_speed_record *record; 2318 2319 if (!info) 2320 return BP_RESULT_BADINPUT; 2321 2322 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2323 2324 if (!object_path_v3) 2325 return BP_RESULT_BADINPUT; 2326 2327 record = get_connector_speed_cap_record(bp, object_path_v3); 2328 if (!record) 2329 return BP_RESULT_NORECORD; 2330 2331 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2332 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2333 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2334 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2335 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2336 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2337 return BP_RESULT_OK; 2338 } 2339 2340 static enum bp_result get_vram_info_v23( 2341 struct bios_parser *bp, 2342 struct dc_vram_info *info) 2343 { 2344 struct atom_vram_info_header_v2_3 *info_v23; 2345 static enum bp_result result = BP_RESULT_OK; 2346 2347 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2348 DATA_TABLES(vram_info)); 2349 2350 if (info_v23 == NULL) 2351 return BP_RESULT_BADBIOSTABLE; 2352 2353 info->num_chans = info_v23->vram_module[0].channel_num; 2354 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2355 2356 return result; 2357 } 2358 2359 static enum bp_result get_vram_info_v24( 2360 struct bios_parser *bp, 2361 struct dc_vram_info *info) 2362 { 2363 struct atom_vram_info_header_v2_4 *info_v24; 2364 static enum bp_result result = BP_RESULT_OK; 2365 2366 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2367 DATA_TABLES(vram_info)); 2368 2369 if (info_v24 == NULL) 2370 return BP_RESULT_BADBIOSTABLE; 2371 2372 info->num_chans = info_v24->vram_module[0].channel_num; 2373 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2374 2375 return result; 2376 } 2377 2378 static enum bp_result get_vram_info_v25( 2379 struct bios_parser *bp, 2380 struct dc_vram_info *info) 2381 { 2382 struct atom_vram_info_header_v2_5 *info_v25; 2383 static enum bp_result result = BP_RESULT_OK; 2384 2385 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2386 DATA_TABLES(vram_info)); 2387 2388 if (info_v25 == NULL) 2389 return BP_RESULT_BADBIOSTABLE; 2390 2391 info->num_chans = info_v25->vram_module[0].channel_num; 2392 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2393 2394 return result; 2395 } 2396 2397 /* 2398 * get_integrated_info_v11 2399 * 2400 * @brief 2401 * Get V8 integrated BIOS information 2402 * 2403 * @param 2404 * bios_parser *bp - [in]BIOS parser handler to get master data table 2405 * integrated_info *info - [out] store and output integrated info 2406 * 2407 * @return 2408 * static enum bp_result - BP_RESULT_OK if information is available, 2409 * BP_RESULT_BADBIOSTABLE otherwise. 2410 */ 2411 static enum bp_result get_integrated_info_v11( 2412 struct bios_parser *bp, 2413 struct integrated_info *info) 2414 { 2415 struct atom_integrated_system_info_v1_11 *info_v11; 2416 uint32_t i; 2417 2418 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2419 DATA_TABLES(integratedsysteminfo)); 2420 2421 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage); 2422 if (info_v11 == NULL) 2423 return BP_RESULT_BADBIOSTABLE; 2424 2425 info->gpu_cap_info = 2426 le32_to_cpu(info_v11->gpucapinfo); 2427 /* 2428 * system_config: Bit[0] = 0 : PCIE power gating disabled 2429 * = 1 : PCIE power gating enabled 2430 * Bit[1] = 0 : DDR-PLL shut down disabled 2431 * = 1 : DDR-PLL shut down enabled 2432 * Bit[2] = 0 : DDR-PLL power down disabled 2433 * = 1 : DDR-PLL power down enabled 2434 */ 2435 info->system_config = le32_to_cpu(info_v11->system_config); 2436 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2437 info->memory_type = info_v11->memorytype; 2438 info->ma_channel_number = info_v11->umachannelnumber; 2439 info->lvds_ss_percentage = 2440 le16_to_cpu(info_v11->lvds_ss_percentage); 2441 info->dp_ss_control = 2442 le16_to_cpu(info_v11->reserved1); 2443 info->lvds_sspread_rate_in_10hz = 2444 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2445 info->hdmi_ss_percentage = 2446 le16_to_cpu(info_v11->hdmi_ss_percentage); 2447 info->hdmi_sspread_rate_in_10hz = 2448 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2449 info->dvi_ss_percentage = 2450 le16_to_cpu(info_v11->dvi_ss_percentage); 2451 info->dvi_sspread_rate_in_10_hz = 2452 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2453 info->lvds_misc = info_v11->lvds_misc; 2454 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2455 info->ext_disp_conn_info.gu_id[i] = 2456 info_v11->extdispconninfo.guid[i]; 2457 } 2458 2459 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2460 info->ext_disp_conn_info.path[i].device_connector_id = 2461 object_id_from_bios_object_id( 2462 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2463 2464 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2465 object_id_from_bios_object_id( 2466 le16_to_cpu( 2467 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2468 2469 info->ext_disp_conn_info.path[i].device_tag = 2470 le16_to_cpu( 2471 info_v11->extdispconninfo.path[i].device_tag); 2472 info->ext_disp_conn_info.path[i].device_acpi_enum = 2473 le16_to_cpu( 2474 info_v11->extdispconninfo.path[i].device_acpi_enum); 2475 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2476 info_v11->extdispconninfo.path[i].auxddclut_index; 2477 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2478 info_v11->extdispconninfo.path[i].hpdlut_index; 2479 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2480 info_v11->extdispconninfo.path[i].channelmapping; 2481 info->ext_disp_conn_info.path[i].caps = 2482 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2483 } 2484 info->ext_disp_conn_info.checksum = 2485 info_v11->extdispconninfo.checksum; 2486 2487 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2488 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2489 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2490 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2491 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2492 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2493 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2494 } 2495 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2496 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2497 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2498 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2499 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2500 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2501 } 2502 2503 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2504 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2505 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2506 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2507 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2508 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2509 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2510 } 2511 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2512 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2513 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2514 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2515 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2516 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2517 } 2518 2519 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2520 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2521 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2522 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2523 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2524 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2525 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2526 } 2527 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2528 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2529 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2530 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2531 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2532 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2533 } 2534 2535 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2536 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2537 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2538 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2539 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2540 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2541 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2542 } 2543 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2544 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2545 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2546 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2547 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2548 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2549 } 2550 2551 2552 /** TODO - review **/ 2553 #if 0 2554 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2555 * 10; 2556 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2557 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2558 2559 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2560 /* Convert [10KHz] into [KHz] */ 2561 info->disp_clk_voltage[i].max_supported_clk = 2562 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2563 ulMaximumSupportedCLK) * 10; 2564 info->disp_clk_voltage[i].voltage_index = 2565 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2566 } 2567 2568 info->boot_up_req_display_vector = 2569 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2570 info->boot_up_nb_voltage = 2571 le16_to_cpu(info_v11->usBootUpNBVoltage); 2572 info->ext_disp_conn_info_offset = 2573 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2574 info->gmc_restore_reset_time = 2575 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2576 info->minimum_n_clk = 2577 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2578 for (i = 1; i < 4; ++i) 2579 info->minimum_n_clk = 2580 info->minimum_n_clk < 2581 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2582 info->minimum_n_clk : le32_to_cpu( 2583 info_v11->ulNbpStateNClkFreq[i]); 2584 2585 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2586 info->ddr_dll_power_up_time = 2587 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2588 info->ddr_pll_power_up_time = 2589 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2590 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2591 info->max_lvds_pclk_freq_in_single_link = 2592 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2593 info->max_lvds_pclk_freq_in_single_link = 2594 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2595 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2596 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2597 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2598 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2599 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2600 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2601 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2602 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2603 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2604 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2605 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2606 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2607 info->lvds_off_to_on_delay_in_4ms = 2608 info_v11->ucLVDSOffToOnDelay_in4Ms; 2609 info->lvds_bit_depth_control_val = 2610 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2611 2612 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2613 /* Convert [10KHz] into [KHz] */ 2614 info->avail_s_clk[i].supported_s_clk = 2615 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2616 * 10; 2617 info->avail_s_clk[i].voltage_index = 2618 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2619 info->avail_s_clk[i].voltage_id = 2620 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2621 } 2622 #endif /* TODO*/ 2623 2624 return BP_RESULT_OK; 2625 } 2626 2627 static enum bp_result get_integrated_info_v2_1( 2628 struct bios_parser *bp, 2629 struct integrated_info *info) 2630 { 2631 struct atom_integrated_system_info_v2_1 *info_v2_1; 2632 uint32_t i; 2633 2634 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2635 DATA_TABLES(integratedsysteminfo)); 2636 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage); 2637 2638 if (info_v2_1 == NULL) 2639 return BP_RESULT_BADBIOSTABLE; 2640 2641 info->gpu_cap_info = 2642 le32_to_cpu(info_v2_1->gpucapinfo); 2643 /* 2644 * system_config: Bit[0] = 0 : PCIE power gating disabled 2645 * = 1 : PCIE power gating enabled 2646 * Bit[1] = 0 : DDR-PLL shut down disabled 2647 * = 1 : DDR-PLL shut down enabled 2648 * Bit[2] = 0 : DDR-PLL power down disabled 2649 * = 1 : DDR-PLL power down enabled 2650 */ 2651 info->system_config = le32_to_cpu(info_v2_1->system_config); 2652 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2653 info->memory_type = info_v2_1->memorytype; 2654 info->ma_channel_number = info_v2_1->umachannelnumber; 2655 info->dp_ss_control = 2656 le16_to_cpu(info_v2_1->reserved1); 2657 2658 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2659 info->ext_disp_conn_info.gu_id[i] = 2660 info_v2_1->extdispconninfo.guid[i]; 2661 } 2662 2663 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2664 info->ext_disp_conn_info.path[i].device_connector_id = 2665 object_id_from_bios_object_id( 2666 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2667 2668 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2669 object_id_from_bios_object_id( 2670 le16_to_cpu( 2671 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2672 2673 info->ext_disp_conn_info.path[i].device_tag = 2674 le16_to_cpu( 2675 info_v2_1->extdispconninfo.path[i].device_tag); 2676 info->ext_disp_conn_info.path[i].device_acpi_enum = 2677 le16_to_cpu( 2678 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2679 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2680 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2681 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2682 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2683 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2684 info_v2_1->extdispconninfo.path[i].channelmapping; 2685 info->ext_disp_conn_info.path[i].caps = 2686 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2687 } 2688 2689 info->ext_disp_conn_info.checksum = 2690 info_v2_1->extdispconninfo.checksum; 2691 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2692 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2693 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2694 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2695 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2696 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2697 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2698 } 2699 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2700 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2701 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2702 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2703 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2704 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2705 } 2706 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2707 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2708 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2709 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2710 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2711 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2712 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2713 } 2714 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2715 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2716 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2717 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2718 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2719 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2720 } 2721 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2722 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2723 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2724 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2725 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2726 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2727 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2728 } 2729 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2730 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2731 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2732 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2733 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2734 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2735 } 2736 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2737 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2738 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2739 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2740 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2741 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2742 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2743 } 2744 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2745 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2746 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2747 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2748 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2749 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2750 } 2751 2752 info->edp1_info.edp_backlight_pwm_hz = 2753 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2754 info->edp1_info.edp_ss_percentage = 2755 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2756 info->edp1_info.edp_ss_rate_10hz = 2757 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2758 info->edp1_info.edp_pwr_on_off_delay = 2759 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2760 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2761 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2762 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2763 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2764 info->edp1_info.edp_panel_bpc = 2765 info_v2_1->edp1_info.edp_panel_bpc; 2766 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2767 2768 info->edp2_info.edp_backlight_pwm_hz = 2769 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2770 info->edp2_info.edp_ss_percentage = 2771 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2772 info->edp2_info.edp_ss_rate_10hz = 2773 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2774 info->edp2_info.edp_pwr_on_off_delay = 2775 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2776 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2777 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2778 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2779 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2780 info->edp2_info.edp_panel_bpc = 2781 info_v2_1->edp2_info.edp_panel_bpc; 2782 info->edp2_info.edp_bootup_bl_level = 2783 info_v2_1->edp2_info.edp_bootup_bl_level; 2784 2785 return BP_RESULT_OK; 2786 } 2787 2788 static enum bp_result get_integrated_info_v2_2( 2789 struct bios_parser *bp, 2790 struct integrated_info *info) 2791 { 2792 struct atom_integrated_system_info_v2_2 *info_v2_2; 2793 uint32_t i; 2794 2795 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2796 DATA_TABLES(integratedsysteminfo)); 2797 2798 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage); 2799 2800 if (info_v2_2 == NULL) 2801 return BP_RESULT_BADBIOSTABLE; 2802 2803 info->gpu_cap_info = 2804 le32_to_cpu(info_v2_2->gpucapinfo); 2805 /* 2806 * system_config: Bit[0] = 0 : PCIE power gating disabled 2807 * = 1 : PCIE power gating enabled 2808 * Bit[1] = 0 : DDR-PLL shut down disabled 2809 * = 1 : DDR-PLL shut down enabled 2810 * Bit[2] = 0 : DDR-PLL power down disabled 2811 * = 1 : DDR-PLL power down enabled 2812 */ 2813 info->system_config = le32_to_cpu(info_v2_2->system_config); 2814 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2815 info->memory_type = info_v2_2->memorytype; 2816 info->ma_channel_number = info_v2_2->umachannelnumber; 2817 info->dp_ss_control = 2818 le16_to_cpu(info_v2_2->reserved1); 2819 2820 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2821 info->ext_disp_conn_info.gu_id[i] = 2822 info_v2_2->extdispconninfo.guid[i]; 2823 } 2824 2825 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2826 info->ext_disp_conn_info.path[i].device_connector_id = 2827 object_id_from_bios_object_id( 2828 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2829 2830 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2831 object_id_from_bios_object_id( 2832 le16_to_cpu( 2833 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2834 2835 info->ext_disp_conn_info.path[i].device_tag = 2836 le16_to_cpu( 2837 info_v2_2->extdispconninfo.path[i].device_tag); 2838 info->ext_disp_conn_info.path[i].device_acpi_enum = 2839 le16_to_cpu( 2840 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2841 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2842 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2843 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2844 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2845 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2846 info_v2_2->extdispconninfo.path[i].channelmapping; 2847 info->ext_disp_conn_info.path[i].caps = 2848 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2849 } 2850 2851 info->ext_disp_conn_info.checksum = 2852 info_v2_2->extdispconninfo.checksum; 2853 info->ext_disp_conn_info.fixdpvoltageswing = 2854 info_v2_2->extdispconninfo.fixdpvoltageswing; 2855 2856 info->edp1_info.edp_backlight_pwm_hz = 2857 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2858 info->edp1_info.edp_ss_percentage = 2859 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2860 info->edp1_info.edp_ss_rate_10hz = 2861 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2862 info->edp1_info.edp_pwr_on_off_delay = 2863 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2864 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2865 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2866 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2867 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2868 info->edp1_info.edp_panel_bpc = 2869 info_v2_2->edp1_info.edp_panel_bpc; 2870 info->edp1_info.edp_bootup_bl_level = 2871 2872 info->edp2_info.edp_backlight_pwm_hz = 2873 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2874 info->edp2_info.edp_ss_percentage = 2875 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2876 info->edp2_info.edp_ss_rate_10hz = 2877 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2878 info->edp2_info.edp_pwr_on_off_delay = 2879 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2880 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2881 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2882 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2883 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2884 info->edp2_info.edp_panel_bpc = 2885 info_v2_2->edp2_info.edp_panel_bpc; 2886 info->edp2_info.edp_bootup_bl_level = 2887 info_v2_2->edp2_info.edp_bootup_bl_level; 2888 2889 return BP_RESULT_OK; 2890 } 2891 2892 /* 2893 * construct_integrated_info 2894 * 2895 * @brief 2896 * Get integrated BIOS information based on table revision 2897 * 2898 * @param 2899 * bios_parser *bp - [in]BIOS parser handler to get master data table 2900 * integrated_info *info - [out] store and output integrated info 2901 * 2902 * @return 2903 * static enum bp_result - BP_RESULT_OK if information is available, 2904 * BP_RESULT_BADBIOSTABLE otherwise. 2905 */ 2906 static enum bp_result construct_integrated_info( 2907 struct bios_parser *bp, 2908 struct integrated_info *info) 2909 { 2910 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2911 2912 struct atom_common_table_header *header; 2913 struct atom_data_revision revision; 2914 2915 struct clock_voltage_caps temp = {0, 0}; 2916 uint32_t i; 2917 uint32_t j; 2918 2919 if (info && DATA_TABLES(integratedsysteminfo)) { 2920 header = GET_IMAGE(struct atom_common_table_header, 2921 DATA_TABLES(integratedsysteminfo)); 2922 2923 get_atom_data_table_revision(header, &revision); 2924 2925 switch (revision.major) { 2926 case 1: 2927 switch (revision.minor) { 2928 case 11: 2929 case 12: 2930 result = get_integrated_info_v11(bp, info); 2931 break; 2932 default: 2933 return result; 2934 } 2935 break; 2936 case 2: 2937 switch (revision.minor) { 2938 case 1: 2939 result = get_integrated_info_v2_1(bp, info); 2940 break; 2941 case 2: 2942 result = get_integrated_info_v2_2(bp, info); 2943 break; 2944 default: 2945 return result; 2946 } 2947 break; 2948 default: 2949 return result; 2950 } 2951 if (result == BP_RESULT_OK) { 2952 2953 DC_LOG_BIOS("edp1:\n" 2954 "\tedp_pwr_on_off_delay = %d\n" 2955 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2956 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2957 "\tedp_bootup_bl_level = %d\n", 2958 info->edp1_info.edp_pwr_on_off_delay, 2959 info->edp1_info.edp_pwr_on_vary_bl_to_blon, 2960 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff, 2961 info->edp1_info.edp_bootup_bl_level); 2962 DC_LOG_BIOS("edp2:\n" 2963 "\tedp_pwr_on_off_delayv = %d\n" 2964 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2965 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2966 "\tedp_bootup_bl_level = %d\n", 2967 info->edp2_info.edp_pwr_on_off_delay, 2968 info->edp2_info.edp_pwr_on_vary_bl_to_blon, 2969 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff, 2970 info->edp2_info.edp_bootup_bl_level); 2971 } 2972 } 2973 2974 if (result != BP_RESULT_OK) 2975 return result; 2976 else { 2977 // Log each external path 2978 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 2979 if (info->ext_disp_conn_info.path[i].device_tag != 0) 2980 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n" 2981 "DEVICE_TAG: 0x%x\n" 2982 "DEVICE_ACPI_ENUM: 0x%x\n" 2983 "DEVICE_CONNECTOR_ID: 0x%x\n" 2984 "EXT_AUX_DDC_LUT_INDEX: %d\n" 2985 "EXT_HPD_PIN_LUT_INDEX: %d\n" 2986 "EXT_ENCODER_OBJ_ID: 0x%x\n" 2987 "Encoder CAPS: 0x%x\n", 2988 i, 2989 info->ext_disp_conn_info.path[i].device_tag, 2990 info->ext_disp_conn_info.path[i].device_acpi_enum, 2991 info->ext_disp_conn_info.path[i].device_connector_id.id, 2992 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index, 2993 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index, 2994 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id, 2995 info->ext_disp_conn_info.path[i].caps 2996 ); 2997 } 2998 2999 // Log the Checksum and Voltage Swing 3000 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n" 3001 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n", 3002 info->ext_disp_conn_info.checksum, 3003 info->ext_disp_conn_info.fixdpvoltageswing); 3004 } 3005 /* Sort voltage table from low to high*/ 3006 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 3007 for (j = i; j > 0; --j) { 3008 if (info->disp_clk_voltage[j].max_supported_clk < 3009 info->disp_clk_voltage[j-1].max_supported_clk 3010 ) { 3011 /* swap j and j - 1*/ 3012 temp = info->disp_clk_voltage[j-1]; 3013 info->disp_clk_voltage[j-1] = 3014 info->disp_clk_voltage[j]; 3015 info->disp_clk_voltage[j] = temp; 3016 } 3017 } 3018 } 3019 3020 return result; 3021 } 3022 3023 static enum bp_result bios_parser_get_vram_info( 3024 struct dc_bios *dcb, 3025 struct dc_vram_info *info) 3026 { 3027 struct bios_parser *bp = BP_FROM_DCB(dcb); 3028 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 3029 struct atom_common_table_header *header; 3030 struct atom_data_revision revision; 3031 3032 if (info && DATA_TABLES(vram_info)) { 3033 header = GET_IMAGE(struct atom_common_table_header, 3034 DATA_TABLES(vram_info)); 3035 3036 get_atom_data_table_revision(header, &revision); 3037 3038 switch (revision.major) { 3039 case 2: 3040 switch (revision.minor) { 3041 case 3: 3042 result = get_vram_info_v23(bp, info); 3043 break; 3044 case 4: 3045 result = get_vram_info_v24(bp, info); 3046 break; 3047 case 5: 3048 result = get_vram_info_v25(bp, info); 3049 break; 3050 default: 3051 break; 3052 } 3053 break; 3054 3055 default: 3056 return result; 3057 } 3058 3059 } 3060 return result; 3061 } 3062 3063 static struct integrated_info *bios_parser_create_integrated_info( 3064 struct dc_bios *dcb) 3065 { 3066 struct bios_parser *bp = BP_FROM_DCB(dcb); 3067 struct integrated_info *info = NULL; 3068 3069 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 3070 3071 if (info == NULL) { 3072 ASSERT_CRITICAL(0); 3073 return NULL; 3074 } 3075 3076 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3077 return info; 3078 3079 kfree(info); 3080 3081 return NULL; 3082 } 3083 3084 static enum bp_result update_slot_layout_info( 3085 struct dc_bios *dcb, 3086 unsigned int i, 3087 struct slot_layout_info *slot_layout_info) 3088 { 3089 unsigned int record_offset; 3090 unsigned int j; 3091 struct atom_display_object_path_v2 *object; 3092 struct atom_bracket_layout_record *record; 3093 struct atom_common_record_header *record_header; 3094 static enum bp_result result; 3095 struct bios_parser *bp; 3096 struct object_info_table *tbl; 3097 struct display_object_info_table_v1_4 *v1_4; 3098 3099 record = NULL; 3100 record_header = NULL; 3101 result = BP_RESULT_NORECORD; 3102 3103 bp = BP_FROM_DCB(dcb); 3104 tbl = &bp->object_info_tbl; 3105 v1_4 = tbl->v1_4; 3106 3107 object = &v1_4->display_path[i]; 3108 record_offset = (unsigned int) 3109 (object->disp_recordoffset) + 3110 (unsigned int)(bp->object_info_tbl_offset); 3111 3112 for (;;) { 3113 3114 record_header = (struct atom_common_record_header *) 3115 GET_IMAGE(struct atom_common_record_header, 3116 record_offset); 3117 if (record_header == NULL) { 3118 result = BP_RESULT_BADBIOSTABLE; 3119 break; 3120 } 3121 3122 /* the end of the list */ 3123 if (record_header->record_type == 0xff || 3124 record_header->record_size == 0) { 3125 break; 3126 } 3127 3128 if (record_header->record_type == 3129 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3130 sizeof(struct atom_bracket_layout_record) 3131 <= record_header->record_size) { 3132 record = (struct atom_bracket_layout_record *) 3133 (record_header); 3134 result = BP_RESULT_OK; 3135 break; 3136 } 3137 3138 record_offset += record_header->record_size; 3139 } 3140 3141 /* return if the record not found */ 3142 if (result != BP_RESULT_OK) 3143 return result; 3144 3145 /* get slot sizes */ 3146 slot_layout_info->length = record->bracketlen; 3147 slot_layout_info->width = record->bracketwidth; 3148 3149 /* get info for each connector in the slot */ 3150 slot_layout_info->num_of_connectors = record->conn_num; 3151 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3152 slot_layout_info->connectors[j].connector_type = 3153 (enum connector_layout_type) 3154 (record->conn_info[j].connector_type); 3155 switch (record->conn_info[j].connector_type) { 3156 case CONNECTOR_TYPE_DVI_D: 3157 slot_layout_info->connectors[j].connector_type = 3158 CONNECTOR_LAYOUT_TYPE_DVI_D; 3159 slot_layout_info->connectors[j].length = 3160 CONNECTOR_SIZE_DVI; 3161 break; 3162 3163 case CONNECTOR_TYPE_HDMI: 3164 slot_layout_info->connectors[j].connector_type = 3165 CONNECTOR_LAYOUT_TYPE_HDMI; 3166 slot_layout_info->connectors[j].length = 3167 CONNECTOR_SIZE_HDMI; 3168 break; 3169 3170 case CONNECTOR_TYPE_DISPLAY_PORT: 3171 slot_layout_info->connectors[j].connector_type = 3172 CONNECTOR_LAYOUT_TYPE_DP; 3173 slot_layout_info->connectors[j].length = 3174 CONNECTOR_SIZE_DP; 3175 break; 3176 3177 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3178 slot_layout_info->connectors[j].connector_type = 3179 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3180 slot_layout_info->connectors[j].length = 3181 CONNECTOR_SIZE_MINI_DP; 3182 break; 3183 3184 default: 3185 slot_layout_info->connectors[j].connector_type = 3186 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3187 slot_layout_info->connectors[j].length = 3188 CONNECTOR_SIZE_UNKNOWN; 3189 } 3190 3191 slot_layout_info->connectors[j].position = 3192 record->conn_info[j].position; 3193 slot_layout_info->connectors[j].connector_id = 3194 object_id_from_bios_object_id( 3195 record->conn_info[j].connectorobjid); 3196 } 3197 return result; 3198 } 3199 3200 static enum bp_result update_slot_layout_info_v2( 3201 struct dc_bios *dcb, 3202 unsigned int i, 3203 struct slot_layout_info *slot_layout_info) 3204 { 3205 unsigned int record_offset; 3206 struct atom_display_object_path_v3 *object; 3207 struct atom_bracket_layout_record_v2 *record; 3208 struct atom_common_record_header *record_header; 3209 static enum bp_result result; 3210 struct bios_parser *bp; 3211 struct object_info_table *tbl; 3212 struct display_object_info_table_v1_5 *v1_5; 3213 struct graphics_object_id connector_id; 3214 3215 record = NULL; 3216 record_header = NULL; 3217 result = BP_RESULT_NORECORD; 3218 3219 bp = BP_FROM_DCB(dcb); 3220 tbl = &bp->object_info_tbl; 3221 v1_5 = tbl->v1_5; 3222 3223 object = &v1_5->display_path[i]; 3224 record_offset = (unsigned int) 3225 (object->disp_recordoffset) + 3226 (unsigned int)(bp->object_info_tbl_offset); 3227 3228 for (;;) { 3229 3230 record_header = (struct atom_common_record_header *) 3231 GET_IMAGE(struct atom_common_record_header, 3232 record_offset); 3233 if (record_header == NULL) { 3234 result = BP_RESULT_BADBIOSTABLE; 3235 break; 3236 } 3237 3238 /* the end of the list */ 3239 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3240 record_header->record_size == 0) { 3241 break; 3242 } 3243 3244 if (record_header->record_type == 3245 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3246 sizeof(struct atom_bracket_layout_record_v2) 3247 <= record_header->record_size) { 3248 record = (struct atom_bracket_layout_record_v2 *) 3249 (record_header); 3250 result = BP_RESULT_OK; 3251 break; 3252 } 3253 3254 record_offset += record_header->record_size; 3255 } 3256 3257 /* return if the record not found */ 3258 if (result != BP_RESULT_OK) 3259 return result; 3260 3261 /* get slot sizes */ 3262 connector_id = object_id_from_bios_object_id(object->display_objid); 3263 3264 slot_layout_info->length = record->bracketlen; 3265 slot_layout_info->width = record->bracketwidth; 3266 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3267 slot_layout_info->connectors[i].position = record->conn_num; 3268 slot_layout_info->connectors[i].connector_id = connector_id; 3269 3270 switch (connector_id.id) { 3271 case CONNECTOR_ID_SINGLE_LINK_DVID: 3272 case CONNECTOR_ID_DUAL_LINK_DVID: 3273 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3274 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3275 break; 3276 3277 case CONNECTOR_ID_HDMI_TYPE_A: 3278 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3279 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3280 break; 3281 3282 case CONNECTOR_ID_DISPLAY_PORT: 3283 case CONNECTOR_ID_USBC: 3284 if (record->mini_type == MINI_TYPE_NORMAL) { 3285 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3286 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3287 } else { 3288 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3289 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3290 } 3291 break; 3292 3293 default: 3294 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3295 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3296 } 3297 return result; 3298 } 3299 3300 static enum bp_result get_bracket_layout_record( 3301 struct dc_bios *dcb, 3302 unsigned int bracket_layout_id, 3303 struct slot_layout_info *slot_layout_info) 3304 { 3305 unsigned int i; 3306 struct bios_parser *bp = BP_FROM_DCB(dcb); 3307 static enum bp_result result; 3308 struct object_info_table *tbl; 3309 struct display_object_info_table_v1_4 *v1_4; 3310 struct display_object_info_table_v1_5 *v1_5; 3311 3312 if (slot_layout_info == NULL) { 3313 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3314 return BP_RESULT_BADINPUT; 3315 } 3316 tbl = &bp->object_info_tbl; 3317 v1_4 = tbl->v1_4; 3318 v1_5 = tbl->v1_5; 3319 3320 result = BP_RESULT_NORECORD; 3321 switch (bp->object_info_tbl.revision.minor) { 3322 case 4: 3323 default: 3324 for (i = 0; i < v1_4->number_of_path; ++i) { 3325 if (bracket_layout_id == 3326 v1_4->display_path[i].display_objid) { 3327 result = update_slot_layout_info(dcb, i, slot_layout_info); 3328 break; 3329 } 3330 } 3331 break; 3332 case 5: 3333 for (i = 0; i < v1_5->number_of_path; ++i) 3334 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3335 break; 3336 } 3337 return result; 3338 } 3339 3340 static enum bp_result bios_get_board_layout_info( 3341 struct dc_bios *dcb, 3342 struct board_layout_info *board_layout_info) 3343 { 3344 unsigned int i; 3345 3346 struct bios_parser *bp; 3347 3348 static enum bp_result record_result; 3349 unsigned int max_slots; 3350 3351 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3352 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3353 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3354 0, 0 3355 }; 3356 3357 3358 bp = BP_FROM_DCB(dcb); 3359 3360 if (board_layout_info == NULL) { 3361 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3362 return BP_RESULT_BADINPUT; 3363 } 3364 3365 board_layout_info->num_of_slots = 0; 3366 max_slots = MAX_BOARD_SLOTS; 3367 3368 // Assume single slot on v1_5 3369 if (bp->object_info_tbl.revision.minor == 5) { 3370 max_slots = 1; 3371 } 3372 3373 for (i = 0; i < max_slots; ++i) { 3374 record_result = get_bracket_layout_record(dcb, 3375 slot_index_to_vbios_id[i], 3376 &board_layout_info->slots[i]); 3377 3378 if (record_result == BP_RESULT_NORECORD && i > 0) 3379 break; /* no more slots present in bios */ 3380 else if (record_result != BP_RESULT_OK) 3381 return record_result; /* fail */ 3382 3383 ++board_layout_info->num_of_slots; 3384 } 3385 3386 /* all data is valid */ 3387 board_layout_info->is_number_of_slots_valid = 1; 3388 board_layout_info->is_slots_size_valid = 1; 3389 board_layout_info->is_connector_offsets_valid = 1; 3390 board_layout_info->is_connector_lengths_valid = 1; 3391 3392 return BP_RESULT_OK; 3393 } 3394 3395 3396 static uint16_t bios_parser_pack_data_tables( 3397 struct dc_bios *dcb, 3398 void *dst) 3399 { 3400 // TODO: There is data bytes alignment issue, disable it for now. 3401 return 0; 3402 } 3403 3404 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3405 struct bios_parser *bp, 3406 uint32_t rev_major, 3407 uint32_t rev_minor, 3408 uint16_t *dc_golden_table_ver) 3409 { 3410 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3411 uint32_t dc_golden_offset = 0; 3412 *dc_golden_table_ver = 0; 3413 3414 if (!DATA_TABLES(dce_info)) 3415 return NULL; 3416 3417 /* ver.4.4 or higher */ 3418 switch (rev_major) { 3419 case 4: 3420 switch (rev_minor) { 3421 case 4: 3422 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3423 DATA_TABLES(dce_info)); 3424 if (!disp_cntl_tbl_4_4) 3425 return NULL; 3426 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3427 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3428 break; 3429 case 5: 3430 default: 3431 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3432 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3433 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3434 */ 3435 break; 3436 } 3437 break; 3438 } 3439 3440 if (!dc_golden_offset) 3441 return NULL; 3442 3443 if (*dc_golden_table_ver != 1) 3444 return NULL; 3445 3446 return GET_IMAGE(struct atom_dc_golden_table_v1, 3447 dc_golden_offset); 3448 } 3449 3450 static enum bp_result bios_get_atom_dc_golden_table( 3451 struct dc_bios *dcb) 3452 { 3453 struct bios_parser *bp = BP_FROM_DCB(dcb); 3454 enum bp_result result = BP_RESULT_OK; 3455 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3456 struct atom_common_table_header *header; 3457 struct atom_data_revision tbl_revision; 3458 uint16_t dc_golden_table_ver = 0; 3459 3460 header = GET_IMAGE(struct atom_common_table_header, 3461 DATA_TABLES(dce_info)); 3462 if (!header) 3463 return BP_RESULT_UNSUPPORTED; 3464 3465 get_atom_data_table_revision(header, &tbl_revision); 3466 3467 atom_dc_golden_table = bios_get_golden_table(bp, 3468 tbl_revision.major, 3469 tbl_revision.minor, 3470 &dc_golden_table_ver); 3471 3472 if (!atom_dc_golden_table) 3473 return BP_RESULT_UNSUPPORTED; 3474 3475 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3476 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3477 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3478 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3479 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3480 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3481 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3482 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3483 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3484 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3485 3486 return result; 3487 } 3488 3489 3490 static const struct dc_vbios_funcs vbios_funcs = { 3491 .get_connectors_number = bios_parser_get_connectors_number, 3492 3493 .get_connector_id = bios_parser_get_connector_id, 3494 3495 .get_src_obj = bios_parser_get_src_obj, 3496 3497 .get_i2c_info = bios_parser_get_i2c_info, 3498 3499 .get_hpd_info = bios_parser_get_hpd_info, 3500 3501 .get_device_tag = bios_parser_get_device_tag, 3502 3503 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3504 3505 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3506 3507 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3508 3509 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3510 3511 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3512 3513 .is_device_id_supported = bios_parser_is_device_id_supported, 3514 3515 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3516 3517 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3518 3519 3520 /* COMMANDS */ 3521 .encoder_control = bios_parser_encoder_control, 3522 3523 .transmitter_control = bios_parser_transmitter_control, 3524 3525 .enable_crtc = bios_parser_enable_crtc, 3526 3527 .set_pixel_clock = bios_parser_set_pixel_clock, 3528 3529 .set_dce_clock = bios_parser_set_dce_clock, 3530 3531 .program_crtc_timing = bios_parser_program_crtc_timing, 3532 3533 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3534 3535 .bios_parser_destroy = firmware_parser_destroy, 3536 3537 .get_board_layout_info = bios_get_board_layout_info, 3538 /* TODO: use this fn in hw init?*/ 3539 .pack_data_tables = bios_parser_pack_data_tables, 3540 3541 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3542 3543 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3544 3545 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3546 3547 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3548 3549 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3550 3551 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3552 3553 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3554 }; 3555 3556 static bool bios_parser2_construct( 3557 struct bios_parser *bp, 3558 struct bp_init_data *init, 3559 enum dce_version dce_version) 3560 { 3561 uint16_t *rom_header_offset = NULL; 3562 struct atom_rom_header_v2_2 *rom_header = NULL; 3563 struct display_object_info_table_v1_4 *object_info_tbl; 3564 struct atom_data_revision tbl_rev = {0}; 3565 3566 if (!init) 3567 return false; 3568 3569 if (!init->bios) 3570 return false; 3571 3572 bp->base.funcs = &vbios_funcs; 3573 bp->base.bios = init->bios; 3574 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3575 3576 bp->base.ctx = init->ctx; 3577 3578 bp->base.bios_local_image = NULL; 3579 3580 rom_header_offset = 3581 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3582 3583 if (!rom_header_offset) 3584 return false; 3585 3586 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3587 3588 if (!rom_header) 3589 return false; 3590 3591 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3592 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3593 return false; 3594 3595 bp->master_data_tbl = 3596 GET_IMAGE(struct atom_master_data_table_v2_1, 3597 rom_header->masterdatatable_offset); 3598 3599 if (!bp->master_data_tbl) 3600 return false; 3601 3602 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3603 3604 if (!bp->object_info_tbl_offset) 3605 return false; 3606 3607 object_info_tbl = 3608 GET_IMAGE(struct display_object_info_table_v1_4, 3609 bp->object_info_tbl_offset); 3610 3611 if (!object_info_tbl) 3612 return false; 3613 3614 get_atom_data_table_revision(&object_info_tbl->table_header, 3615 &bp->object_info_tbl.revision); 3616 3617 if (bp->object_info_tbl.revision.major == 1 3618 && bp->object_info_tbl.revision.minor == 4) { 3619 struct display_object_info_table_v1_4 *tbl_v1_4; 3620 3621 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3622 bp->object_info_tbl_offset); 3623 if (!tbl_v1_4) 3624 return false; 3625 3626 bp->object_info_tbl.v1_4 = tbl_v1_4; 3627 } else if (bp->object_info_tbl.revision.major == 1 3628 && bp->object_info_tbl.revision.minor == 5) { 3629 struct display_object_info_table_v1_5 *tbl_v1_5; 3630 3631 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3632 bp->object_info_tbl_offset); 3633 if (!tbl_v1_5) 3634 return false; 3635 3636 bp->object_info_tbl.v1_5 = tbl_v1_5; 3637 } else { 3638 ASSERT(0); 3639 return false; 3640 } 3641 3642 dal_firmware_parser_init_cmd_tbl(bp); 3643 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3644 3645 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3646 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3647 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3648 3649 return true; 3650 } 3651 3652 struct dc_bios *firmware_parser_create( 3653 struct bp_init_data *init, 3654 enum dce_version dce_version) 3655 { 3656 struct bios_parser *bp = NULL; 3657 3658 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 3659 if (!bp) 3660 return NULL; 3661 3662 if (bios_parser2_construct(bp, init, dce_version)) 3663 return &bp->base; 3664 3665 kfree(bp); 3666 return NULL; 3667 } 3668 3669 3670