1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "dc_bios_types.h" 32 #include "include/grph_object_ctrl_defs.h" 33 #include "include/bios_parser_interface.h" 34 #include "include/i2caux_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 #define LAST_RECORD_TYPE 0xff 47 48 49 struct i2c_id_config_access { 50 uint8_t bfI2C_LineMux:4; 51 uint8_t bfHW_EngineID:3; 52 uint8_t bfHW_Capable:1; 53 uint8_t ucAccess; 54 }; 55 56 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 57 struct atom_i2c_record *record, 58 struct graphics_object_i2c_info *info); 59 60 static enum bp_result bios_parser_get_firmware_info( 61 struct dc_bios *dcb, 62 struct dc_firmware_info *info); 63 64 static enum bp_result bios_parser_get_encoder_cap_info( 65 struct dc_bios *dcb, 66 struct graphics_object_id object_id, 67 struct bp_encoder_cap_info *info); 68 69 static enum bp_result get_firmware_info_v3_1( 70 struct bios_parser *bp, 71 struct dc_firmware_info *info); 72 73 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 74 struct atom_display_object_path_v2 *object); 75 76 static struct atom_encoder_caps_record *get_encoder_cap_record( 77 struct bios_parser *bp, 78 struct atom_display_object_path_v2 *object); 79 80 #define BIOS_IMAGE_SIZE_OFFSET 2 81 #define BIOS_IMAGE_SIZE_UNIT 512 82 83 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 84 85 86 static void destruct(struct bios_parser *bp) 87 { 88 if (bp->base.bios_local_image) 89 kfree(bp->base.bios_local_image); 90 91 if (bp->base.integrated_info) 92 kfree(bp->base.integrated_info); 93 } 94 95 static void firmware_parser_destroy(struct dc_bios **dcb) 96 { 97 struct bios_parser *bp = BP_FROM_DCB(*dcb); 98 99 if (!bp) { 100 BREAK_TO_DEBUGGER(); 101 return; 102 } 103 104 destruct(bp); 105 106 kfree(bp); 107 *dcb = NULL; 108 } 109 110 static void get_atom_data_table_revision( 111 struct atom_common_table_header *atom_data_tbl, 112 struct atom_data_revision *tbl_revision) 113 { 114 if (!tbl_revision) 115 return; 116 117 /* initialize the revision to 0 which is invalid revision */ 118 tbl_revision->major = 0; 119 tbl_revision->minor = 0; 120 121 if (!atom_data_tbl) 122 return; 123 124 tbl_revision->major = 125 (uint32_t) atom_data_tbl->format_revision & 0x3f; 126 tbl_revision->minor = 127 (uint32_t) atom_data_tbl->content_revision & 0x3f; 128 } 129 130 /* BIOS oject table displaypath is per connector. 131 * There is extra path not for connector. BIOS fill its encoderid as 0 132 */ 133 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 134 { 135 struct bios_parser *bp = BP_FROM_DCB(dcb); 136 unsigned int count = 0; 137 unsigned int i; 138 139 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 140 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 141 count++; 142 } 143 return count; 144 } 145 146 static struct graphics_object_id bios_parser_get_encoder_id( 147 struct dc_bios *dcb, 148 uint32_t i) 149 { 150 struct bios_parser *bp = BP_FROM_DCB(dcb); 151 struct graphics_object_id object_id = dal_graphics_object_id_init( 152 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 153 154 if (bp->object_info_tbl.v1_4->number_of_path > i) 155 object_id = object_id_from_bios_object_id( 156 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 157 158 return object_id; 159 } 160 161 static struct graphics_object_id bios_parser_get_connector_id( 162 struct dc_bios *dcb, 163 uint8_t i) 164 { 165 struct bios_parser *bp = BP_FROM_DCB(dcb); 166 struct graphics_object_id object_id = dal_graphics_object_id_init( 167 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 168 struct object_info_table *tbl = &bp->object_info_tbl; 169 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 170 171 if (v1_4->number_of_path > i) { 172 /* If display_objid is generic object id, the encoderObj 173 * /extencoderobjId should be 0 174 */ 175 if (v1_4->display_path[i].encoderobjid != 0 && 176 v1_4->display_path[i].display_objid != 0) 177 object_id = object_id_from_bios_object_id( 178 v1_4->display_path[i].display_objid); 179 } 180 181 return object_id; 182 } 183 184 185 /* TODO: GetNumberOfSrc*/ 186 187 static uint32_t bios_parser_get_dst_number(struct dc_bios *dcb, 188 struct graphics_object_id id) 189 { 190 /* connector has 1 Dest, encoder has 0 Dest */ 191 switch (id.type) { 192 case OBJECT_TYPE_ENCODER: 193 return 0; 194 case OBJECT_TYPE_CONNECTOR: 195 return 1; 196 default: 197 return 0; 198 } 199 } 200 201 /* removed getSrcObjList, getDestObjList*/ 202 203 204 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 205 struct graphics_object_id object_id, uint32_t index, 206 struct graphics_object_id *src_object_id) 207 { 208 struct bios_parser *bp = BP_FROM_DCB(dcb); 209 unsigned int i; 210 enum bp_result bp_result = BP_RESULT_BADINPUT; 211 struct graphics_object_id obj_id = {0}; 212 struct object_info_table *tbl = &bp->object_info_tbl; 213 214 if (!src_object_id) 215 return bp_result; 216 217 switch (object_id.type) { 218 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 219 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 220 */ 221 case OBJECT_TYPE_ENCODER: 222 /* TODO: since num of src must be less than 2. 223 * If found in for loop, should break. 224 * DAL2 implementation may be changed too 225 */ 226 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 227 obj_id = object_id_from_bios_object_id( 228 tbl->v1_4->display_path[i].encoderobjid); 229 if (object_id.type == obj_id.type && 230 object_id.id == obj_id.id && 231 object_id.enum_id == 232 obj_id.enum_id) { 233 *src_object_id = 234 object_id_from_bios_object_id(0x1100); 235 /* break; */ 236 } 237 } 238 bp_result = BP_RESULT_OK; 239 break; 240 case OBJECT_TYPE_CONNECTOR: 241 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 242 obj_id = object_id_from_bios_object_id( 243 tbl->v1_4->display_path[i].display_objid); 244 245 if (object_id.type == obj_id.type && 246 object_id.id == obj_id.id && 247 object_id.enum_id == obj_id.enum_id) { 248 *src_object_id = 249 object_id_from_bios_object_id( 250 tbl->v1_4->display_path[i].encoderobjid); 251 /* break; */ 252 } 253 } 254 bp_result = BP_RESULT_OK; 255 break; 256 default: 257 break; 258 } 259 260 return bp_result; 261 } 262 263 static enum bp_result bios_parser_get_dst_obj(struct dc_bios *dcb, 264 struct graphics_object_id object_id, uint32_t index, 265 struct graphics_object_id *dest_object_id) 266 { 267 struct bios_parser *bp = BP_FROM_DCB(dcb); 268 unsigned int i; 269 enum bp_result bp_result = BP_RESULT_BADINPUT; 270 struct graphics_object_id obj_id = {0}; 271 struct object_info_table *tbl = &bp->object_info_tbl; 272 273 if (!dest_object_id) 274 return BP_RESULT_BADINPUT; 275 276 switch (object_id.type) { 277 case OBJECT_TYPE_ENCODER: 278 /* TODO: since num of src must be less than 2. 279 * If found in for loop, should break. 280 * DAL2 implementation may be changed too 281 */ 282 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 283 obj_id = object_id_from_bios_object_id( 284 tbl->v1_4->display_path[i].encoderobjid); 285 if (object_id.type == obj_id.type && 286 object_id.id == obj_id.id && 287 object_id.enum_id == 288 obj_id.enum_id) { 289 *dest_object_id = 290 object_id_from_bios_object_id( 291 tbl->v1_4->display_path[i].display_objid); 292 /* break; */ 293 } 294 } 295 bp_result = BP_RESULT_OK; 296 break; 297 default: 298 break; 299 } 300 301 return bp_result; 302 } 303 304 305 /* from graphics_object_id, find display path which includes the object_id */ 306 static struct atom_display_object_path_v2 *get_bios_object( 307 struct bios_parser *bp, 308 struct graphics_object_id id) 309 { 310 unsigned int i; 311 struct graphics_object_id obj_id = {0}; 312 313 switch (id.type) { 314 case OBJECT_TYPE_ENCODER: 315 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 316 obj_id = object_id_from_bios_object_id( 317 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 318 if (id.type == obj_id.type && 319 id.id == obj_id.id && 320 id.enum_id == obj_id.enum_id) 321 return 322 &bp->object_info_tbl.v1_4->display_path[i]; 323 } 324 case OBJECT_TYPE_CONNECTOR: 325 case OBJECT_TYPE_GENERIC: 326 /* Both Generic and Connector Object ID 327 * will be stored on display_objid 328 */ 329 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 330 obj_id = object_id_from_bios_object_id( 331 bp->object_info_tbl.v1_4->display_path[i].display_objid 332 ); 333 if (id.type == obj_id.type && 334 id.id == obj_id.id && 335 id.enum_id == obj_id.enum_id) 336 return 337 &bp->object_info_tbl.v1_4->display_path[i]; 338 } 339 default: 340 return NULL; 341 } 342 } 343 344 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 345 struct graphics_object_id id, 346 struct graphics_object_i2c_info *info) 347 { 348 uint32_t offset; 349 struct atom_display_object_path_v2 *object; 350 struct atom_common_record_header *header; 351 struct atom_i2c_record *record; 352 struct bios_parser *bp = BP_FROM_DCB(dcb); 353 354 if (!info) 355 return BP_RESULT_BADINPUT; 356 357 object = get_bios_object(bp, id); 358 359 if (!object) 360 return BP_RESULT_BADINPUT; 361 362 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 363 364 for (;;) { 365 header = GET_IMAGE(struct atom_common_record_header, offset); 366 367 if (!header) 368 return BP_RESULT_BADBIOSTABLE; 369 370 if (header->record_type == LAST_RECORD_TYPE || 371 !header->record_size) 372 break; 373 374 if (header->record_type == ATOM_I2C_RECORD_TYPE 375 && sizeof(struct atom_i2c_record) <= 376 header->record_size) { 377 /* get the I2C info */ 378 record = (struct atom_i2c_record *) header; 379 380 if (get_gpio_i2c_info(bp, record, info) == 381 BP_RESULT_OK) 382 return BP_RESULT_OK; 383 } 384 385 offset += header->record_size; 386 } 387 388 return BP_RESULT_NORECORD; 389 } 390 391 static enum bp_result get_gpio_i2c_info( 392 struct bios_parser *bp, 393 struct atom_i2c_record *record, 394 struct graphics_object_i2c_info *info) 395 { 396 struct atom_gpio_pin_lut_v2_1 *header; 397 uint32_t count = 0; 398 unsigned int table_index = 0; 399 400 if (!info) 401 return BP_RESULT_BADINPUT; 402 403 /* get the GPIO_I2C info */ 404 if (!DATA_TABLES(gpio_pin_lut)) 405 return BP_RESULT_BADBIOSTABLE; 406 407 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 408 DATA_TABLES(gpio_pin_lut)); 409 if (!header) 410 return BP_RESULT_BADBIOSTABLE; 411 412 if (sizeof(struct atom_common_table_header) + 413 sizeof(struct atom_gpio_pin_assignment) > 414 le16_to_cpu(header->table_header.structuresize)) 415 return BP_RESULT_BADBIOSTABLE; 416 417 /* TODO: is version change? */ 418 if (header->table_header.content_revision != 1) 419 return BP_RESULT_UNSUPPORTED; 420 421 /* get data count */ 422 count = (le16_to_cpu(header->table_header.structuresize) 423 - sizeof(struct atom_common_table_header)) 424 / sizeof(struct atom_gpio_pin_assignment); 425 426 table_index = record->i2c_id & I2C_HW_LANE_MUX; 427 428 if (count < table_index) { 429 bool find_valid = false; 430 431 for (table_index = 0; table_index < count; table_index++) { 432 if (((record->i2c_id & I2C_HW_CAP) == ( 433 header->gpio_pin[table_index].gpio_id & 434 I2C_HW_CAP)) && 435 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 436 (header->gpio_pin[table_index].gpio_id & 437 I2C_HW_ENGINE_ID_MASK)) && 438 ((record->i2c_id & I2C_HW_LANE_MUX) == 439 (header->gpio_pin[table_index].gpio_id & 440 I2C_HW_LANE_MUX))) { 441 /* still valid */ 442 find_valid = true; 443 break; 444 } 445 } 446 /* If we don't find the entry that we are looking for then 447 * we will return BP_Result_BadBiosTable. 448 */ 449 if (find_valid == false) 450 return BP_RESULT_BADBIOSTABLE; 451 } 452 453 /* get the GPIO_I2C_INFO */ 454 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 455 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 456 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 457 info->i2c_slave_address = record->i2c_slave_addr; 458 459 /* TODO: check how to get register offset for en, Y, etc. */ 460 info->gpio_info.clk_a_register_index = 461 le16_to_cpu( 462 header->gpio_pin[table_index].data_a_reg_index); 463 info->gpio_info.clk_a_shift = 464 header->gpio_pin[table_index].gpio_bitshift; 465 466 return BP_RESULT_OK; 467 } 468 469 static enum bp_result get_voltage_ddc_info_v4( 470 uint8_t *i2c_line, 471 uint32_t index, 472 struct atom_common_table_header *header, 473 uint8_t *address) 474 { 475 enum bp_result result = BP_RESULT_NORECORD; 476 struct atom_voltage_objects_info_v4_1 *info = 477 (struct atom_voltage_objects_info_v4_1 *) address; 478 479 uint8_t *voltage_current_object = 480 (uint8_t *) (&(info->voltage_object[0])); 481 482 while ((address + le16_to_cpu(header->structuresize)) > 483 voltage_current_object) { 484 struct atom_i2c_voltage_object_v4 *object = 485 (struct atom_i2c_voltage_object_v4 *) 486 voltage_current_object; 487 488 if (object->header.voltage_mode == 489 ATOM_INIT_VOLTAGE_REGULATOR) { 490 if (object->header.voltage_type == index) { 491 *i2c_line = object->i2c_id ^ 0x90; 492 result = BP_RESULT_OK; 493 break; 494 } 495 } 496 497 voltage_current_object += 498 le16_to_cpu(object->header.object_size); 499 } 500 return result; 501 } 502 503 static enum bp_result bios_parser_get_thermal_ddc_info( 504 struct dc_bios *dcb, 505 uint32_t i2c_channel_id, 506 struct graphics_object_i2c_info *info) 507 { 508 struct bios_parser *bp = BP_FROM_DCB(dcb); 509 struct i2c_id_config_access *config; 510 struct atom_i2c_record record; 511 512 if (!info) 513 return BP_RESULT_BADINPUT; 514 515 config = (struct i2c_id_config_access *) &i2c_channel_id; 516 517 record.i2c_id = config->bfHW_Capable; 518 record.i2c_id |= config->bfI2C_LineMux; 519 record.i2c_id |= config->bfHW_EngineID; 520 521 return get_gpio_i2c_info(bp, &record, info); 522 } 523 524 static enum bp_result bios_parser_get_voltage_ddc_info(struct dc_bios *dcb, 525 uint32_t index, 526 struct graphics_object_i2c_info *info) 527 { 528 uint8_t i2c_line = 0; 529 enum bp_result result = BP_RESULT_NORECORD; 530 uint8_t *voltage_info_address; 531 struct atom_common_table_header *header; 532 struct atom_data_revision revision = {0}; 533 struct bios_parser *bp = BP_FROM_DCB(dcb); 534 535 if (!DATA_TABLES(voltageobject_info)) 536 return result; 537 538 voltage_info_address = get_image(&bp->base, 539 DATA_TABLES(voltageobject_info), 540 sizeof(struct atom_common_table_header)); 541 542 header = (struct atom_common_table_header *) voltage_info_address; 543 544 get_atom_data_table_revision(header, &revision); 545 546 switch (revision.major) { 547 case 4: 548 if (revision.minor != 1) 549 break; 550 result = get_voltage_ddc_info_v4(&i2c_line, index, header, 551 voltage_info_address); 552 break; 553 } 554 555 if (result == BP_RESULT_OK) 556 result = bios_parser_get_thermal_ddc_info(dcb, 557 i2c_line, info); 558 559 return result; 560 } 561 562 static enum bp_result bios_parser_get_hpd_info( 563 struct dc_bios *dcb, 564 struct graphics_object_id id, 565 struct graphics_object_hpd_info *info) 566 { 567 struct bios_parser *bp = BP_FROM_DCB(dcb); 568 struct atom_display_object_path_v2 *object; 569 struct atom_hpd_int_record *record = NULL; 570 571 if (!info) 572 return BP_RESULT_BADINPUT; 573 574 object = get_bios_object(bp, id); 575 576 if (!object) 577 return BP_RESULT_BADINPUT; 578 579 record = get_hpd_record(bp, object); 580 581 if (record != NULL) { 582 info->hpd_int_gpio_uid = record->pin_id; 583 info->hpd_active = record->plugin_pin_state; 584 return BP_RESULT_OK; 585 } 586 587 return BP_RESULT_NORECORD; 588 } 589 590 static struct atom_hpd_int_record *get_hpd_record( 591 struct bios_parser *bp, 592 struct atom_display_object_path_v2 *object) 593 { 594 struct atom_common_record_header *header; 595 uint32_t offset; 596 597 if (!object) { 598 BREAK_TO_DEBUGGER(); /* Invalid object */ 599 return NULL; 600 } 601 602 offset = le16_to_cpu(object->disp_recordoffset) 603 + bp->object_info_tbl_offset; 604 605 for (;;) { 606 header = GET_IMAGE(struct atom_common_record_header, offset); 607 608 if (!header) 609 return NULL; 610 611 if (header->record_type == LAST_RECORD_TYPE || 612 !header->record_size) 613 break; 614 615 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 616 && sizeof(struct atom_hpd_int_record) <= 617 header->record_size) 618 return (struct atom_hpd_int_record *) header; 619 620 offset += header->record_size; 621 } 622 623 return NULL; 624 } 625 626 /** 627 * bios_parser_get_gpio_pin_info 628 * Get GpioPin information of input gpio id 629 * 630 * @param gpio_id, GPIO ID 631 * @param info, GpioPin information structure 632 * @return Bios parser result code 633 * @note 634 * to get the GPIO PIN INFO, we need: 635 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 636 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 637 * to get the registerA offset/mask 638 */ 639 static enum bp_result bios_parser_get_gpio_pin_info( 640 struct dc_bios *dcb, 641 uint32_t gpio_id, 642 struct gpio_pin_info *info) 643 { 644 struct bios_parser *bp = BP_FROM_DCB(dcb); 645 struct atom_gpio_pin_lut_v2_1 *header; 646 uint32_t count = 0; 647 uint32_t i = 0; 648 649 if (!DATA_TABLES(gpio_pin_lut)) 650 return BP_RESULT_BADBIOSTABLE; 651 652 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 653 DATA_TABLES(gpio_pin_lut)); 654 if (!header) 655 return BP_RESULT_BADBIOSTABLE; 656 657 if (sizeof(struct atom_common_table_header) + 658 sizeof(struct atom_gpio_pin_lut_v2_1) 659 > le16_to_cpu(header->table_header.structuresize)) 660 return BP_RESULT_BADBIOSTABLE; 661 662 if (header->table_header.content_revision != 1) 663 return BP_RESULT_UNSUPPORTED; 664 665 /* Temporary hard code gpio pin info */ 666 #if defined(FOR_SIMNOW_BOOT) 667 { 668 struct atom_gpio_pin_assignment gpio_pin[8] = { 669 {0x5db5, 0, 0, 1, 0}, 670 {0x5db5, 8, 8, 2, 0}, 671 {0x5db5, 0x10, 0x10, 3, 0}, 672 {0x5db5, 0x18, 0x14, 4, 0}, 673 {0x5db5, 0x1A, 0x18, 5, 0}, 674 {0x5db5, 0x1C, 0x1C, 6, 0}, 675 }; 676 677 count = 6; 678 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 679 } 680 #else 681 count = (le16_to_cpu(header->table_header.structuresize) 682 - sizeof(struct atom_common_table_header)) 683 / sizeof(struct atom_gpio_pin_assignment); 684 #endif 685 for (i = 0; i < count; ++i) { 686 if (header->gpio_pin[i].gpio_id != gpio_id) 687 continue; 688 689 info->offset = 690 (uint32_t) le16_to_cpu( 691 header->gpio_pin[i].data_a_reg_index); 692 info->offset_y = info->offset + 2; 693 info->offset_en = info->offset + 1; 694 info->offset_mask = info->offset - 1; 695 696 info->mask = (uint32_t) (1 << 697 header->gpio_pin[i].gpio_bitshift); 698 info->mask_y = info->mask + 2; 699 info->mask_en = info->mask + 1; 700 info->mask_mask = info->mask - 1; 701 702 return BP_RESULT_OK; 703 } 704 705 return BP_RESULT_NORECORD; 706 } 707 708 static struct device_id device_type_from_device_id(uint16_t device_id) 709 { 710 711 struct device_id result_device_id; 712 713 result_device_id.raw_device_tag = device_id; 714 715 switch (device_id) { 716 case ATOM_DISPLAY_LCD1_SUPPORT: 717 result_device_id.device_type = DEVICE_TYPE_LCD; 718 result_device_id.enum_id = 1; 719 break; 720 721 case ATOM_DISPLAY_DFP1_SUPPORT: 722 result_device_id.device_type = DEVICE_TYPE_DFP; 723 result_device_id.enum_id = 1; 724 break; 725 726 case ATOM_DISPLAY_DFP2_SUPPORT: 727 result_device_id.device_type = DEVICE_TYPE_DFP; 728 result_device_id.enum_id = 2; 729 break; 730 731 case ATOM_DISPLAY_DFP3_SUPPORT: 732 result_device_id.device_type = DEVICE_TYPE_DFP; 733 result_device_id.enum_id = 3; 734 break; 735 736 case ATOM_DISPLAY_DFP4_SUPPORT: 737 result_device_id.device_type = DEVICE_TYPE_DFP; 738 result_device_id.enum_id = 4; 739 break; 740 741 case ATOM_DISPLAY_DFP5_SUPPORT: 742 result_device_id.device_type = DEVICE_TYPE_DFP; 743 result_device_id.enum_id = 5; 744 break; 745 746 case ATOM_DISPLAY_DFP6_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_DFP; 748 result_device_id.enum_id = 6; 749 break; 750 751 default: 752 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 753 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 754 result_device_id.enum_id = 0; 755 } 756 return result_device_id; 757 } 758 759 static enum bp_result bios_parser_get_device_tag( 760 struct dc_bios *dcb, 761 struct graphics_object_id connector_object_id, 762 uint32_t device_tag_index, 763 struct connector_device_tag_info *info) 764 { 765 struct bios_parser *bp = BP_FROM_DCB(dcb); 766 struct atom_display_object_path_v2 *object; 767 768 if (!info) 769 return BP_RESULT_BADINPUT; 770 771 /* getBiosObject will return MXM object */ 772 object = get_bios_object(bp, connector_object_id); 773 774 if (!object) { 775 BREAK_TO_DEBUGGER(); /* Invalid object id */ 776 return BP_RESULT_BADINPUT; 777 } 778 779 info->acpi_device = 0; /* BIOS no longer provides this */ 780 info->dev_id = device_type_from_device_id(object->device_tag); 781 782 return BP_RESULT_OK; 783 } 784 785 static enum bp_result get_ss_info_v4_1( 786 struct bios_parser *bp, 787 uint32_t id, 788 uint32_t index, 789 struct spread_spectrum_info *ss_info) 790 { 791 enum bp_result result = BP_RESULT_OK; 792 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 793 794 if (!ss_info) 795 return BP_RESULT_BADINPUT; 796 797 if (!DATA_TABLES(dce_info)) 798 return BP_RESULT_BADBIOSTABLE; 799 800 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 801 DATA_TABLES(dce_info)); 802 if (!disp_cntl_tbl) 803 return BP_RESULT_BADBIOSTABLE; 804 805 ss_info->type.STEP_AND_DELAY_INFO = false; 806 ss_info->spread_percentage_divider = 1000; 807 /* BIOS no longer uses target clock. Always enable for now */ 808 ss_info->target_clock_range = 0xffffffff; 809 810 switch (id) { 811 case AS_SIGNAL_TYPE_DVI: 812 ss_info->spread_spectrum_percentage = 813 disp_cntl_tbl->dvi_ss_percentage; 814 ss_info->spread_spectrum_range = 815 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 816 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 817 ss_info->type.CENTER_MODE = true; 818 break; 819 case AS_SIGNAL_TYPE_HDMI: 820 ss_info->spread_spectrum_percentage = 821 disp_cntl_tbl->hdmi_ss_percentage; 822 ss_info->spread_spectrum_range = 823 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 824 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 825 ss_info->type.CENTER_MODE = true; 826 break; 827 /* TODO LVDS not support anymore? */ 828 case AS_SIGNAL_TYPE_DISPLAY_PORT: 829 ss_info->spread_spectrum_percentage = 830 disp_cntl_tbl->dp_ss_percentage; 831 ss_info->spread_spectrum_range = 832 disp_cntl_tbl->dp_ss_rate_10hz * 10; 833 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 834 ss_info->type.CENTER_MODE = true; 835 break; 836 case AS_SIGNAL_TYPE_GPU_PLL: 837 /* atom_firmware: DAL only get data from dce_info table. 838 * if data within smu_info is needed for DAL, VBIOS should 839 * copy it into dce_info 840 */ 841 result = BP_RESULT_UNSUPPORTED; 842 break; 843 default: 844 result = BP_RESULT_UNSUPPORTED; 845 } 846 847 return result; 848 } 849 850 static enum bp_result get_ss_info_v4_2( 851 struct bios_parser *bp, 852 uint32_t id, 853 uint32_t index, 854 struct spread_spectrum_info *ss_info) 855 { 856 enum bp_result result = BP_RESULT_OK; 857 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 858 struct atom_smu_info_v3_1 *smu_info = NULL; 859 860 if (!ss_info) 861 return BP_RESULT_BADINPUT; 862 863 if (!DATA_TABLES(dce_info)) 864 return BP_RESULT_BADBIOSTABLE; 865 866 if (!DATA_TABLES(smu_info)) 867 return BP_RESULT_BADBIOSTABLE; 868 869 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 870 DATA_TABLES(dce_info)); 871 if (!disp_cntl_tbl) 872 return BP_RESULT_BADBIOSTABLE; 873 874 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 875 if (!smu_info) 876 return BP_RESULT_BADBIOSTABLE; 877 878 ss_info->type.STEP_AND_DELAY_INFO = false; 879 ss_info->spread_percentage_divider = 1000; 880 /* BIOS no longer uses target clock. Always enable for now */ 881 ss_info->target_clock_range = 0xffffffff; 882 883 switch (id) { 884 case AS_SIGNAL_TYPE_DVI: 885 ss_info->spread_spectrum_percentage = 886 disp_cntl_tbl->dvi_ss_percentage; 887 ss_info->spread_spectrum_range = 888 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 889 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 890 ss_info->type.CENTER_MODE = true; 891 break; 892 case AS_SIGNAL_TYPE_HDMI: 893 ss_info->spread_spectrum_percentage = 894 disp_cntl_tbl->hdmi_ss_percentage; 895 ss_info->spread_spectrum_range = 896 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 897 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 898 ss_info->type.CENTER_MODE = true; 899 break; 900 /* TODO LVDS not support anymore? */ 901 case AS_SIGNAL_TYPE_DISPLAY_PORT: 902 ss_info->spread_spectrum_percentage = 903 smu_info->gpuclk_ss_percentage; 904 ss_info->spread_spectrum_range = 905 smu_info->gpuclk_ss_rate_10hz * 10; 906 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 907 ss_info->type.CENTER_MODE = true; 908 break; 909 case AS_SIGNAL_TYPE_GPU_PLL: 910 /* atom_firmware: DAL only get data from dce_info table. 911 * if data within smu_info is needed for DAL, VBIOS should 912 * copy it into dce_info 913 */ 914 result = BP_RESULT_UNSUPPORTED; 915 break; 916 default: 917 result = BP_RESULT_UNSUPPORTED; 918 } 919 920 return result; 921 } 922 923 /** 924 * bios_parser_get_spread_spectrum_info 925 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 926 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 927 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 928 * ver 3.1, 929 * there is only one entry for each signal /ss id. However, there is 930 * no planning of supporting multiple spread Sprectum entry for EverGreen 931 * @param [in] this 932 * @param [in] signal, ASSignalType to be converted to info index 933 * @param [in] index, number of entries that match the converted info index 934 * @param [out] ss_info, sprectrum information structure, 935 * @return Bios parser result code 936 */ 937 static enum bp_result bios_parser_get_spread_spectrum_info( 938 struct dc_bios *dcb, 939 enum as_signal_type signal, 940 uint32_t index, 941 struct spread_spectrum_info *ss_info) 942 { 943 struct bios_parser *bp = BP_FROM_DCB(dcb); 944 enum bp_result result = BP_RESULT_UNSUPPORTED; 945 struct atom_common_table_header *header; 946 struct atom_data_revision tbl_revision; 947 948 if (!ss_info) /* check for bad input */ 949 return BP_RESULT_BADINPUT; 950 951 if (!DATA_TABLES(dce_info)) 952 return BP_RESULT_UNSUPPORTED; 953 954 header = GET_IMAGE(struct atom_common_table_header, 955 DATA_TABLES(dce_info)); 956 get_atom_data_table_revision(header, &tbl_revision); 957 958 switch (tbl_revision.major) { 959 case 4: 960 switch (tbl_revision.minor) { 961 case 1: 962 return get_ss_info_v4_1(bp, signal, index, ss_info); 963 case 2: 964 return get_ss_info_v4_2(bp, signal, index, ss_info); 965 default: 966 break; 967 } 968 break; 969 default: 970 break; 971 } 972 /* there can not be more then one entry for SS Info table */ 973 return result; 974 } 975 976 static enum bp_result get_embedded_panel_info_v2_1( 977 struct bios_parser *bp, 978 struct embedded_panel_info *info) 979 { 980 struct lcd_info_v2_1 *lvds; 981 982 if (!info) 983 return BP_RESULT_BADINPUT; 984 985 if (!DATA_TABLES(lcd_info)) 986 return BP_RESULT_UNSUPPORTED; 987 988 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 989 990 if (!lvds) 991 return BP_RESULT_BADBIOSTABLE; 992 993 /* TODO: previous vv1_3, should v2_1 */ 994 if (!((lvds->table_header.format_revision == 2) 995 && (lvds->table_header.content_revision >= 1))) 996 return BP_RESULT_UNSUPPORTED; 997 998 memset(info, 0, sizeof(struct embedded_panel_info)); 999 1000 /* We need to convert from 10KHz units into KHz units */ 1001 info->lcd_timing.pixel_clk = 1002 le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1003 /* usHActive does not include borders, according to VBIOS team */ 1004 info->lcd_timing.horizontal_addressable = 1005 le16_to_cpu(lvds->lcd_timing.h_active); 1006 /* usHBlanking_Time includes borders, so we should really be 1007 * subtractingborders duing this translation, but LVDS generally 1008 * doesn't have borders, so we should be okay leaving this as is for 1009 * now. May need to revisit if we ever have LVDS with borders 1010 */ 1011 info->lcd_timing.horizontal_blanking_time = 1012 le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1013 /* usVActive does not include borders, according to VBIOS team*/ 1014 info->lcd_timing.vertical_addressable = 1015 le16_to_cpu(lvds->lcd_timing.v_active); 1016 /* usVBlanking_Time includes borders, so we should really be 1017 * subtracting borders duing this translation, but LVDS generally 1018 * doesn't have borders, so we should be okay leaving this as is for 1019 * now. May need to revisit if we ever have LVDS with borders 1020 */ 1021 info->lcd_timing.vertical_blanking_time = 1022 le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1023 info->lcd_timing.horizontal_sync_offset = 1024 le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1025 info->lcd_timing.horizontal_sync_width = 1026 le16_to_cpu(lvds->lcd_timing.h_sync_width); 1027 info->lcd_timing.vertical_sync_offset = 1028 le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1029 info->lcd_timing.vertical_sync_width = 1030 le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1031 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1032 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1033 1034 /* not provided by VBIOS */ 1035 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1036 1037 info->lcd_timing.misc_info.H_SYNC_POLARITY = 1038 ~(uint32_t) 1039 (lvds->lcd_timing.miscinfo & ATOM_HSYNC_POLARITY); 1040 info->lcd_timing.misc_info.V_SYNC_POLARITY = 1041 ~(uint32_t) 1042 (lvds->lcd_timing.miscinfo & ATOM_VSYNC_POLARITY); 1043 1044 /* not provided by VBIOS */ 1045 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1046 1047 info->lcd_timing.misc_info.H_REPLICATION_BY2 = 1048 lvds->lcd_timing.miscinfo & ATOM_H_REPLICATIONBY2; 1049 info->lcd_timing.misc_info.V_REPLICATION_BY2 = 1050 lvds->lcd_timing.miscinfo & ATOM_V_REPLICATIONBY2; 1051 info->lcd_timing.misc_info.COMPOSITE_SYNC = 1052 lvds->lcd_timing.miscinfo & ATOM_COMPOSITESYNC; 1053 info->lcd_timing.misc_info.INTERLACE = 1054 lvds->lcd_timing.miscinfo & ATOM_INTERLACE; 1055 1056 /* not provided by VBIOS*/ 1057 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1058 /* not provided by VBIOS*/ 1059 info->ss_id = 0; 1060 1061 info->realtek_eDPToLVDS = 1062 (lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID ? 1:0); 1063 1064 return BP_RESULT_OK; 1065 } 1066 1067 static enum bp_result bios_parser_get_embedded_panel_info( 1068 struct dc_bios *dcb, 1069 struct embedded_panel_info *info) 1070 { 1071 struct bios_parser *bp = BP_FROM_DCB(dcb); 1072 struct atom_common_table_header *header; 1073 struct atom_data_revision tbl_revision; 1074 1075 if (!DATA_TABLES(lcd_info)) 1076 return BP_RESULT_FAILURE; 1077 1078 header = GET_IMAGE(struct atom_common_table_header, 1079 DATA_TABLES(lcd_info)); 1080 1081 if (!header) 1082 return BP_RESULT_BADBIOSTABLE; 1083 1084 get_atom_data_table_revision(header, &tbl_revision); 1085 1086 1087 switch (tbl_revision.major) { 1088 case 2: 1089 switch (tbl_revision.minor) { 1090 case 1: 1091 return get_embedded_panel_info_v2_1(bp, info); 1092 default: 1093 break; 1094 } 1095 default: 1096 break; 1097 } 1098 1099 return BP_RESULT_FAILURE; 1100 } 1101 1102 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1103 { 1104 enum dal_device_type device_type = device_id.device_type; 1105 uint32_t enum_id = device_id.enum_id; 1106 1107 switch (device_type) { 1108 case DEVICE_TYPE_LCD: 1109 switch (enum_id) { 1110 case 1: 1111 return ATOM_DISPLAY_LCD1_SUPPORT; 1112 default: 1113 break; 1114 } 1115 break; 1116 case DEVICE_TYPE_DFP: 1117 switch (enum_id) { 1118 case 1: 1119 return ATOM_DISPLAY_DFP1_SUPPORT; 1120 case 2: 1121 return ATOM_DISPLAY_DFP2_SUPPORT; 1122 case 3: 1123 return ATOM_DISPLAY_DFP3_SUPPORT; 1124 case 4: 1125 return ATOM_DISPLAY_DFP4_SUPPORT; 1126 case 5: 1127 return ATOM_DISPLAY_DFP5_SUPPORT; 1128 case 6: 1129 return ATOM_DISPLAY_DFP6_SUPPORT; 1130 default: 1131 break; 1132 } 1133 break; 1134 default: 1135 break; 1136 }; 1137 1138 /* Unidentified device ID, return empty support mask. */ 1139 return 0; 1140 } 1141 1142 static bool bios_parser_is_device_id_supported( 1143 struct dc_bios *dcb, 1144 struct device_id id) 1145 { 1146 struct bios_parser *bp = BP_FROM_DCB(dcb); 1147 1148 uint32_t mask = get_support_mask_for_device_id(id); 1149 1150 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1151 mask) != 0; 1152 } 1153 1154 static void bios_parser_post_init( 1155 struct dc_bios *dcb) 1156 { 1157 /* TODO for OPM module. Need implement later */ 1158 } 1159 1160 static uint32_t bios_parser_get_ss_entry_number( 1161 struct dc_bios *dcb, 1162 enum as_signal_type signal) 1163 { 1164 /* TODO: DAL2 atomfirmware implementation does not need this. 1165 * why DAL3 need this? 1166 */ 1167 return 1; 1168 } 1169 1170 static enum bp_result bios_parser_transmitter_control( 1171 struct dc_bios *dcb, 1172 struct bp_transmitter_control *cntl) 1173 { 1174 struct bios_parser *bp = BP_FROM_DCB(dcb); 1175 1176 if (!bp->cmd_tbl.transmitter_control) 1177 return BP_RESULT_FAILURE; 1178 1179 return bp->cmd_tbl.transmitter_control(bp, cntl); 1180 } 1181 1182 static enum bp_result bios_parser_encoder_control( 1183 struct dc_bios *dcb, 1184 struct bp_encoder_control *cntl) 1185 { 1186 struct bios_parser *bp = BP_FROM_DCB(dcb); 1187 1188 if (!bp->cmd_tbl.dig_encoder_control) 1189 return BP_RESULT_FAILURE; 1190 1191 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1192 } 1193 1194 static enum bp_result bios_parser_set_pixel_clock( 1195 struct dc_bios *dcb, 1196 struct bp_pixel_clock_parameters *bp_params) 1197 { 1198 struct bios_parser *bp = BP_FROM_DCB(dcb); 1199 1200 if (!bp->cmd_tbl.set_pixel_clock) 1201 return BP_RESULT_FAILURE; 1202 1203 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1204 } 1205 1206 static enum bp_result bios_parser_set_dce_clock( 1207 struct dc_bios *dcb, 1208 struct bp_set_dce_clock_parameters *bp_params) 1209 { 1210 struct bios_parser *bp = BP_FROM_DCB(dcb); 1211 1212 if (!bp->cmd_tbl.set_dce_clock) 1213 return BP_RESULT_FAILURE; 1214 1215 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1216 } 1217 1218 static unsigned int bios_parser_get_smu_clock_info( 1219 struct dc_bios *dcb) 1220 { 1221 struct bios_parser *bp = BP_FROM_DCB(dcb); 1222 1223 if (!bp->cmd_tbl.get_smu_clock_info) 1224 return BP_RESULT_FAILURE; 1225 1226 return bp->cmd_tbl.get_smu_clock_info(bp); 1227 } 1228 1229 static enum bp_result bios_parser_program_crtc_timing( 1230 struct dc_bios *dcb, 1231 struct bp_hw_crtc_timing_parameters *bp_params) 1232 { 1233 struct bios_parser *bp = BP_FROM_DCB(dcb); 1234 1235 if (!bp->cmd_tbl.set_crtc_timing) 1236 return BP_RESULT_FAILURE; 1237 1238 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1239 } 1240 1241 static enum bp_result bios_parser_enable_crtc( 1242 struct dc_bios *dcb, 1243 enum controller_id id, 1244 bool enable) 1245 { 1246 struct bios_parser *bp = BP_FROM_DCB(dcb); 1247 1248 if (!bp->cmd_tbl.enable_crtc) 1249 return BP_RESULT_FAILURE; 1250 1251 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1252 } 1253 1254 static enum bp_result bios_parser_crtc_source_select( 1255 struct dc_bios *dcb, 1256 struct bp_crtc_source_select *bp_params) 1257 { 1258 struct bios_parser *bp = BP_FROM_DCB(dcb); 1259 1260 if (!bp->cmd_tbl.select_crtc_source) 1261 return BP_RESULT_FAILURE; 1262 1263 return bp->cmd_tbl.select_crtc_source(bp, bp_params); 1264 } 1265 1266 static enum bp_result bios_parser_enable_disp_power_gating( 1267 struct dc_bios *dcb, 1268 enum controller_id controller_id, 1269 enum bp_pipe_control_action action) 1270 { 1271 struct bios_parser *bp = BP_FROM_DCB(dcb); 1272 1273 if (!bp->cmd_tbl.enable_disp_power_gating) 1274 return BP_RESULT_FAILURE; 1275 1276 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1277 action); 1278 } 1279 1280 static bool bios_parser_is_accelerated_mode( 1281 struct dc_bios *dcb) 1282 { 1283 return bios_is_accelerated_mode(dcb); 1284 } 1285 1286 1287 /** 1288 * bios_parser_set_scratch_critical_state 1289 * 1290 * @brief 1291 * update critical state bit in VBIOS scratch register 1292 * 1293 * @param 1294 * bool - to set or reset state 1295 */ 1296 static void bios_parser_set_scratch_critical_state( 1297 struct dc_bios *dcb, 1298 bool state) 1299 { 1300 bios_set_scratch_critical_state(dcb, state); 1301 } 1302 1303 static enum bp_result bios_parser_get_firmware_info( 1304 struct dc_bios *dcb, 1305 struct dc_firmware_info *info) 1306 { 1307 struct bios_parser *bp = BP_FROM_DCB(dcb); 1308 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1309 struct atom_common_table_header *header; 1310 1311 struct atom_data_revision revision; 1312 1313 if (info && DATA_TABLES(firmwareinfo)) { 1314 header = GET_IMAGE(struct atom_common_table_header, 1315 DATA_TABLES(firmwareinfo)); 1316 get_atom_data_table_revision(header, &revision); 1317 switch (revision.major) { 1318 case 3: 1319 switch (revision.minor) { 1320 case 1: 1321 result = get_firmware_info_v3_1(bp, info); 1322 break; 1323 default: 1324 break; 1325 } 1326 break; 1327 default: 1328 break; 1329 } 1330 } 1331 1332 return result; 1333 } 1334 1335 static enum bp_result get_firmware_info_v3_1( 1336 struct bios_parser *bp, 1337 struct dc_firmware_info *info) 1338 { 1339 struct atom_firmware_info_v3_1 *firmware_info; 1340 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1341 1342 if (!info) 1343 return BP_RESULT_BADINPUT; 1344 1345 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1346 DATA_TABLES(firmwareinfo)); 1347 1348 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1349 DATA_TABLES(dce_info)); 1350 1351 if (!firmware_info || !dce_info) 1352 return BP_RESULT_BADBIOSTABLE; 1353 1354 memset(info, 0, sizeof(*info)); 1355 1356 /* Pixel clock pll information. */ 1357 /* We need to convert from 10KHz units into KHz units */ 1358 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1359 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1360 1361 /* 27MHz for Vega10: */ 1362 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1363 1364 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1365 if (info->pll_info.crystal_frequency == 0) 1366 info->pll_info.crystal_frequency = 27000; 1367 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1368 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1369 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1370 1371 /* Get GPU PLL VCO Clock */ 1372 1373 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1374 /* VBIOS gives in 10KHz */ 1375 info->smu_gpu_pll_output_freq = 1376 bp->cmd_tbl.get_smu_clock_info(bp) * 10; 1377 } 1378 1379 return BP_RESULT_OK; 1380 } 1381 1382 static enum bp_result bios_parser_get_encoder_cap_info( 1383 struct dc_bios *dcb, 1384 struct graphics_object_id object_id, 1385 struct bp_encoder_cap_info *info) 1386 { 1387 struct bios_parser *bp = BP_FROM_DCB(dcb); 1388 struct atom_display_object_path_v2 *object; 1389 struct atom_encoder_caps_record *record = NULL; 1390 1391 if (!info) 1392 return BP_RESULT_BADINPUT; 1393 1394 object = get_bios_object(bp, object_id); 1395 1396 if (!object) 1397 return BP_RESULT_BADINPUT; 1398 1399 record = get_encoder_cap_record(bp, object); 1400 if (!record) 1401 return BP_RESULT_NORECORD; 1402 1403 info->DP_HBR2_CAP = (record->encodercaps & 1404 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1405 info->DP_HBR2_EN = (record->encodercaps & 1406 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1407 info->DP_HBR3_EN = (record->encodercaps & 1408 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1409 info->HDMI_6GB_EN = (record->encodercaps & 1410 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1411 1412 return BP_RESULT_OK; 1413 } 1414 1415 1416 static struct atom_encoder_caps_record *get_encoder_cap_record( 1417 struct bios_parser *bp, 1418 struct atom_display_object_path_v2 *object) 1419 { 1420 struct atom_common_record_header *header; 1421 uint32_t offset; 1422 1423 if (!object) { 1424 BREAK_TO_DEBUGGER(); /* Invalid object */ 1425 return NULL; 1426 } 1427 1428 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1429 1430 for (;;) { 1431 header = GET_IMAGE(struct atom_common_record_header, offset); 1432 1433 if (!header) 1434 return NULL; 1435 1436 offset += header->record_size; 1437 1438 if (header->record_type == LAST_RECORD_TYPE || 1439 !header->record_size) 1440 break; 1441 1442 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1443 continue; 1444 1445 if (sizeof(struct atom_encoder_caps_record) <= 1446 header->record_size) 1447 return (struct atom_encoder_caps_record *)header; 1448 } 1449 1450 return NULL; 1451 } 1452 1453 /* 1454 * get_integrated_info_v11 1455 * 1456 * @brief 1457 * Get V8 integrated BIOS information 1458 * 1459 * @param 1460 * bios_parser *bp - [in]BIOS parser handler to get master data table 1461 * integrated_info *info - [out] store and output integrated info 1462 * 1463 * @return 1464 * enum bp_result - BP_RESULT_OK if information is available, 1465 * BP_RESULT_BADBIOSTABLE otherwise. 1466 */ 1467 static enum bp_result get_integrated_info_v11( 1468 struct bios_parser *bp, 1469 struct integrated_info *info) 1470 { 1471 struct atom_integrated_system_info_v1_11 *info_v11; 1472 uint32_t i; 1473 1474 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1475 DATA_TABLES(integratedsysteminfo)); 1476 1477 if (info_v11 == NULL) 1478 return BP_RESULT_BADBIOSTABLE; 1479 1480 info->gpu_cap_info = 1481 le32_to_cpu(info_v11->gpucapinfo); 1482 /* 1483 * system_config: Bit[0] = 0 : PCIE power gating disabled 1484 * = 1 : PCIE power gating enabled 1485 * Bit[1] = 0 : DDR-PLL shut down disabled 1486 * = 1 : DDR-PLL shut down enabled 1487 * Bit[2] = 0 : DDR-PLL power down disabled 1488 * = 1 : DDR-PLL power down enabled 1489 */ 1490 info->system_config = le32_to_cpu(info_v11->system_config); 1491 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1492 info->memory_type = info_v11->memorytype; 1493 info->ma_channel_number = info_v11->umachannelnumber; 1494 info->lvds_ss_percentage = 1495 le16_to_cpu(info_v11->lvds_ss_percentage); 1496 info->lvds_sspread_rate_in_10hz = 1497 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1498 info->hdmi_ss_percentage = 1499 le16_to_cpu(info_v11->hdmi_ss_percentage); 1500 info->hdmi_sspread_rate_in_10hz = 1501 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1502 info->dvi_ss_percentage = 1503 le16_to_cpu(info_v11->dvi_ss_percentage); 1504 info->dvi_sspread_rate_in_10_hz = 1505 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1506 info->lvds_misc = info_v11->lvds_misc; 1507 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1508 info->ext_disp_conn_info.gu_id[i] = 1509 info_v11->extdispconninfo.guid[i]; 1510 } 1511 1512 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1513 info->ext_disp_conn_info.path[i].device_connector_id = 1514 object_id_from_bios_object_id( 1515 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1516 1517 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1518 object_id_from_bios_object_id( 1519 le16_to_cpu( 1520 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1521 1522 info->ext_disp_conn_info.path[i].device_tag = 1523 le16_to_cpu( 1524 info_v11->extdispconninfo.path[i].device_tag); 1525 info->ext_disp_conn_info.path[i].device_acpi_enum = 1526 le16_to_cpu( 1527 info_v11->extdispconninfo.path[i].device_acpi_enum); 1528 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1529 info_v11->extdispconninfo.path[i].auxddclut_index; 1530 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1531 info_v11->extdispconninfo.path[i].hpdlut_index; 1532 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1533 info_v11->extdispconninfo.path[i].channelmapping; 1534 info->ext_disp_conn_info.path[i].caps = 1535 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1536 } 1537 info->ext_disp_conn_info.checksum = 1538 info_v11->extdispconninfo.checksum; 1539 1540 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1541 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1542 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1543 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1544 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1545 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1546 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1547 } 1548 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1549 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1550 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1551 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1552 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1553 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1554 } 1555 1556 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1557 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1558 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1559 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1560 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1561 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1562 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1563 } 1564 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1565 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1566 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1567 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1568 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1569 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1570 } 1571 1572 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1573 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1574 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1575 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1576 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1577 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1578 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1579 } 1580 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1581 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1582 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1583 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1584 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1585 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1586 } 1587 1588 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1589 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1590 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1591 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1592 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1593 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1594 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1595 } 1596 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1597 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1598 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1599 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1600 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1601 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1602 } 1603 1604 1605 /** TODO - review **/ 1606 #if 0 1607 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1608 * 10; 1609 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1610 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1611 1612 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1613 /* Convert [10KHz] into [KHz] */ 1614 info->disp_clk_voltage[i].max_supported_clk = 1615 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1616 ulMaximumSupportedCLK) * 10; 1617 info->disp_clk_voltage[i].voltage_index = 1618 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1619 } 1620 1621 info->boot_up_req_display_vector = 1622 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1623 info->boot_up_nb_voltage = 1624 le16_to_cpu(info_v11->usBootUpNBVoltage); 1625 info->ext_disp_conn_info_offset = 1626 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1627 info->gmc_restore_reset_time = 1628 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1629 info->minimum_n_clk = 1630 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1631 for (i = 1; i < 4; ++i) 1632 info->minimum_n_clk = 1633 info->minimum_n_clk < 1634 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1635 info->minimum_n_clk : le32_to_cpu( 1636 info_v11->ulNbpStateNClkFreq[i]); 1637 1638 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1639 info->ddr_dll_power_up_time = 1640 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1641 info->ddr_pll_power_up_time = 1642 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1643 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1644 info->max_lvds_pclk_freq_in_single_link = 1645 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1646 info->max_lvds_pclk_freq_in_single_link = 1647 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1648 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1649 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1650 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1651 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1652 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1653 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1654 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1655 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1656 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1657 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1658 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1659 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1660 info->lvds_off_to_on_delay_in_4ms = 1661 info_v11->ucLVDSOffToOnDelay_in4Ms; 1662 info->lvds_bit_depth_control_val = 1663 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1664 1665 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1666 /* Convert [10KHz] into [KHz] */ 1667 info->avail_s_clk[i].supported_s_clk = 1668 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1669 * 10; 1670 info->avail_s_clk[i].voltage_index = 1671 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1672 info->avail_s_clk[i].voltage_id = 1673 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1674 } 1675 #endif /* TODO*/ 1676 1677 return BP_RESULT_OK; 1678 } 1679 1680 1681 /* 1682 * construct_integrated_info 1683 * 1684 * @brief 1685 * Get integrated BIOS information based on table revision 1686 * 1687 * @param 1688 * bios_parser *bp - [in]BIOS parser handler to get master data table 1689 * integrated_info *info - [out] store and output integrated info 1690 * 1691 * @return 1692 * enum bp_result - BP_RESULT_OK if information is available, 1693 * BP_RESULT_BADBIOSTABLE otherwise. 1694 */ 1695 static enum bp_result construct_integrated_info( 1696 struct bios_parser *bp, 1697 struct integrated_info *info) 1698 { 1699 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1700 1701 struct atom_common_table_header *header; 1702 struct atom_data_revision revision; 1703 1704 struct clock_voltage_caps temp = {0, 0}; 1705 uint32_t i; 1706 uint32_t j; 1707 1708 if (info && DATA_TABLES(integratedsysteminfo)) { 1709 header = GET_IMAGE(struct atom_common_table_header, 1710 DATA_TABLES(integratedsysteminfo)); 1711 1712 get_atom_data_table_revision(header, &revision); 1713 1714 /* Don't need to check major revision as they are all 1 */ 1715 switch (revision.minor) { 1716 case 11: 1717 result = get_integrated_info_v11(bp, info); 1718 break; 1719 default: 1720 return result; 1721 } 1722 } 1723 1724 if (result != BP_RESULT_OK) 1725 return result; 1726 1727 /* Sort voltage table from low to high*/ 1728 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1729 for (j = i; j > 0; --j) { 1730 if (info->disp_clk_voltage[j].max_supported_clk < 1731 info->disp_clk_voltage[j-1].max_supported_clk 1732 ) { 1733 /* swap j and j - 1*/ 1734 temp = info->disp_clk_voltage[j-1]; 1735 info->disp_clk_voltage[j-1] = 1736 info->disp_clk_voltage[j]; 1737 info->disp_clk_voltage[j] = temp; 1738 } 1739 } 1740 } 1741 1742 return result; 1743 } 1744 1745 static struct integrated_info *bios_parser_create_integrated_info( 1746 struct dc_bios *dcb) 1747 { 1748 struct bios_parser *bp = BP_FROM_DCB(dcb); 1749 struct integrated_info *info = NULL; 1750 1751 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 1752 1753 if (info == NULL) { 1754 ASSERT_CRITICAL(0); 1755 return NULL; 1756 } 1757 1758 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 1759 return info; 1760 1761 kfree(info); 1762 1763 return NULL; 1764 } 1765 1766 static const struct dc_vbios_funcs vbios_funcs = { 1767 .get_connectors_number = bios_parser_get_connectors_number, 1768 1769 .get_encoder_id = bios_parser_get_encoder_id, 1770 1771 .get_connector_id = bios_parser_get_connector_id, 1772 1773 .get_dst_number = bios_parser_get_dst_number, 1774 1775 .get_src_obj = bios_parser_get_src_obj, 1776 1777 .get_dst_obj = bios_parser_get_dst_obj, 1778 1779 .get_i2c_info = bios_parser_get_i2c_info, 1780 1781 .get_voltage_ddc_info = bios_parser_get_voltage_ddc_info, 1782 1783 .get_thermal_ddc_info = bios_parser_get_thermal_ddc_info, 1784 1785 .get_hpd_info = bios_parser_get_hpd_info, 1786 1787 .get_device_tag = bios_parser_get_device_tag, 1788 1789 .get_firmware_info = bios_parser_get_firmware_info, 1790 1791 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 1792 1793 .get_ss_entry_number = bios_parser_get_ss_entry_number, 1794 1795 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 1796 1797 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 1798 1799 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 1800 1801 .is_device_id_supported = bios_parser_is_device_id_supported, 1802 1803 1804 1805 .is_accelerated_mode = bios_parser_is_accelerated_mode, 1806 1807 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 1808 1809 1810 /* COMMANDS */ 1811 .encoder_control = bios_parser_encoder_control, 1812 1813 .transmitter_control = bios_parser_transmitter_control, 1814 1815 .enable_crtc = bios_parser_enable_crtc, 1816 1817 .set_pixel_clock = bios_parser_set_pixel_clock, 1818 1819 .set_dce_clock = bios_parser_set_dce_clock, 1820 1821 .program_crtc_timing = bios_parser_program_crtc_timing, 1822 1823 /* .blank_crtc = bios_parser_blank_crtc, */ 1824 1825 .crtc_source_select = bios_parser_crtc_source_select, 1826 1827 /* .external_encoder_control = bios_parser_external_encoder_control, */ 1828 1829 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 1830 1831 .post_init = bios_parser_post_init, 1832 1833 .bios_parser_destroy = firmware_parser_destroy, 1834 1835 .get_smu_clock_info = bios_parser_get_smu_clock_info, 1836 }; 1837 1838 static bool bios_parser_construct( 1839 struct bios_parser *bp, 1840 struct bp_init_data *init, 1841 enum dce_version dce_version) 1842 { 1843 uint16_t *rom_header_offset = NULL; 1844 struct atom_rom_header_v2_2 *rom_header = NULL; 1845 struct display_object_info_table_v1_4 *object_info_tbl; 1846 struct atom_data_revision tbl_rev = {0}; 1847 1848 if (!init) 1849 return false; 1850 1851 if (!init->bios) 1852 return false; 1853 1854 bp->base.funcs = &vbios_funcs; 1855 bp->base.bios = init->bios; 1856 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 1857 1858 bp->base.ctx = init->ctx; 1859 1860 bp->base.bios_local_image = NULL; 1861 1862 rom_header_offset = 1863 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 1864 1865 if (!rom_header_offset) 1866 return false; 1867 1868 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 1869 1870 if (!rom_header) 1871 return false; 1872 1873 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 1874 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 1875 return false; 1876 1877 bp->master_data_tbl = 1878 GET_IMAGE(struct atom_master_data_table_v2_1, 1879 rom_header->masterdatatable_offset); 1880 1881 if (!bp->master_data_tbl) 1882 return false; 1883 1884 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 1885 1886 if (!bp->object_info_tbl_offset) 1887 return false; 1888 1889 object_info_tbl = 1890 GET_IMAGE(struct display_object_info_table_v1_4, 1891 bp->object_info_tbl_offset); 1892 1893 if (!object_info_tbl) 1894 return false; 1895 1896 get_atom_data_table_revision(&object_info_tbl->table_header, 1897 &bp->object_info_tbl.revision); 1898 1899 if (bp->object_info_tbl.revision.major == 1 1900 && bp->object_info_tbl.revision.minor >= 4) { 1901 struct display_object_info_table_v1_4 *tbl_v1_4; 1902 1903 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 1904 bp->object_info_tbl_offset); 1905 if (!tbl_v1_4) 1906 return false; 1907 1908 bp->object_info_tbl.v1_4 = tbl_v1_4; 1909 } else 1910 return false; 1911 1912 dal_firmware_parser_init_cmd_tbl(bp); 1913 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 1914 1915 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 1916 1917 return true; 1918 } 1919 1920 struct dc_bios *firmware_parser_create( 1921 struct bp_init_data *init, 1922 enum dce_version dce_version) 1923 { 1924 struct bios_parser *bp = NULL; 1925 1926 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 1927 if (!bp) 1928 return NULL; 1929 1930 if (bios_parser_construct(bp, init, dce_version)) 1931 return &bp->base; 1932 1933 kfree(bp); 1934 return NULL; 1935 } 1936 1937 1938