1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static enum bp_result get_firmware_info_v3_4( 103 struct bios_parser *bp, 104 struct dc_firmware_info *info); 105 106 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 static struct atom_encoder_caps_record *get_encoder_cap_record( 110 struct bios_parser *bp, 111 struct atom_display_object_path_v2 *object); 112 113 #define BIOS_IMAGE_SIZE_OFFSET 2 114 #define BIOS_IMAGE_SIZE_UNIT 512 115 116 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 117 118 static void bios_parser2_destruct(struct bios_parser *bp) 119 { 120 kfree(bp->base.bios_local_image); 121 kfree(bp->base.integrated_info); 122 } 123 124 static void firmware_parser_destroy(struct dc_bios **dcb) 125 { 126 struct bios_parser *bp = BP_FROM_DCB(*dcb); 127 128 if (!bp) { 129 BREAK_TO_DEBUGGER(); 130 return; 131 } 132 133 bios_parser2_destruct(bp); 134 135 kfree(bp); 136 *dcb = NULL; 137 } 138 139 static void get_atom_data_table_revision( 140 struct atom_common_table_header *atom_data_tbl, 141 struct atom_data_revision *tbl_revision) 142 { 143 if (!tbl_revision) 144 return; 145 146 /* initialize the revision to 0 which is invalid revision */ 147 tbl_revision->major = 0; 148 tbl_revision->minor = 0; 149 150 if (!atom_data_tbl) 151 return; 152 153 tbl_revision->major = 154 (uint32_t) atom_data_tbl->format_revision & 0x3f; 155 tbl_revision->minor = 156 (uint32_t) atom_data_tbl->content_revision & 0x3f; 157 } 158 159 /* BIOS oject table displaypath is per connector. 160 * There is extra path not for connector. BIOS fill its encoderid as 0 161 */ 162 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 163 { 164 struct bios_parser *bp = BP_FROM_DCB(dcb); 165 unsigned int count = 0; 166 unsigned int i; 167 168 switch (bp->object_info_tbl.revision.minor) { 169 default: 170 case 4: 171 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 172 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 173 count++; 174 175 break; 176 177 case 5: 178 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 179 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 180 count++; 181 182 break; 183 } 184 return count; 185 } 186 187 static struct graphics_object_id bios_parser_get_connector_id( 188 struct dc_bios *dcb, 189 uint8_t i) 190 { 191 struct bios_parser *bp = BP_FROM_DCB(dcb); 192 struct graphics_object_id object_id = dal_graphics_object_id_init( 193 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 194 struct object_info_table *tbl = &bp->object_info_tbl; 195 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 196 197 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 198 199 switch (bp->object_info_tbl.revision.minor) { 200 default: 201 case 4: 202 if (v1_4->number_of_path > i) { 203 /* If display_objid is generic object id, the encoderObj 204 * /extencoderobjId should be 0 205 */ 206 if (v1_4->display_path[i].encoderobjid != 0 && 207 v1_4->display_path[i].display_objid != 0) 208 object_id = object_id_from_bios_object_id( 209 v1_4->display_path[i].display_objid); 210 } 211 break; 212 213 case 5: 214 if (v1_5->number_of_path > i) { 215 /* If display_objid is generic object id, the encoderObjId 216 * should be 0 217 */ 218 if (v1_5->display_path[i].encoderobjid != 0 && 219 v1_5->display_path[i].display_objid != 0) 220 object_id = object_id_from_bios_object_id( 221 v1_5->display_path[i].display_objid); 222 } 223 break; 224 } 225 return object_id; 226 } 227 228 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 229 struct graphics_object_id object_id, uint32_t index, 230 struct graphics_object_id *src_object_id) 231 { 232 struct bios_parser *bp = BP_FROM_DCB(dcb); 233 unsigned int i; 234 enum bp_result bp_result = BP_RESULT_BADINPUT; 235 struct graphics_object_id obj_id = { 0 }; 236 struct object_info_table *tbl = &bp->object_info_tbl; 237 238 if (!src_object_id) 239 return bp_result; 240 241 switch (object_id.type) { 242 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 243 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 244 */ 245 case OBJECT_TYPE_ENCODER: 246 /* TODO: since num of src must be less than 2. 247 * If found in for loop, should break. 248 * DAL2 implementation may be changed too 249 */ 250 switch (bp->object_info_tbl.revision.minor) { 251 default: 252 case 4: 253 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 254 obj_id = object_id_from_bios_object_id( 255 tbl->v1_4->display_path[i].encoderobjid); 256 if (object_id.type == obj_id.type && 257 object_id.id == obj_id.id && 258 object_id.enum_id == obj_id.enum_id) { 259 *src_object_id = 260 object_id_from_bios_object_id( 261 0x1100); 262 /* break; */ 263 } 264 } 265 bp_result = BP_RESULT_OK; 266 break; 267 268 case 5: 269 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 270 obj_id = object_id_from_bios_object_id( 271 tbl->v1_5->display_path[i].encoderobjid); 272 if (object_id.type == obj_id.type && 273 object_id.id == obj_id.id && 274 object_id.enum_id == obj_id.enum_id) { 275 *src_object_id = 276 object_id_from_bios_object_id( 277 0x1100); 278 /* break; */ 279 } 280 } 281 bp_result = BP_RESULT_OK; 282 break; 283 } 284 break; 285 case OBJECT_TYPE_CONNECTOR: 286 switch (bp->object_info_tbl.revision.minor) { 287 default: 288 case 4: 289 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 290 obj_id = object_id_from_bios_object_id( 291 tbl->v1_4->display_path[i] 292 .display_objid); 293 294 if (object_id.type == obj_id.type && 295 object_id.id == obj_id.id && 296 object_id.enum_id == obj_id.enum_id) { 297 *src_object_id = 298 object_id_from_bios_object_id( 299 tbl->v1_4 300 ->display_path[i] 301 .encoderobjid); 302 /* break; */ 303 } 304 } 305 bp_result = BP_RESULT_OK; 306 break; 307 } 308 bp_result = BP_RESULT_OK; 309 break; 310 case 5: 311 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 312 obj_id = object_id_from_bios_object_id( 313 tbl->v1_5->display_path[i].display_objid); 314 315 if (object_id.type == obj_id.type && 316 object_id.id == obj_id.id && 317 object_id.enum_id == obj_id.enum_id) { 318 *src_object_id = object_id_from_bios_object_id( 319 tbl->v1_5->display_path[i].encoderobjid); 320 /* break; */ 321 } 322 } 323 bp_result = BP_RESULT_OK; 324 break; 325 326 default: 327 bp_result = BP_RESULT_OK; 328 break; 329 } 330 331 return bp_result; 332 } 333 334 /* from graphics_object_id, find display path which includes the object_id */ 335 static struct atom_display_object_path_v2 *get_bios_object( 336 struct bios_parser *bp, 337 struct graphics_object_id id) 338 { 339 unsigned int i; 340 struct graphics_object_id obj_id = {0}; 341 342 switch (id.type) { 343 case OBJECT_TYPE_ENCODER: 344 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 345 obj_id = object_id_from_bios_object_id( 346 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 347 if (id.type == obj_id.type && id.id == obj_id.id 348 && id.enum_id == obj_id.enum_id) 349 return &bp->object_info_tbl.v1_4->display_path[i]; 350 } 351 fallthrough; 352 case OBJECT_TYPE_CONNECTOR: 353 case OBJECT_TYPE_GENERIC: 354 /* Both Generic and Connector Object ID 355 * will be stored on display_objid 356 */ 357 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 358 obj_id = object_id_from_bios_object_id( 359 bp->object_info_tbl.v1_4->display_path[i].display_objid); 360 if (id.type == obj_id.type && id.id == obj_id.id 361 && id.enum_id == obj_id.enum_id) 362 return &bp->object_info_tbl.v1_4->display_path[i]; 363 } 364 fallthrough; 365 default: 366 return NULL; 367 } 368 } 369 370 /* from graphics_object_id, find display path which includes the object_id */ 371 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( 372 struct bios_parser *bp, 373 struct graphics_object_id id) 374 { 375 unsigned int i; 376 struct graphics_object_id obj_id = {0}; 377 378 switch (id.type) { 379 case OBJECT_TYPE_ENCODER: 380 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 381 obj_id = object_id_from_bios_object_id( 382 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 383 if (id.type == obj_id.type && id.id == obj_id.id 384 && id.enum_id == obj_id.enum_id) 385 return &bp->object_info_tbl.v1_5->display_path[i]; 386 } 387 break; 388 389 case OBJECT_TYPE_CONNECTOR: 390 case OBJECT_TYPE_GENERIC: 391 /* Both Generic and Connector Object ID 392 * will be stored on display_objid 393 */ 394 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 395 obj_id = object_id_from_bios_object_id( 396 bp->object_info_tbl.v1_5->display_path[i].display_objid); 397 if (id.type == obj_id.type && id.id == obj_id.id 398 && id.enum_id == obj_id.enum_id) 399 return &bp->object_info_tbl.v1_5->display_path[i]; 400 } 401 break; 402 403 default: 404 return NULL; 405 } 406 407 return NULL; 408 } 409 410 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 411 struct graphics_object_id id, 412 struct graphics_object_i2c_info *info) 413 { 414 uint32_t offset; 415 struct atom_display_object_path_v2 *object; 416 417 struct atom_display_object_path_v3 *object_path_v3; 418 419 struct atom_common_record_header *header; 420 struct atom_i2c_record *record; 421 struct atom_i2c_record dummy_record = {0}; 422 struct bios_parser *bp = BP_FROM_DCB(dcb); 423 424 if (!info) 425 return BP_RESULT_BADINPUT; 426 427 if (id.type == OBJECT_TYPE_GENERIC) { 428 dummy_record.i2c_id = id.id; 429 430 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 431 return BP_RESULT_OK; 432 else 433 return BP_RESULT_NORECORD; 434 } 435 436 switch (bp->object_info_tbl.revision.minor) { 437 case 4: 438 default: 439 object = get_bios_object(bp, id); 440 441 if (!object) 442 return BP_RESULT_BADINPUT; 443 444 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 445 break; 446 case 5: 447 object_path_v3 = get_bios_object_from_path_v3(bp, id); 448 449 if (!object_path_v3) 450 return BP_RESULT_BADINPUT; 451 452 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 453 break; 454 } 455 456 for (;;) { 457 header = GET_IMAGE(struct atom_common_record_header, offset); 458 459 if (!header) 460 return BP_RESULT_BADBIOSTABLE; 461 462 if (header->record_type == LAST_RECORD_TYPE || 463 !header->record_size) 464 break; 465 466 if (header->record_type == ATOM_I2C_RECORD_TYPE 467 && sizeof(struct atom_i2c_record) <= 468 header->record_size) { 469 /* get the I2C info */ 470 record = (struct atom_i2c_record *) header; 471 472 if (get_gpio_i2c_info(bp, record, info) == 473 BP_RESULT_OK) 474 return BP_RESULT_OK; 475 } 476 477 offset += header->record_size; 478 } 479 480 return BP_RESULT_NORECORD; 481 } 482 483 static enum bp_result get_gpio_i2c_info( 484 struct bios_parser *bp, 485 struct atom_i2c_record *record, 486 struct graphics_object_i2c_info *info) 487 { 488 struct atom_gpio_pin_lut_v2_1 *header; 489 uint32_t count = 0; 490 unsigned int table_index = 0; 491 bool find_valid = false; 492 493 if (!info) 494 return BP_RESULT_BADINPUT; 495 496 /* get the GPIO_I2C info */ 497 if (!DATA_TABLES(gpio_pin_lut)) 498 return BP_RESULT_BADBIOSTABLE; 499 500 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 501 DATA_TABLES(gpio_pin_lut)); 502 if (!header) 503 return BP_RESULT_BADBIOSTABLE; 504 505 if (sizeof(struct atom_common_table_header) + 506 sizeof(struct atom_gpio_pin_assignment) > 507 le16_to_cpu(header->table_header.structuresize)) 508 return BP_RESULT_BADBIOSTABLE; 509 510 /* TODO: is version change? */ 511 if (header->table_header.content_revision != 1) 512 return BP_RESULT_UNSUPPORTED; 513 514 /* get data count */ 515 count = (le16_to_cpu(header->table_header.structuresize) 516 - sizeof(struct atom_common_table_header)) 517 / sizeof(struct atom_gpio_pin_assignment); 518 519 for (table_index = 0; table_index < count; table_index++) { 520 if (((record->i2c_id & I2C_HW_CAP) == ( 521 header->gpio_pin[table_index].gpio_id & 522 I2C_HW_CAP)) && 523 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 524 (header->gpio_pin[table_index].gpio_id & 525 I2C_HW_ENGINE_ID_MASK)) && 526 ((record->i2c_id & I2C_HW_LANE_MUX) == 527 (header->gpio_pin[table_index].gpio_id & 528 I2C_HW_LANE_MUX))) { 529 /* still valid */ 530 find_valid = true; 531 break; 532 } 533 } 534 535 /* If we don't find the entry that we are looking for then 536 * we will return BP_Result_BadBiosTable. 537 */ 538 if (find_valid == false) 539 return BP_RESULT_BADBIOSTABLE; 540 541 /* get the GPIO_I2C_INFO */ 542 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 543 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 544 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 545 info->i2c_slave_address = record->i2c_slave_addr; 546 547 /* TODO: check how to get register offset for en, Y, etc. */ 548 info->gpio_info.clk_a_register_index = 549 le16_to_cpu( 550 header->gpio_pin[table_index].data_a_reg_index); 551 info->gpio_info.clk_a_shift = 552 header->gpio_pin[table_index].gpio_bitshift; 553 554 return BP_RESULT_OK; 555 } 556 557 static struct atom_hpd_int_record *get_hpd_record_for_path_v3( 558 struct bios_parser *bp, 559 struct atom_display_object_path_v3 *object) 560 { 561 struct atom_common_record_header *header; 562 uint32_t offset; 563 564 if (!object) { 565 BREAK_TO_DEBUGGER(); /* Invalid object */ 566 return NULL; 567 } 568 569 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 570 571 for (;;) { 572 header = GET_IMAGE(struct atom_common_record_header, offset); 573 574 if (!header) 575 return NULL; 576 577 if (header->record_type == ATOM_RECORD_END_TYPE || 578 !header->record_size) 579 break; 580 581 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 582 && sizeof(struct atom_hpd_int_record) <= 583 header->record_size) 584 return (struct atom_hpd_int_record *) header; 585 586 offset += header->record_size; 587 } 588 589 return NULL; 590 } 591 592 static enum bp_result bios_parser_get_hpd_info( 593 struct dc_bios *dcb, 594 struct graphics_object_id id, 595 struct graphics_object_hpd_info *info) 596 { 597 struct bios_parser *bp = BP_FROM_DCB(dcb); 598 struct atom_display_object_path_v2 *object; 599 struct atom_display_object_path_v3 *object_path_v3; 600 struct atom_hpd_int_record *record = NULL; 601 602 if (!info) 603 return BP_RESULT_BADINPUT; 604 605 switch (bp->object_info_tbl.revision.minor) { 606 case 4: 607 default: 608 object = get_bios_object(bp, id); 609 610 if (!object) 611 return BP_RESULT_BADINPUT; 612 613 record = get_hpd_record(bp, object); 614 615 break; 616 case 5: 617 object_path_v3 = get_bios_object_from_path_v3(bp, id); 618 619 if (!object_path_v3) 620 return BP_RESULT_BADINPUT; 621 622 record = get_hpd_record_for_path_v3(bp, object_path_v3); 623 break; 624 } 625 626 if (record != NULL) { 627 info->hpd_int_gpio_uid = record->pin_id; 628 info->hpd_active = record->plugin_pin_state; 629 return BP_RESULT_OK; 630 } 631 632 return BP_RESULT_NORECORD; 633 } 634 635 static struct atom_hpd_int_record *get_hpd_record( 636 struct bios_parser *bp, 637 struct atom_display_object_path_v2 *object) 638 { 639 struct atom_common_record_header *header; 640 uint32_t offset; 641 642 if (!object) { 643 BREAK_TO_DEBUGGER(); /* Invalid object */ 644 return NULL; 645 } 646 647 offset = le16_to_cpu(object->disp_recordoffset) 648 + bp->object_info_tbl_offset; 649 650 for (;;) { 651 header = GET_IMAGE(struct atom_common_record_header, offset); 652 653 if (!header) 654 return NULL; 655 656 if (header->record_type == LAST_RECORD_TYPE || 657 !header->record_size) 658 break; 659 660 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 661 && sizeof(struct atom_hpd_int_record) <= 662 header->record_size) 663 return (struct atom_hpd_int_record *) header; 664 665 offset += header->record_size; 666 } 667 668 return NULL; 669 } 670 671 /** 672 * bios_parser_get_gpio_pin_info 673 * Get GpioPin information of input gpio id 674 * 675 * @dcb: pointer to the DC BIOS 676 * @gpio_id: GPIO ID 677 * @info: GpioPin information structure 678 * return: Bios parser result code 679 * note: 680 * to get the GPIO PIN INFO, we need: 681 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 682 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 683 * to get the registerA offset/mask 684 */ 685 static enum bp_result bios_parser_get_gpio_pin_info( 686 struct dc_bios *dcb, 687 uint32_t gpio_id, 688 struct gpio_pin_info *info) 689 { 690 struct bios_parser *bp = BP_FROM_DCB(dcb); 691 struct atom_gpio_pin_lut_v2_1 *header; 692 uint32_t count = 0; 693 uint32_t i = 0; 694 695 if (!DATA_TABLES(gpio_pin_lut)) 696 return BP_RESULT_BADBIOSTABLE; 697 698 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 699 DATA_TABLES(gpio_pin_lut)); 700 if (!header) 701 return BP_RESULT_BADBIOSTABLE; 702 703 if (sizeof(struct atom_common_table_header) + 704 sizeof(struct atom_gpio_pin_assignment) 705 > le16_to_cpu(header->table_header.structuresize)) 706 return BP_RESULT_BADBIOSTABLE; 707 708 if (header->table_header.content_revision != 1) 709 return BP_RESULT_UNSUPPORTED; 710 711 /* Temporary hard code gpio pin info */ 712 count = (le16_to_cpu(header->table_header.structuresize) 713 - sizeof(struct atom_common_table_header)) 714 / sizeof(struct atom_gpio_pin_assignment); 715 for (i = 0; i < count; ++i) { 716 if (header->gpio_pin[i].gpio_id != gpio_id) 717 continue; 718 719 info->offset = 720 (uint32_t) le16_to_cpu( 721 header->gpio_pin[i].data_a_reg_index); 722 info->offset_y = info->offset + 2; 723 info->offset_en = info->offset + 1; 724 info->offset_mask = info->offset - 1; 725 726 info->mask = (uint32_t) (1 << 727 header->gpio_pin[i].gpio_bitshift); 728 info->mask_y = info->mask + 2; 729 info->mask_en = info->mask + 1; 730 info->mask_mask = info->mask - 1; 731 732 return BP_RESULT_OK; 733 } 734 735 return BP_RESULT_NORECORD; 736 } 737 738 static struct device_id device_type_from_device_id(uint16_t device_id) 739 { 740 741 struct device_id result_device_id; 742 743 result_device_id.raw_device_tag = device_id; 744 745 switch (device_id) { 746 case ATOM_DISPLAY_LCD1_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_LCD; 748 result_device_id.enum_id = 1; 749 break; 750 751 case ATOM_DISPLAY_LCD2_SUPPORT: 752 result_device_id.device_type = DEVICE_TYPE_LCD; 753 result_device_id.enum_id = 2; 754 break; 755 756 case ATOM_DISPLAY_DFP1_SUPPORT: 757 result_device_id.device_type = DEVICE_TYPE_DFP; 758 result_device_id.enum_id = 1; 759 break; 760 761 case ATOM_DISPLAY_DFP2_SUPPORT: 762 result_device_id.device_type = DEVICE_TYPE_DFP; 763 result_device_id.enum_id = 2; 764 break; 765 766 case ATOM_DISPLAY_DFP3_SUPPORT: 767 result_device_id.device_type = DEVICE_TYPE_DFP; 768 result_device_id.enum_id = 3; 769 break; 770 771 case ATOM_DISPLAY_DFP4_SUPPORT: 772 result_device_id.device_type = DEVICE_TYPE_DFP; 773 result_device_id.enum_id = 4; 774 break; 775 776 case ATOM_DISPLAY_DFP5_SUPPORT: 777 result_device_id.device_type = DEVICE_TYPE_DFP; 778 result_device_id.enum_id = 5; 779 break; 780 781 case ATOM_DISPLAY_DFP6_SUPPORT: 782 result_device_id.device_type = DEVICE_TYPE_DFP; 783 result_device_id.enum_id = 6; 784 break; 785 786 default: 787 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 788 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 789 result_device_id.enum_id = 0; 790 } 791 return result_device_id; 792 } 793 794 static enum bp_result bios_parser_get_device_tag( 795 struct dc_bios *dcb, 796 struct graphics_object_id connector_object_id, 797 uint32_t device_tag_index, 798 struct connector_device_tag_info *info) 799 { 800 struct bios_parser *bp = BP_FROM_DCB(dcb); 801 struct atom_display_object_path_v2 *object; 802 803 struct atom_display_object_path_v3 *object_path_v3; 804 805 806 if (!info) 807 return BP_RESULT_BADINPUT; 808 809 switch (bp->object_info_tbl.revision.minor) { 810 case 4: 811 default: 812 /* getBiosObject will return MXM object */ 813 object = get_bios_object(bp, connector_object_id); 814 815 if (!object) { 816 BREAK_TO_DEBUGGER(); /* Invalid object id */ 817 return BP_RESULT_BADINPUT; 818 } 819 820 info->acpi_device = 0; /* BIOS no longer provides this */ 821 info->dev_id = device_type_from_device_id(object->device_tag); 822 break; 823 case 5: 824 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 825 826 if (!object_path_v3) { 827 BREAK_TO_DEBUGGER(); /* Invalid object id */ 828 return BP_RESULT_BADINPUT; 829 } 830 info->acpi_device = 0; /* BIOS no longer provides this */ 831 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 832 break; 833 } 834 835 return BP_RESULT_OK; 836 } 837 838 static enum bp_result get_ss_info_v4_1( 839 struct bios_parser *bp, 840 uint32_t id, 841 uint32_t index, 842 struct spread_spectrum_info *ss_info) 843 { 844 enum bp_result result = BP_RESULT_OK; 845 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 846 struct atom_smu_info_v3_3 *smu_info = NULL; 847 848 if (!ss_info) 849 return BP_RESULT_BADINPUT; 850 851 if (!DATA_TABLES(dce_info)) 852 return BP_RESULT_BADBIOSTABLE; 853 854 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 855 DATA_TABLES(dce_info)); 856 if (!disp_cntl_tbl) 857 return BP_RESULT_BADBIOSTABLE; 858 859 860 ss_info->type.STEP_AND_DELAY_INFO = false; 861 ss_info->spread_percentage_divider = 1000; 862 /* BIOS no longer uses target clock. Always enable for now */ 863 ss_info->target_clock_range = 0xffffffff; 864 865 switch (id) { 866 case AS_SIGNAL_TYPE_DVI: 867 ss_info->spread_spectrum_percentage = 868 disp_cntl_tbl->dvi_ss_percentage; 869 ss_info->spread_spectrum_range = 870 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 871 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 872 ss_info->type.CENTER_MODE = true; 873 break; 874 case AS_SIGNAL_TYPE_HDMI: 875 ss_info->spread_spectrum_percentage = 876 disp_cntl_tbl->hdmi_ss_percentage; 877 ss_info->spread_spectrum_range = 878 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 879 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 880 ss_info->type.CENTER_MODE = true; 881 break; 882 /* TODO LVDS not support anymore? */ 883 case AS_SIGNAL_TYPE_DISPLAY_PORT: 884 ss_info->spread_spectrum_percentage = 885 disp_cntl_tbl->dp_ss_percentage; 886 ss_info->spread_spectrum_range = 887 disp_cntl_tbl->dp_ss_rate_10hz * 10; 888 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 889 ss_info->type.CENTER_MODE = true; 890 break; 891 case AS_SIGNAL_TYPE_GPU_PLL: 892 /* atom_firmware: DAL only get data from dce_info table. 893 * if data within smu_info is needed for DAL, VBIOS should 894 * copy it into dce_info 895 */ 896 result = BP_RESULT_UNSUPPORTED; 897 break; 898 case AS_SIGNAL_TYPE_XGMI: 899 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 900 DATA_TABLES(smu_info)); 901 if (!smu_info) 902 return BP_RESULT_BADBIOSTABLE; 903 904 ss_info->spread_spectrum_percentage = 905 smu_info->waflclk_ss_percentage; 906 ss_info->spread_spectrum_range = 907 smu_info->gpuclk_ss_rate_10hz * 10; 908 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 909 ss_info->type.CENTER_MODE = true; 910 break; 911 default: 912 result = BP_RESULT_UNSUPPORTED; 913 } 914 915 return result; 916 } 917 918 static enum bp_result get_ss_info_v4_2( 919 struct bios_parser *bp, 920 uint32_t id, 921 uint32_t index, 922 struct spread_spectrum_info *ss_info) 923 { 924 enum bp_result result = BP_RESULT_OK; 925 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 926 struct atom_smu_info_v3_1 *smu_info = NULL; 927 928 if (!ss_info) 929 return BP_RESULT_BADINPUT; 930 931 if (!DATA_TABLES(dce_info)) 932 return BP_RESULT_BADBIOSTABLE; 933 934 if (!DATA_TABLES(smu_info)) 935 return BP_RESULT_BADBIOSTABLE; 936 937 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 938 DATA_TABLES(dce_info)); 939 if (!disp_cntl_tbl) 940 return BP_RESULT_BADBIOSTABLE; 941 942 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 943 if (!smu_info) 944 return BP_RESULT_BADBIOSTABLE; 945 946 ss_info->type.STEP_AND_DELAY_INFO = false; 947 ss_info->spread_percentage_divider = 1000; 948 /* BIOS no longer uses target clock. Always enable for now */ 949 ss_info->target_clock_range = 0xffffffff; 950 951 switch (id) { 952 case AS_SIGNAL_TYPE_DVI: 953 ss_info->spread_spectrum_percentage = 954 disp_cntl_tbl->dvi_ss_percentage; 955 ss_info->spread_spectrum_range = 956 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 957 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 958 ss_info->type.CENTER_MODE = true; 959 break; 960 case AS_SIGNAL_TYPE_HDMI: 961 ss_info->spread_spectrum_percentage = 962 disp_cntl_tbl->hdmi_ss_percentage; 963 ss_info->spread_spectrum_range = 964 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 965 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 966 ss_info->type.CENTER_MODE = true; 967 break; 968 /* TODO LVDS not support anymore? */ 969 case AS_SIGNAL_TYPE_DISPLAY_PORT: 970 ss_info->spread_spectrum_percentage = 971 smu_info->gpuclk_ss_percentage; 972 ss_info->spread_spectrum_range = 973 smu_info->gpuclk_ss_rate_10hz * 10; 974 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 975 ss_info->type.CENTER_MODE = true; 976 break; 977 case AS_SIGNAL_TYPE_GPU_PLL: 978 /* atom_firmware: DAL only get data from dce_info table. 979 * if data within smu_info is needed for DAL, VBIOS should 980 * copy it into dce_info 981 */ 982 result = BP_RESULT_UNSUPPORTED; 983 break; 984 default: 985 result = BP_RESULT_UNSUPPORTED; 986 } 987 988 return result; 989 } 990 991 static enum bp_result get_ss_info_v4_5( 992 struct bios_parser *bp, 993 uint32_t id, 994 uint32_t index, 995 struct spread_spectrum_info *ss_info) 996 { 997 enum bp_result result = BP_RESULT_OK; 998 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 999 1000 if (!ss_info) 1001 return BP_RESULT_BADINPUT; 1002 1003 if (!DATA_TABLES(dce_info)) 1004 return BP_RESULT_BADBIOSTABLE; 1005 1006 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1007 DATA_TABLES(dce_info)); 1008 if (!disp_cntl_tbl) 1009 return BP_RESULT_BADBIOSTABLE; 1010 1011 ss_info->type.STEP_AND_DELAY_INFO = false; 1012 ss_info->spread_percentage_divider = 1000; 1013 /* BIOS no longer uses target clock. Always enable for now */ 1014 ss_info->target_clock_range = 0xffffffff; 1015 1016 switch (id) { 1017 case AS_SIGNAL_TYPE_DVI: 1018 ss_info->spread_spectrum_percentage = 1019 disp_cntl_tbl->dvi_ss_percentage; 1020 ss_info->spread_spectrum_range = 1021 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1022 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1023 ss_info->type.CENTER_MODE = true; 1024 break; 1025 case AS_SIGNAL_TYPE_HDMI: 1026 ss_info->spread_spectrum_percentage = 1027 disp_cntl_tbl->hdmi_ss_percentage; 1028 ss_info->spread_spectrum_range = 1029 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1030 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1031 ss_info->type.CENTER_MODE = true; 1032 break; 1033 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1034 ss_info->spread_spectrum_percentage = 1035 disp_cntl_tbl->dp_ss_percentage; 1036 ss_info->spread_spectrum_range = 1037 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1038 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1039 ss_info->type.CENTER_MODE = true; 1040 break; 1041 case AS_SIGNAL_TYPE_GPU_PLL: 1042 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1043 * SMU Display PLL supposed to be without spread. 1044 * Better place for it would be in atom_display_controller_info_v4_5 table. 1045 */ 1046 result = BP_RESULT_UNSUPPORTED; 1047 break; 1048 default: 1049 result = BP_RESULT_UNSUPPORTED; 1050 break; 1051 } 1052 1053 return result; 1054 } 1055 1056 /** 1057 * bios_parser_get_spread_spectrum_info 1058 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1059 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1060 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1061 * ver 3.1, 1062 * there is only one entry for each signal /ss id. However, there is 1063 * no planning of supporting multiple spread Sprectum entry for EverGreen 1064 * @dcb: pointer to the DC BIOS 1065 * @signal: ASSignalType to be converted to info index 1066 * @index: number of entries that match the converted info index 1067 * @ss_info: sprectrum information structure, 1068 * return: Bios parser result code 1069 */ 1070 static enum bp_result bios_parser_get_spread_spectrum_info( 1071 struct dc_bios *dcb, 1072 enum as_signal_type signal, 1073 uint32_t index, 1074 struct spread_spectrum_info *ss_info) 1075 { 1076 struct bios_parser *bp = BP_FROM_DCB(dcb); 1077 enum bp_result result = BP_RESULT_UNSUPPORTED; 1078 struct atom_common_table_header *header; 1079 struct atom_data_revision tbl_revision; 1080 1081 if (!ss_info) /* check for bad input */ 1082 return BP_RESULT_BADINPUT; 1083 1084 if (!DATA_TABLES(dce_info)) 1085 return BP_RESULT_UNSUPPORTED; 1086 1087 header = GET_IMAGE(struct atom_common_table_header, 1088 DATA_TABLES(dce_info)); 1089 get_atom_data_table_revision(header, &tbl_revision); 1090 1091 switch (tbl_revision.major) { 1092 case 4: 1093 switch (tbl_revision.minor) { 1094 case 1: 1095 return get_ss_info_v4_1(bp, signal, index, ss_info); 1096 case 2: 1097 case 3: 1098 case 4: 1099 return get_ss_info_v4_2(bp, signal, index, ss_info); 1100 case 5: 1101 return get_ss_info_v4_5(bp, signal, index, ss_info); 1102 1103 default: 1104 ASSERT(0); 1105 break; 1106 } 1107 break; 1108 default: 1109 break; 1110 } 1111 /* there can not be more then one entry for SS Info table */ 1112 return result; 1113 } 1114 1115 static enum bp_result get_soc_bb_info_v4_4( 1116 struct bios_parser *bp, 1117 struct bp_soc_bb_info *soc_bb_info) 1118 { 1119 enum bp_result result = BP_RESULT_OK; 1120 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1121 1122 if (!soc_bb_info) 1123 return BP_RESULT_BADINPUT; 1124 1125 if (!DATA_TABLES(dce_info)) 1126 return BP_RESULT_BADBIOSTABLE; 1127 1128 if (!DATA_TABLES(smu_info)) 1129 return BP_RESULT_BADBIOSTABLE; 1130 1131 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1132 DATA_TABLES(dce_info)); 1133 if (!disp_cntl_tbl) 1134 return BP_RESULT_BADBIOSTABLE; 1135 1136 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1137 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1138 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1139 1140 return result; 1141 } 1142 1143 static enum bp_result get_soc_bb_info_v4_5( 1144 struct bios_parser *bp, 1145 struct bp_soc_bb_info *soc_bb_info) 1146 { 1147 enum bp_result result = BP_RESULT_OK; 1148 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1149 1150 if (!soc_bb_info) 1151 return BP_RESULT_BADINPUT; 1152 1153 if (!DATA_TABLES(dce_info)) 1154 return BP_RESULT_BADBIOSTABLE; 1155 1156 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1157 DATA_TABLES(dce_info)); 1158 if (!disp_cntl_tbl) 1159 return BP_RESULT_BADBIOSTABLE; 1160 1161 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1162 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1163 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1164 1165 return result; 1166 } 1167 1168 static enum bp_result bios_parser_get_soc_bb_info( 1169 struct dc_bios *dcb, 1170 struct bp_soc_bb_info *soc_bb_info) 1171 { 1172 struct bios_parser *bp = BP_FROM_DCB(dcb); 1173 enum bp_result result = BP_RESULT_UNSUPPORTED; 1174 struct atom_common_table_header *header; 1175 struct atom_data_revision tbl_revision; 1176 1177 if (!soc_bb_info) /* check for bad input */ 1178 return BP_RESULT_BADINPUT; 1179 1180 if (!DATA_TABLES(dce_info)) 1181 return BP_RESULT_UNSUPPORTED; 1182 1183 header = GET_IMAGE(struct atom_common_table_header, 1184 DATA_TABLES(dce_info)); 1185 get_atom_data_table_revision(header, &tbl_revision); 1186 1187 switch (tbl_revision.major) { 1188 case 4: 1189 switch (tbl_revision.minor) { 1190 case 1: 1191 case 2: 1192 case 3: 1193 break; 1194 case 4: 1195 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1196 break; 1197 case 5: 1198 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1199 break; 1200 default: 1201 break; 1202 } 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 return result; 1209 } 1210 1211 static enum bp_result get_disp_caps_v4_1( 1212 struct bios_parser *bp, 1213 uint8_t *dce_caps) 1214 { 1215 enum bp_result result = BP_RESULT_OK; 1216 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1217 1218 if (!dce_caps) 1219 return BP_RESULT_BADINPUT; 1220 1221 if (!DATA_TABLES(dce_info)) 1222 return BP_RESULT_BADBIOSTABLE; 1223 1224 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1225 DATA_TABLES(dce_info)); 1226 1227 if (!disp_cntl_tbl) 1228 return BP_RESULT_BADBIOSTABLE; 1229 1230 *dce_caps = disp_cntl_tbl->display_caps; 1231 1232 return result; 1233 } 1234 1235 static enum bp_result get_disp_caps_v4_2( 1236 struct bios_parser *bp, 1237 uint8_t *dce_caps) 1238 { 1239 enum bp_result result = BP_RESULT_OK; 1240 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1241 1242 if (!dce_caps) 1243 return BP_RESULT_BADINPUT; 1244 1245 if (!DATA_TABLES(dce_info)) 1246 return BP_RESULT_BADBIOSTABLE; 1247 1248 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1249 DATA_TABLES(dce_info)); 1250 1251 if (!disp_cntl_tbl) 1252 return BP_RESULT_BADBIOSTABLE; 1253 1254 *dce_caps = disp_cntl_tbl->display_caps; 1255 1256 return result; 1257 } 1258 1259 static enum bp_result get_disp_caps_v4_3( 1260 struct bios_parser *bp, 1261 uint8_t *dce_caps) 1262 { 1263 enum bp_result result = BP_RESULT_OK; 1264 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1265 1266 if (!dce_caps) 1267 return BP_RESULT_BADINPUT; 1268 1269 if (!DATA_TABLES(dce_info)) 1270 return BP_RESULT_BADBIOSTABLE; 1271 1272 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1273 DATA_TABLES(dce_info)); 1274 1275 if (!disp_cntl_tbl) 1276 return BP_RESULT_BADBIOSTABLE; 1277 1278 *dce_caps = disp_cntl_tbl->display_caps; 1279 1280 return result; 1281 } 1282 1283 static enum bp_result get_disp_caps_v4_4( 1284 struct bios_parser *bp, 1285 uint8_t *dce_caps) 1286 { 1287 enum bp_result result = BP_RESULT_OK; 1288 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1289 1290 if (!dce_caps) 1291 return BP_RESULT_BADINPUT; 1292 1293 if (!DATA_TABLES(dce_info)) 1294 return BP_RESULT_BADBIOSTABLE; 1295 1296 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1297 DATA_TABLES(dce_info)); 1298 1299 if (!disp_cntl_tbl) 1300 return BP_RESULT_BADBIOSTABLE; 1301 1302 *dce_caps = disp_cntl_tbl->display_caps; 1303 1304 return result; 1305 } 1306 1307 static enum bp_result get_disp_caps_v4_5( 1308 struct bios_parser *bp, 1309 uint8_t *dce_caps) 1310 { 1311 enum bp_result result = BP_RESULT_OK; 1312 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1313 1314 if (!dce_caps) 1315 return BP_RESULT_BADINPUT; 1316 1317 if (!DATA_TABLES(dce_info)) 1318 return BP_RESULT_BADBIOSTABLE; 1319 1320 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1321 DATA_TABLES(dce_info)); 1322 1323 if (!disp_cntl_tbl) 1324 return BP_RESULT_BADBIOSTABLE; 1325 1326 *dce_caps = disp_cntl_tbl->display_caps; 1327 1328 return result; 1329 } 1330 1331 static enum bp_result bios_parser_get_lttpr_interop( 1332 struct dc_bios *dcb, 1333 uint8_t *dce_caps) 1334 { 1335 struct bios_parser *bp = BP_FROM_DCB(dcb); 1336 enum bp_result result = BP_RESULT_UNSUPPORTED; 1337 struct atom_common_table_header *header; 1338 struct atom_data_revision tbl_revision; 1339 1340 if (!DATA_TABLES(dce_info)) 1341 return BP_RESULT_UNSUPPORTED; 1342 1343 header = GET_IMAGE(struct atom_common_table_header, 1344 DATA_TABLES(dce_info)); 1345 get_atom_data_table_revision(header, &tbl_revision); 1346 switch (tbl_revision.major) { 1347 case 4: 1348 switch (tbl_revision.minor) { 1349 case 1: 1350 result = get_disp_caps_v4_1(bp, dce_caps); 1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1352 break; 1353 case 2: 1354 result = get_disp_caps_v4_2(bp, dce_caps); 1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1356 break; 1357 case 3: 1358 result = get_disp_caps_v4_3(bp, dce_caps); 1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1360 break; 1361 case 4: 1362 result = get_disp_caps_v4_4(bp, dce_caps); 1363 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1364 break; 1365 case 5: 1366 result = get_disp_caps_v4_5(bp, dce_caps); 1367 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1368 break; 1369 1370 default: 1371 break; 1372 } 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 return result; 1379 } 1380 1381 static enum bp_result bios_parser_get_lttpr_caps( 1382 struct dc_bios *dcb, 1383 uint8_t *dce_caps) 1384 { 1385 struct bios_parser *bp = BP_FROM_DCB(dcb); 1386 enum bp_result result = BP_RESULT_UNSUPPORTED; 1387 struct atom_common_table_header *header; 1388 struct atom_data_revision tbl_revision; 1389 1390 if (!DATA_TABLES(dce_info)) 1391 return BP_RESULT_UNSUPPORTED; 1392 1393 header = GET_IMAGE(struct atom_common_table_header, 1394 DATA_TABLES(dce_info)); 1395 get_atom_data_table_revision(header, &tbl_revision); 1396 switch (tbl_revision.major) { 1397 case 4: 1398 switch (tbl_revision.minor) { 1399 case 1: 1400 result = get_disp_caps_v4_1(bp, dce_caps); 1401 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1402 break; 1403 case 2: 1404 result = get_disp_caps_v4_2(bp, dce_caps); 1405 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1406 break; 1407 case 3: 1408 result = get_disp_caps_v4_3(bp, dce_caps); 1409 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1410 break; 1411 case 4: 1412 result = get_disp_caps_v4_4(bp, dce_caps); 1413 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1414 break; 1415 case 5: 1416 result = get_disp_caps_v4_5(bp, dce_caps); 1417 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1418 break; 1419 default: 1420 break; 1421 } 1422 break; 1423 default: 1424 break; 1425 } 1426 1427 return result; 1428 } 1429 1430 static enum bp_result get_embedded_panel_info_v2_1( 1431 struct bios_parser *bp, 1432 struct embedded_panel_info *info) 1433 { 1434 struct lcd_info_v2_1 *lvds; 1435 1436 if (!info) 1437 return BP_RESULT_BADINPUT; 1438 1439 if (!DATA_TABLES(lcd_info)) 1440 return BP_RESULT_UNSUPPORTED; 1441 1442 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1443 1444 if (!lvds) 1445 return BP_RESULT_BADBIOSTABLE; 1446 1447 /* TODO: previous vv1_3, should v2_1 */ 1448 if (!((lvds->table_header.format_revision == 2) 1449 && (lvds->table_header.content_revision >= 1))) 1450 return BP_RESULT_UNSUPPORTED; 1451 1452 memset(info, 0, sizeof(struct embedded_panel_info)); 1453 1454 /* We need to convert from 10KHz units into KHz units */ 1455 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1456 /* usHActive does not include borders, according to VBIOS team */ 1457 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1458 /* usHBlanking_Time includes borders, so we should really be 1459 * subtractingborders duing this translation, but LVDS generally 1460 * doesn't have borders, so we should be okay leaving this as is for 1461 * now. May need to revisit if we ever have LVDS with borders 1462 */ 1463 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1464 /* usVActive does not include borders, according to VBIOS team*/ 1465 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1466 /* usVBlanking_Time includes borders, so we should really be 1467 * subtracting borders duing this translation, but LVDS generally 1468 * doesn't have borders, so we should be okay leaving this as is for 1469 * now. May need to revisit if we ever have LVDS with borders 1470 */ 1471 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1472 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1473 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1474 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1475 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1476 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1477 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1478 1479 /* not provided by VBIOS */ 1480 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1481 1482 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1483 & ATOM_HSYNC_POLARITY); 1484 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1485 & ATOM_VSYNC_POLARITY); 1486 1487 /* not provided by VBIOS */ 1488 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1489 1490 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1491 & ATOM_H_REPLICATIONBY2); 1492 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1493 & ATOM_V_REPLICATIONBY2); 1494 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1495 & ATOM_COMPOSITESYNC); 1496 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1497 1498 /* not provided by VBIOS*/ 1499 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1500 /* not provided by VBIOS*/ 1501 info->ss_id = 0; 1502 1503 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1504 1505 return BP_RESULT_OK; 1506 } 1507 1508 static enum bp_result bios_parser_get_embedded_panel_info( 1509 struct dc_bios *dcb, 1510 struct embedded_panel_info *info) 1511 { 1512 struct bios_parser 1513 *bp = BP_FROM_DCB(dcb); 1514 struct atom_common_table_header *header; 1515 struct atom_data_revision tbl_revision; 1516 1517 if (!DATA_TABLES(lcd_info)) 1518 return BP_RESULT_FAILURE; 1519 1520 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1521 1522 if (!header) 1523 return BP_RESULT_BADBIOSTABLE; 1524 1525 get_atom_data_table_revision(header, &tbl_revision); 1526 1527 switch (tbl_revision.major) { 1528 case 2: 1529 switch (tbl_revision.minor) { 1530 case 1: 1531 return get_embedded_panel_info_v2_1(bp, info); 1532 default: 1533 break; 1534 } 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 return BP_RESULT_FAILURE; 1541 } 1542 1543 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1544 { 1545 enum dal_device_type device_type = device_id.device_type; 1546 uint32_t enum_id = device_id.enum_id; 1547 1548 switch (device_type) { 1549 case DEVICE_TYPE_LCD: 1550 switch (enum_id) { 1551 case 1: 1552 return ATOM_DISPLAY_LCD1_SUPPORT; 1553 default: 1554 break; 1555 } 1556 break; 1557 case DEVICE_TYPE_DFP: 1558 switch (enum_id) { 1559 case 1: 1560 return ATOM_DISPLAY_DFP1_SUPPORT; 1561 case 2: 1562 return ATOM_DISPLAY_DFP2_SUPPORT; 1563 case 3: 1564 return ATOM_DISPLAY_DFP3_SUPPORT; 1565 case 4: 1566 return ATOM_DISPLAY_DFP4_SUPPORT; 1567 case 5: 1568 return ATOM_DISPLAY_DFP5_SUPPORT; 1569 case 6: 1570 return ATOM_DISPLAY_DFP6_SUPPORT; 1571 default: 1572 break; 1573 } 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 /* Unidentified device ID, return empty support mask. */ 1580 return 0; 1581 } 1582 1583 static bool bios_parser_is_device_id_supported( 1584 struct dc_bios *dcb, 1585 struct device_id id) 1586 { 1587 struct bios_parser *bp = BP_FROM_DCB(dcb); 1588 1589 uint32_t mask = get_support_mask_for_device_id(id); 1590 1591 switch (bp->object_info_tbl.revision.minor) { 1592 case 4: 1593 default: 1594 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1595 break; 1596 case 5: 1597 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1598 break; 1599 } 1600 1601 return false; 1602 } 1603 1604 static uint32_t bios_parser_get_ss_entry_number( 1605 struct dc_bios *dcb, 1606 enum as_signal_type signal) 1607 { 1608 /* TODO: DAL2 atomfirmware implementation does not need this. 1609 * why DAL3 need this? 1610 */ 1611 return 1; 1612 } 1613 1614 static enum bp_result bios_parser_transmitter_control( 1615 struct dc_bios *dcb, 1616 struct bp_transmitter_control *cntl) 1617 { 1618 struct bios_parser *bp = BP_FROM_DCB(dcb); 1619 1620 if (!bp->cmd_tbl.transmitter_control) 1621 return BP_RESULT_FAILURE; 1622 1623 return bp->cmd_tbl.transmitter_control(bp, cntl); 1624 } 1625 1626 static enum bp_result bios_parser_encoder_control( 1627 struct dc_bios *dcb, 1628 struct bp_encoder_control *cntl) 1629 { 1630 struct bios_parser *bp = BP_FROM_DCB(dcb); 1631 1632 if (!bp->cmd_tbl.dig_encoder_control) 1633 return BP_RESULT_FAILURE; 1634 1635 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1636 } 1637 1638 static enum bp_result bios_parser_set_pixel_clock( 1639 struct dc_bios *dcb, 1640 struct bp_pixel_clock_parameters *bp_params) 1641 { 1642 struct bios_parser *bp = BP_FROM_DCB(dcb); 1643 1644 if (!bp->cmd_tbl.set_pixel_clock) 1645 return BP_RESULT_FAILURE; 1646 1647 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1648 } 1649 1650 static enum bp_result bios_parser_set_dce_clock( 1651 struct dc_bios *dcb, 1652 struct bp_set_dce_clock_parameters *bp_params) 1653 { 1654 struct bios_parser *bp = BP_FROM_DCB(dcb); 1655 1656 if (!bp->cmd_tbl.set_dce_clock) 1657 return BP_RESULT_FAILURE; 1658 1659 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1660 } 1661 1662 static enum bp_result bios_parser_program_crtc_timing( 1663 struct dc_bios *dcb, 1664 struct bp_hw_crtc_timing_parameters *bp_params) 1665 { 1666 struct bios_parser *bp = BP_FROM_DCB(dcb); 1667 1668 if (!bp->cmd_tbl.set_crtc_timing) 1669 return BP_RESULT_FAILURE; 1670 1671 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1672 } 1673 1674 static enum bp_result bios_parser_enable_crtc( 1675 struct dc_bios *dcb, 1676 enum controller_id id, 1677 bool enable) 1678 { 1679 struct bios_parser *bp = BP_FROM_DCB(dcb); 1680 1681 if (!bp->cmd_tbl.enable_crtc) 1682 return BP_RESULT_FAILURE; 1683 1684 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1685 } 1686 1687 static enum bp_result bios_parser_enable_disp_power_gating( 1688 struct dc_bios *dcb, 1689 enum controller_id controller_id, 1690 enum bp_pipe_control_action action) 1691 { 1692 struct bios_parser *bp = BP_FROM_DCB(dcb); 1693 1694 if (!bp->cmd_tbl.enable_disp_power_gating) 1695 return BP_RESULT_FAILURE; 1696 1697 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1698 action); 1699 } 1700 1701 static enum bp_result bios_parser_enable_lvtma_control( 1702 struct dc_bios *dcb, 1703 uint8_t uc_pwr_on, 1704 uint8_t panel_instance) 1705 { 1706 struct bios_parser *bp = BP_FROM_DCB(dcb); 1707 1708 if (!bp->cmd_tbl.enable_lvtma_control) 1709 return BP_RESULT_FAILURE; 1710 1711 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance); 1712 } 1713 1714 static bool bios_parser_is_accelerated_mode( 1715 struct dc_bios *dcb) 1716 { 1717 return bios_is_accelerated_mode(dcb); 1718 } 1719 1720 /** 1721 * bios_parser_set_scratch_critical_state - update critical state bit 1722 * in VBIOS scratch register 1723 * 1724 * @dcb: pointer to the DC BIO 1725 * @state: set or reset state 1726 */ 1727 static void bios_parser_set_scratch_critical_state( 1728 struct dc_bios *dcb, 1729 bool state) 1730 { 1731 bios_set_scratch_critical_state(dcb, state); 1732 } 1733 1734 struct atom_dig_transmitter_info_header_v5_3 { 1735 struct atom_common_table_header table_header; 1736 uint16_t dpphy_hdmi_settings_offset; 1737 uint16_t dpphy_dvi_settings_offset; 1738 uint16_t dpphy_dp_setting_table_offset; 1739 uint16_t uniphy_xbar_settings_v2_table_offset; 1740 uint16_t dpphy_internal_reg_overide_offset; 1741 }; 1742 1743 static enum bp_result bios_parser_get_firmware_info( 1744 struct dc_bios *dcb, 1745 struct dc_firmware_info *info) 1746 { 1747 struct bios_parser *bp = BP_FROM_DCB(dcb); 1748 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1749 struct atom_common_table_header *header; 1750 1751 struct atom_data_revision revision; 1752 1753 if (info && DATA_TABLES(firmwareinfo)) { 1754 header = GET_IMAGE(struct atom_common_table_header, 1755 DATA_TABLES(firmwareinfo)); 1756 get_atom_data_table_revision(header, &revision); 1757 switch (revision.major) { 1758 case 3: 1759 switch (revision.minor) { 1760 case 1: 1761 result = get_firmware_info_v3_1(bp, info); 1762 break; 1763 case 2: 1764 case 3: 1765 result = get_firmware_info_v3_2(bp, info); 1766 break; 1767 case 4: 1768 result = get_firmware_info_v3_4(bp, info); 1769 break; 1770 default: 1771 break; 1772 } 1773 break; 1774 default: 1775 break; 1776 } 1777 } 1778 1779 return result; 1780 } 1781 1782 static enum bp_result get_firmware_info_v3_1( 1783 struct bios_parser *bp, 1784 struct dc_firmware_info *info) 1785 { 1786 struct atom_firmware_info_v3_1 *firmware_info; 1787 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1788 1789 if (!info) 1790 return BP_RESULT_BADINPUT; 1791 1792 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1793 DATA_TABLES(firmwareinfo)); 1794 1795 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1796 DATA_TABLES(dce_info)); 1797 1798 if (!firmware_info || !dce_info) 1799 return BP_RESULT_BADBIOSTABLE; 1800 1801 memset(info, 0, sizeof(*info)); 1802 1803 /* Pixel clock pll information. */ 1804 /* We need to convert from 10KHz units into KHz units */ 1805 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1806 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1807 1808 /* 27MHz for Vega10: */ 1809 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1810 1811 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1812 if (info->pll_info.crystal_frequency == 0) 1813 info->pll_info.crystal_frequency = 27000; 1814 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1815 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1816 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1817 1818 /* Get GPU PLL VCO Clock */ 1819 1820 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1821 /* VBIOS gives in 10KHz */ 1822 info->smu_gpu_pll_output_freq = 1823 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1824 } 1825 1826 info->oem_i2c_present = false; 1827 1828 return BP_RESULT_OK; 1829 } 1830 1831 static enum bp_result get_firmware_info_v3_2( 1832 struct bios_parser *bp, 1833 struct dc_firmware_info *info) 1834 { 1835 struct atom_firmware_info_v3_2 *firmware_info; 1836 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1837 struct atom_common_table_header *header; 1838 struct atom_data_revision revision; 1839 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1840 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1841 1842 if (!info) 1843 return BP_RESULT_BADINPUT; 1844 1845 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1846 DATA_TABLES(firmwareinfo)); 1847 1848 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1849 DATA_TABLES(dce_info)); 1850 1851 if (!firmware_info || !dce_info) 1852 return BP_RESULT_BADBIOSTABLE; 1853 1854 memset(info, 0, sizeof(*info)); 1855 1856 header = GET_IMAGE(struct atom_common_table_header, 1857 DATA_TABLES(smu_info)); 1858 get_atom_data_table_revision(header, &revision); 1859 1860 if (revision.minor == 2) { 1861 /* Vega12 */ 1862 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1863 DATA_TABLES(smu_info)); 1864 1865 if (!smu_info_v3_2) 1866 return BP_RESULT_BADBIOSTABLE; 1867 1868 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1869 } else if (revision.minor == 3) { 1870 /* Vega20 */ 1871 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1872 DATA_TABLES(smu_info)); 1873 1874 if (!smu_info_v3_3) 1875 return BP_RESULT_BADBIOSTABLE; 1876 1877 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1878 } 1879 1880 // We need to convert from 10KHz units into KHz units. 1881 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1882 1883 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1884 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1885 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1886 if (info->pll_info.crystal_frequency == 0) { 1887 if (revision.minor == 2) 1888 info->pll_info.crystal_frequency = 27000; 1889 else if (revision.minor == 3) 1890 info->pll_info.crystal_frequency = 100000; 1891 } 1892 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1893 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1894 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1895 1896 /* Get GPU PLL VCO Clock */ 1897 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1898 if (revision.minor == 2) 1899 info->smu_gpu_pll_output_freq = 1900 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1901 else if (revision.minor == 3) 1902 info->smu_gpu_pll_output_freq = 1903 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1904 } 1905 1906 if (firmware_info->board_i2c_feature_id == 0x2) { 1907 info->oem_i2c_present = true; 1908 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1909 } else { 1910 info->oem_i2c_present = false; 1911 } 1912 1913 return BP_RESULT_OK; 1914 } 1915 1916 static enum bp_result get_firmware_info_v3_4( 1917 struct bios_parser *bp, 1918 struct dc_firmware_info *info) 1919 { 1920 struct atom_firmware_info_v3_4 *firmware_info; 1921 struct atom_common_table_header *header; 1922 struct atom_data_revision revision; 1923 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1924 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1925 1926 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1927 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1928 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1929 1930 if (!info) 1931 return BP_RESULT_BADINPUT; 1932 1933 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1934 DATA_TABLES(firmwareinfo)); 1935 1936 if (!firmware_info) 1937 return BP_RESULT_BADBIOSTABLE; 1938 1939 memset(info, 0, sizeof(*info)); 1940 1941 header = GET_IMAGE(struct atom_common_table_header, 1942 DATA_TABLES(dce_info)); 1943 1944 get_atom_data_table_revision(header, &revision); 1945 1946 switch (revision.major) { 1947 case 4: 1948 switch (revision.minor) { 1949 case 5: 1950 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1951 DATA_TABLES(dce_info)); 1952 1953 if (!dce_info_v4_5) 1954 return BP_RESULT_BADBIOSTABLE; 1955 1956 /* 100MHz expected */ 1957 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1958 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1959 /* 50MHz expected */ 1960 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1961 1962 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1963 break; 1964 1965 case 4: 1966 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1967 DATA_TABLES(dce_info)); 1968 1969 if (!dce_info_v4_4) 1970 return BP_RESULT_BADBIOSTABLE; 1971 1972 /* 100MHz expected */ 1973 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1974 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1975 /* 50MHz expected */ 1976 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1977 1978 /* Get SMU Display PLL VCO Frequency in KHz*/ 1979 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1980 break; 1981 1982 default: 1983 /* should not come here, keep as backup, as was before */ 1984 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1985 DATA_TABLES(dce_info)); 1986 1987 if (!dce_info_v4_1) 1988 return BP_RESULT_BADBIOSTABLE; 1989 1990 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 1991 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 1992 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 1993 break; 1994 } 1995 break; 1996 1997 default: 1998 ASSERT(0); 1999 break; 2000 } 2001 2002 header = GET_IMAGE(struct atom_common_table_header, 2003 DATA_TABLES(smu_info)); 2004 get_atom_data_table_revision(header, &revision); 2005 2006 switch (revision.major) { 2007 case 3: 2008 switch (revision.minor) { 2009 case 5: 2010 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2011 DATA_TABLES(smu_info)); 2012 2013 if (!smu_info_v3_5) 2014 return BP_RESULT_BADBIOSTABLE; 2015 2016 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2017 break; 2018 2019 default: 2020 break; 2021 } 2022 break; 2023 2024 case 4: 2025 switch (revision.minor) { 2026 case 0: 2027 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2028 DATA_TABLES(smu_info)); 2029 2030 if (!smu_info_v4_0) 2031 return BP_RESULT_BADBIOSTABLE; 2032 2033 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2034 break; 2035 2036 default: 2037 break; 2038 } 2039 break; 2040 2041 default: 2042 break; 2043 } 2044 2045 // We need to convert from 10KHz units into KHz units. 2046 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2047 2048 if (firmware_info->board_i2c_feature_id == 0x2) { 2049 info->oem_i2c_present = true; 2050 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2051 } else { 2052 info->oem_i2c_present = false; 2053 } 2054 2055 return BP_RESULT_OK; 2056 } 2057 2058 static enum bp_result bios_parser_get_encoder_cap_info( 2059 struct dc_bios *dcb, 2060 struct graphics_object_id object_id, 2061 struct bp_encoder_cap_info *info) 2062 { 2063 struct bios_parser *bp = BP_FROM_DCB(dcb); 2064 struct atom_display_object_path_v2 *object; 2065 struct atom_encoder_caps_record *record = NULL; 2066 2067 if (!info) 2068 return BP_RESULT_BADINPUT; 2069 2070 #if defined(CONFIG_DRM_AMD_DC_DCN) 2071 /* encoder cap record not available in v1_5 */ 2072 if (bp->object_info_tbl.revision.minor == 5) 2073 return BP_RESULT_NORECORD; 2074 #endif 2075 2076 object = get_bios_object(bp, object_id); 2077 2078 if (!object) 2079 return BP_RESULT_BADINPUT; 2080 2081 record = get_encoder_cap_record(bp, object); 2082 if (!record) 2083 return BP_RESULT_NORECORD; 2084 2085 info->DP_HBR2_CAP = (record->encodercaps & 2086 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2087 info->DP_HBR2_EN = (record->encodercaps & 2088 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2089 info->DP_HBR3_EN = (record->encodercaps & 2090 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2091 info->HDMI_6GB_EN = (record->encodercaps & 2092 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2093 info->IS_DP2_CAPABLE = (record->encodercaps & 2094 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2095 info->DP_UHBR10_EN = (record->encodercaps & 2096 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2097 info->DP_UHBR13_5_EN = (record->encodercaps & 2098 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2099 info->DP_UHBR20_EN = (record->encodercaps & 2100 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2101 info->DP_IS_USB_C = (record->encodercaps & 2102 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2103 2104 return BP_RESULT_OK; 2105 } 2106 2107 2108 static struct atom_encoder_caps_record *get_encoder_cap_record( 2109 struct bios_parser *bp, 2110 struct atom_display_object_path_v2 *object) 2111 { 2112 struct atom_common_record_header *header; 2113 uint32_t offset; 2114 2115 if (!object) { 2116 BREAK_TO_DEBUGGER(); /* Invalid object */ 2117 return NULL; 2118 } 2119 2120 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2121 2122 for (;;) { 2123 header = GET_IMAGE(struct atom_common_record_header, offset); 2124 2125 if (!header) 2126 return NULL; 2127 2128 offset += header->record_size; 2129 2130 if (header->record_type == LAST_RECORD_TYPE || 2131 !header->record_size) 2132 break; 2133 2134 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2135 continue; 2136 2137 if (sizeof(struct atom_encoder_caps_record) <= 2138 header->record_size) 2139 return (struct atom_encoder_caps_record *)header; 2140 } 2141 2142 return NULL; 2143 } 2144 2145 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2146 struct bios_parser *bp, 2147 struct atom_display_object_path_v2 *object) 2148 { 2149 struct atom_common_record_header *header; 2150 uint32_t offset; 2151 2152 if (!object) { 2153 BREAK_TO_DEBUGGER(); /* Invalid object */ 2154 return NULL; 2155 } 2156 2157 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2158 2159 for (;;) { 2160 header = GET_IMAGE(struct atom_common_record_header, offset); 2161 2162 if (!header) 2163 return NULL; 2164 2165 offset += header->record_size; 2166 2167 if (header->record_type == LAST_RECORD_TYPE || 2168 !header->record_size) 2169 break; 2170 2171 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2172 continue; 2173 2174 if (sizeof(struct atom_disp_connector_caps_record) <= 2175 header->record_size) 2176 return (struct atom_disp_connector_caps_record *)header; 2177 } 2178 2179 return NULL; 2180 } 2181 2182 static struct atom_connector_caps_record *get_connector_caps_record( 2183 struct bios_parser *bp, 2184 struct atom_display_object_path_v3 *object) 2185 { 2186 struct atom_common_record_header *header; 2187 uint32_t offset; 2188 2189 if (!object) { 2190 BREAK_TO_DEBUGGER(); /* Invalid object */ 2191 return NULL; 2192 } 2193 2194 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2195 2196 for (;;) { 2197 header = GET_IMAGE(struct atom_common_record_header, offset); 2198 2199 if (!header) 2200 return NULL; 2201 2202 offset += header->record_size; 2203 2204 if (header->record_type == ATOM_RECORD_END_TYPE || 2205 !header->record_size) 2206 break; 2207 2208 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2209 continue; 2210 2211 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2212 return (struct atom_connector_caps_record *)header; 2213 } 2214 2215 return NULL; 2216 } 2217 2218 static enum bp_result bios_parser_get_disp_connector_caps_info( 2219 struct dc_bios *dcb, 2220 struct graphics_object_id object_id, 2221 struct bp_disp_connector_caps_info *info) 2222 { 2223 struct bios_parser *bp = BP_FROM_DCB(dcb); 2224 struct atom_display_object_path_v2 *object; 2225 2226 struct atom_display_object_path_v3 *object_path_v3; 2227 struct atom_connector_caps_record *record_path_v3; 2228 2229 struct atom_disp_connector_caps_record *record = NULL; 2230 2231 if (!info) 2232 return BP_RESULT_BADINPUT; 2233 2234 switch (bp->object_info_tbl.revision.minor) { 2235 case 4: 2236 default: 2237 object = get_bios_object(bp, object_id); 2238 2239 if (!object) 2240 return BP_RESULT_BADINPUT; 2241 2242 record = get_disp_connector_caps_record(bp, object); 2243 if (!record) 2244 return BP_RESULT_NORECORD; 2245 2246 info->INTERNAL_DISPLAY = 2247 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2248 info->INTERNAL_DISPLAY_BL = 2249 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2250 break; 2251 case 5: 2252 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2253 2254 if (!object_path_v3) 2255 return BP_RESULT_BADINPUT; 2256 2257 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2258 if (!record_path_v3) 2259 return BP_RESULT_NORECORD; 2260 2261 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2262 ? 1 : 0; 2263 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2264 ? 1 : 0; 2265 break; 2266 } 2267 2268 return BP_RESULT_OK; 2269 } 2270 2271 static struct atom_connector_speed_record *get_connector_speed_cap_record( 2272 struct bios_parser *bp, 2273 struct atom_display_object_path_v3 *object) 2274 { 2275 struct atom_common_record_header *header; 2276 uint32_t offset; 2277 2278 if (!object) { 2279 BREAK_TO_DEBUGGER(); /* Invalid object */ 2280 return NULL; 2281 } 2282 2283 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2284 2285 for (;;) { 2286 header = GET_IMAGE(struct atom_common_record_header, offset); 2287 2288 if (!header) 2289 return NULL; 2290 2291 offset += header->record_size; 2292 2293 if (header->record_type == ATOM_RECORD_END_TYPE || 2294 !header->record_size) 2295 break; 2296 2297 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2298 continue; 2299 2300 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2301 return (struct atom_connector_speed_record *)header; 2302 } 2303 2304 return NULL; 2305 } 2306 2307 static enum bp_result bios_parser_get_connector_speed_cap_info( 2308 struct dc_bios *dcb, 2309 struct graphics_object_id object_id, 2310 struct bp_connector_speed_cap_info *info) 2311 { 2312 struct bios_parser *bp = BP_FROM_DCB(dcb); 2313 struct atom_display_object_path_v3 *object_path_v3; 2314 //struct atom_connector_speed_record *record = NULL; 2315 struct atom_connector_speed_record *record; 2316 2317 if (!info) 2318 return BP_RESULT_BADINPUT; 2319 2320 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2321 2322 if (!object_path_v3) 2323 return BP_RESULT_BADINPUT; 2324 2325 record = get_connector_speed_cap_record(bp, object_path_v3); 2326 if (!record) 2327 return BP_RESULT_NORECORD; 2328 2329 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2330 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2331 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2332 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2333 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2334 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2335 return BP_RESULT_OK; 2336 } 2337 2338 static enum bp_result get_vram_info_v23( 2339 struct bios_parser *bp, 2340 struct dc_vram_info *info) 2341 { 2342 struct atom_vram_info_header_v2_3 *info_v23; 2343 static enum bp_result result = BP_RESULT_OK; 2344 2345 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2346 DATA_TABLES(vram_info)); 2347 2348 if (info_v23 == NULL) 2349 return BP_RESULT_BADBIOSTABLE; 2350 2351 info->num_chans = info_v23->vram_module[0].channel_num; 2352 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2353 2354 return result; 2355 } 2356 2357 static enum bp_result get_vram_info_v24( 2358 struct bios_parser *bp, 2359 struct dc_vram_info *info) 2360 { 2361 struct atom_vram_info_header_v2_4 *info_v24; 2362 static enum bp_result result = BP_RESULT_OK; 2363 2364 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2365 DATA_TABLES(vram_info)); 2366 2367 if (info_v24 == NULL) 2368 return BP_RESULT_BADBIOSTABLE; 2369 2370 info->num_chans = info_v24->vram_module[0].channel_num; 2371 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2372 2373 return result; 2374 } 2375 2376 static enum bp_result get_vram_info_v25( 2377 struct bios_parser *bp, 2378 struct dc_vram_info *info) 2379 { 2380 struct atom_vram_info_header_v2_5 *info_v25; 2381 static enum bp_result result = BP_RESULT_OK; 2382 2383 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2384 DATA_TABLES(vram_info)); 2385 2386 if (info_v25 == NULL) 2387 return BP_RESULT_BADBIOSTABLE; 2388 2389 info->num_chans = info_v25->vram_module[0].channel_num; 2390 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2391 2392 return result; 2393 } 2394 2395 /* 2396 * get_integrated_info_v11 2397 * 2398 * @brief 2399 * Get V8 integrated BIOS information 2400 * 2401 * @param 2402 * bios_parser *bp - [in]BIOS parser handler to get master data table 2403 * integrated_info *info - [out] store and output integrated info 2404 * 2405 * @return 2406 * static enum bp_result - BP_RESULT_OK if information is available, 2407 * BP_RESULT_BADBIOSTABLE otherwise. 2408 */ 2409 static enum bp_result get_integrated_info_v11( 2410 struct bios_parser *bp, 2411 struct integrated_info *info) 2412 { 2413 struct atom_integrated_system_info_v1_11 *info_v11; 2414 uint32_t i; 2415 2416 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2417 DATA_TABLES(integratedsysteminfo)); 2418 2419 if (info_v11 == NULL) 2420 return BP_RESULT_BADBIOSTABLE; 2421 2422 info->gpu_cap_info = 2423 le32_to_cpu(info_v11->gpucapinfo); 2424 /* 2425 * system_config: Bit[0] = 0 : PCIE power gating disabled 2426 * = 1 : PCIE power gating enabled 2427 * Bit[1] = 0 : DDR-PLL shut down disabled 2428 * = 1 : DDR-PLL shut down enabled 2429 * Bit[2] = 0 : DDR-PLL power down disabled 2430 * = 1 : DDR-PLL power down enabled 2431 */ 2432 info->system_config = le32_to_cpu(info_v11->system_config); 2433 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2434 info->memory_type = info_v11->memorytype; 2435 info->ma_channel_number = info_v11->umachannelnumber; 2436 info->lvds_ss_percentage = 2437 le16_to_cpu(info_v11->lvds_ss_percentage); 2438 info->dp_ss_control = 2439 le16_to_cpu(info_v11->reserved1); 2440 info->lvds_sspread_rate_in_10hz = 2441 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2442 info->hdmi_ss_percentage = 2443 le16_to_cpu(info_v11->hdmi_ss_percentage); 2444 info->hdmi_sspread_rate_in_10hz = 2445 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2446 info->dvi_ss_percentage = 2447 le16_to_cpu(info_v11->dvi_ss_percentage); 2448 info->dvi_sspread_rate_in_10_hz = 2449 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2450 info->lvds_misc = info_v11->lvds_misc; 2451 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2452 info->ext_disp_conn_info.gu_id[i] = 2453 info_v11->extdispconninfo.guid[i]; 2454 } 2455 2456 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2457 info->ext_disp_conn_info.path[i].device_connector_id = 2458 object_id_from_bios_object_id( 2459 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2460 2461 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2462 object_id_from_bios_object_id( 2463 le16_to_cpu( 2464 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2465 2466 info->ext_disp_conn_info.path[i].device_tag = 2467 le16_to_cpu( 2468 info_v11->extdispconninfo.path[i].device_tag); 2469 info->ext_disp_conn_info.path[i].device_acpi_enum = 2470 le16_to_cpu( 2471 info_v11->extdispconninfo.path[i].device_acpi_enum); 2472 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2473 info_v11->extdispconninfo.path[i].auxddclut_index; 2474 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2475 info_v11->extdispconninfo.path[i].hpdlut_index; 2476 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2477 info_v11->extdispconninfo.path[i].channelmapping; 2478 info->ext_disp_conn_info.path[i].caps = 2479 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2480 } 2481 info->ext_disp_conn_info.checksum = 2482 info_v11->extdispconninfo.checksum; 2483 2484 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2485 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2486 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2487 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2488 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2489 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2490 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2491 } 2492 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2493 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2494 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2495 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2496 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2497 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2498 } 2499 2500 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2501 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2502 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2503 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2504 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2505 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2506 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2507 } 2508 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2509 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2510 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2511 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2512 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2513 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2514 } 2515 2516 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2517 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2518 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2519 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2520 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2521 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2522 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2523 } 2524 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2525 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2526 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2527 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2528 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2529 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2530 } 2531 2532 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2533 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2534 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2535 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2536 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2537 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2538 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2539 } 2540 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2541 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2542 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2543 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2544 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2545 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2546 } 2547 2548 2549 /** TODO - review **/ 2550 #if 0 2551 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2552 * 10; 2553 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2554 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2555 2556 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2557 /* Convert [10KHz] into [KHz] */ 2558 info->disp_clk_voltage[i].max_supported_clk = 2559 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2560 ulMaximumSupportedCLK) * 10; 2561 info->disp_clk_voltage[i].voltage_index = 2562 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2563 } 2564 2565 info->boot_up_req_display_vector = 2566 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2567 info->boot_up_nb_voltage = 2568 le16_to_cpu(info_v11->usBootUpNBVoltage); 2569 info->ext_disp_conn_info_offset = 2570 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2571 info->gmc_restore_reset_time = 2572 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2573 info->minimum_n_clk = 2574 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2575 for (i = 1; i < 4; ++i) 2576 info->minimum_n_clk = 2577 info->minimum_n_clk < 2578 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2579 info->minimum_n_clk : le32_to_cpu( 2580 info_v11->ulNbpStateNClkFreq[i]); 2581 2582 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2583 info->ddr_dll_power_up_time = 2584 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2585 info->ddr_pll_power_up_time = 2586 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2587 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2588 info->max_lvds_pclk_freq_in_single_link = 2589 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2590 info->max_lvds_pclk_freq_in_single_link = 2591 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2592 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2593 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2594 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2595 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2596 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2597 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2598 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2599 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2600 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2601 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2602 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2603 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2604 info->lvds_off_to_on_delay_in_4ms = 2605 info_v11->ucLVDSOffToOnDelay_in4Ms; 2606 info->lvds_bit_depth_control_val = 2607 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2608 2609 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2610 /* Convert [10KHz] into [KHz] */ 2611 info->avail_s_clk[i].supported_s_clk = 2612 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2613 * 10; 2614 info->avail_s_clk[i].voltage_index = 2615 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2616 info->avail_s_clk[i].voltage_id = 2617 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2618 } 2619 #endif /* TODO*/ 2620 2621 return BP_RESULT_OK; 2622 } 2623 2624 static enum bp_result get_integrated_info_v2_1( 2625 struct bios_parser *bp, 2626 struct integrated_info *info) 2627 { 2628 struct atom_integrated_system_info_v2_1 *info_v2_1; 2629 uint32_t i; 2630 2631 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2632 DATA_TABLES(integratedsysteminfo)); 2633 2634 if (info_v2_1 == NULL) 2635 return BP_RESULT_BADBIOSTABLE; 2636 2637 info->gpu_cap_info = 2638 le32_to_cpu(info_v2_1->gpucapinfo); 2639 /* 2640 * system_config: Bit[0] = 0 : PCIE power gating disabled 2641 * = 1 : PCIE power gating enabled 2642 * Bit[1] = 0 : DDR-PLL shut down disabled 2643 * = 1 : DDR-PLL shut down enabled 2644 * Bit[2] = 0 : DDR-PLL power down disabled 2645 * = 1 : DDR-PLL power down enabled 2646 */ 2647 info->system_config = le32_to_cpu(info_v2_1->system_config); 2648 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2649 info->memory_type = info_v2_1->memorytype; 2650 info->ma_channel_number = info_v2_1->umachannelnumber; 2651 info->dp_ss_control = 2652 le16_to_cpu(info_v2_1->reserved1); 2653 2654 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2655 info->ext_disp_conn_info.gu_id[i] = 2656 info_v2_1->extdispconninfo.guid[i]; 2657 } 2658 2659 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2660 info->ext_disp_conn_info.path[i].device_connector_id = 2661 object_id_from_bios_object_id( 2662 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2663 2664 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2665 object_id_from_bios_object_id( 2666 le16_to_cpu( 2667 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2668 2669 info->ext_disp_conn_info.path[i].device_tag = 2670 le16_to_cpu( 2671 info_v2_1->extdispconninfo.path[i].device_tag); 2672 info->ext_disp_conn_info.path[i].device_acpi_enum = 2673 le16_to_cpu( 2674 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2675 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2676 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2677 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2678 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2679 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2680 info_v2_1->extdispconninfo.path[i].channelmapping; 2681 info->ext_disp_conn_info.path[i].caps = 2682 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2683 } 2684 2685 info->ext_disp_conn_info.checksum = 2686 info_v2_1->extdispconninfo.checksum; 2687 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2688 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2689 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2690 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2691 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2692 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2693 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2694 } 2695 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2696 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2697 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2698 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2699 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2700 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2701 } 2702 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2703 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2704 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2705 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2706 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2707 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2708 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2709 } 2710 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2711 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2712 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2713 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2714 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2715 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2716 } 2717 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2718 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2719 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2720 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2721 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2722 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2723 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2724 } 2725 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2726 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2727 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2728 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2729 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2730 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2731 } 2732 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2733 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2734 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2735 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2736 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2737 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2738 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2739 } 2740 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2741 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2742 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2743 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2744 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2745 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2746 } 2747 2748 info->edp1_info.edp_backlight_pwm_hz = 2749 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2750 info->edp1_info.edp_ss_percentage = 2751 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2752 info->edp1_info.edp_ss_rate_10hz = 2753 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2754 info->edp1_info.edp_pwr_on_off_delay = 2755 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2756 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2757 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2758 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2759 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2760 info->edp1_info.edp_panel_bpc = 2761 info_v2_1->edp1_info.edp_panel_bpc; 2762 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2763 2764 info->edp2_info.edp_backlight_pwm_hz = 2765 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2766 info->edp2_info.edp_ss_percentage = 2767 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2768 info->edp2_info.edp_ss_rate_10hz = 2769 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2770 info->edp2_info.edp_pwr_on_off_delay = 2771 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2772 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2773 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2774 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2775 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2776 info->edp2_info.edp_panel_bpc = 2777 info_v2_1->edp2_info.edp_panel_bpc; 2778 info->edp2_info.edp_bootup_bl_level = 2779 info_v2_1->edp2_info.edp_bootup_bl_level; 2780 2781 return BP_RESULT_OK; 2782 } 2783 2784 static enum bp_result get_integrated_info_v2_2( 2785 struct bios_parser *bp, 2786 struct integrated_info *info) 2787 { 2788 struct atom_integrated_system_info_v2_2 *info_v2_2; 2789 uint32_t i; 2790 2791 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2792 DATA_TABLES(integratedsysteminfo)); 2793 2794 if (info_v2_2 == NULL) 2795 return BP_RESULT_BADBIOSTABLE; 2796 2797 info->gpu_cap_info = 2798 le32_to_cpu(info_v2_2->gpucapinfo); 2799 /* 2800 * system_config: Bit[0] = 0 : PCIE power gating disabled 2801 * = 1 : PCIE power gating enabled 2802 * Bit[1] = 0 : DDR-PLL shut down disabled 2803 * = 1 : DDR-PLL shut down enabled 2804 * Bit[2] = 0 : DDR-PLL power down disabled 2805 * = 1 : DDR-PLL power down enabled 2806 */ 2807 info->system_config = le32_to_cpu(info_v2_2->system_config); 2808 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2809 info->memory_type = info_v2_2->memorytype; 2810 info->ma_channel_number = info_v2_2->umachannelnumber; 2811 info->dp_ss_control = 2812 le16_to_cpu(info_v2_2->reserved1); 2813 2814 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2815 info->ext_disp_conn_info.gu_id[i] = 2816 info_v2_2->extdispconninfo.guid[i]; 2817 } 2818 2819 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2820 info->ext_disp_conn_info.path[i].device_connector_id = 2821 object_id_from_bios_object_id( 2822 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2823 2824 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2825 object_id_from_bios_object_id( 2826 le16_to_cpu( 2827 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2828 2829 info->ext_disp_conn_info.path[i].device_tag = 2830 le16_to_cpu( 2831 info_v2_2->extdispconninfo.path[i].device_tag); 2832 info->ext_disp_conn_info.path[i].device_acpi_enum = 2833 le16_to_cpu( 2834 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2835 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2836 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2837 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2838 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2839 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2840 info_v2_2->extdispconninfo.path[i].channelmapping; 2841 info->ext_disp_conn_info.path[i].caps = 2842 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2843 } 2844 2845 info->ext_disp_conn_info.checksum = 2846 info_v2_2->extdispconninfo.checksum; 2847 info->ext_disp_conn_info.fixdpvoltageswing = 2848 info_v2_2->extdispconninfo.fixdpvoltageswing; 2849 2850 info->edp1_info.edp_backlight_pwm_hz = 2851 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2852 info->edp1_info.edp_ss_percentage = 2853 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2854 info->edp1_info.edp_ss_rate_10hz = 2855 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2856 info->edp1_info.edp_pwr_on_off_delay = 2857 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2858 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2859 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2860 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2861 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2862 info->edp1_info.edp_panel_bpc = 2863 info_v2_2->edp1_info.edp_panel_bpc; 2864 info->edp1_info.edp_bootup_bl_level = 2865 2866 info->edp2_info.edp_backlight_pwm_hz = 2867 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2868 info->edp2_info.edp_ss_percentage = 2869 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2870 info->edp2_info.edp_ss_rate_10hz = 2871 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2872 info->edp2_info.edp_pwr_on_off_delay = 2873 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2874 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2875 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2876 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2877 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2878 info->edp2_info.edp_panel_bpc = 2879 info_v2_2->edp2_info.edp_panel_bpc; 2880 info->edp2_info.edp_bootup_bl_level = 2881 info_v2_2->edp2_info.edp_bootup_bl_level; 2882 2883 return BP_RESULT_OK; 2884 } 2885 2886 /* 2887 * construct_integrated_info 2888 * 2889 * @brief 2890 * Get integrated BIOS information based on table revision 2891 * 2892 * @param 2893 * bios_parser *bp - [in]BIOS parser handler to get master data table 2894 * integrated_info *info - [out] store and output integrated info 2895 * 2896 * @return 2897 * static enum bp_result - BP_RESULT_OK if information is available, 2898 * BP_RESULT_BADBIOSTABLE otherwise. 2899 */ 2900 static enum bp_result construct_integrated_info( 2901 struct bios_parser *bp, 2902 struct integrated_info *info) 2903 { 2904 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2905 2906 struct atom_common_table_header *header; 2907 struct atom_data_revision revision; 2908 2909 struct clock_voltage_caps temp = {0, 0}; 2910 uint32_t i; 2911 uint32_t j; 2912 2913 if (info && DATA_TABLES(integratedsysteminfo)) { 2914 header = GET_IMAGE(struct atom_common_table_header, 2915 DATA_TABLES(integratedsysteminfo)); 2916 2917 get_atom_data_table_revision(header, &revision); 2918 2919 switch (revision.major) { 2920 case 1: 2921 switch (revision.minor) { 2922 case 11: 2923 case 12: 2924 result = get_integrated_info_v11(bp, info); 2925 break; 2926 default: 2927 return result; 2928 } 2929 break; 2930 case 2: 2931 switch (revision.minor) { 2932 case 1: 2933 result = get_integrated_info_v2_1(bp, info); 2934 break; 2935 case 2: 2936 result = get_integrated_info_v2_2(bp, info); 2937 break; 2938 default: 2939 return result; 2940 } 2941 break; 2942 default: 2943 return result; 2944 } 2945 } 2946 2947 if (result != BP_RESULT_OK) 2948 return result; 2949 2950 /* Sort voltage table from low to high*/ 2951 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2952 for (j = i; j > 0; --j) { 2953 if (info->disp_clk_voltage[j].max_supported_clk < 2954 info->disp_clk_voltage[j-1].max_supported_clk 2955 ) { 2956 /* swap j and j - 1*/ 2957 temp = info->disp_clk_voltage[j-1]; 2958 info->disp_clk_voltage[j-1] = 2959 info->disp_clk_voltage[j]; 2960 info->disp_clk_voltage[j] = temp; 2961 } 2962 } 2963 } 2964 2965 return result; 2966 } 2967 2968 static enum bp_result bios_parser_get_vram_info( 2969 struct dc_bios *dcb, 2970 struct dc_vram_info *info) 2971 { 2972 struct bios_parser *bp = BP_FROM_DCB(dcb); 2973 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2974 struct atom_common_table_header *header; 2975 struct atom_data_revision revision; 2976 2977 if (info && DATA_TABLES(vram_info)) { 2978 header = GET_IMAGE(struct atom_common_table_header, 2979 DATA_TABLES(vram_info)); 2980 2981 get_atom_data_table_revision(header, &revision); 2982 2983 switch (revision.major) { 2984 case 2: 2985 switch (revision.minor) { 2986 case 3: 2987 result = get_vram_info_v23(bp, info); 2988 break; 2989 case 4: 2990 result = get_vram_info_v24(bp, info); 2991 break; 2992 case 5: 2993 result = get_vram_info_v25(bp, info); 2994 break; 2995 default: 2996 break; 2997 } 2998 break; 2999 3000 default: 3001 return result; 3002 } 3003 3004 } 3005 return result; 3006 } 3007 3008 static struct integrated_info *bios_parser_create_integrated_info( 3009 struct dc_bios *dcb) 3010 { 3011 struct bios_parser *bp = BP_FROM_DCB(dcb); 3012 struct integrated_info *info = NULL; 3013 3014 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 3015 3016 if (info == NULL) { 3017 ASSERT_CRITICAL(0); 3018 return NULL; 3019 } 3020 3021 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3022 return info; 3023 3024 kfree(info); 3025 3026 return NULL; 3027 } 3028 3029 static enum bp_result update_slot_layout_info( 3030 struct dc_bios *dcb, 3031 unsigned int i, 3032 struct slot_layout_info *slot_layout_info) 3033 { 3034 unsigned int record_offset; 3035 unsigned int j; 3036 struct atom_display_object_path_v2 *object; 3037 struct atom_bracket_layout_record *record; 3038 struct atom_common_record_header *record_header; 3039 static enum bp_result result; 3040 struct bios_parser *bp; 3041 struct object_info_table *tbl; 3042 struct display_object_info_table_v1_4 *v1_4; 3043 3044 record = NULL; 3045 record_header = NULL; 3046 result = BP_RESULT_NORECORD; 3047 3048 bp = BP_FROM_DCB(dcb); 3049 tbl = &bp->object_info_tbl; 3050 v1_4 = tbl->v1_4; 3051 3052 object = &v1_4->display_path[i]; 3053 record_offset = (unsigned int) 3054 (object->disp_recordoffset) + 3055 (unsigned int)(bp->object_info_tbl_offset); 3056 3057 for (;;) { 3058 3059 record_header = (struct atom_common_record_header *) 3060 GET_IMAGE(struct atom_common_record_header, 3061 record_offset); 3062 if (record_header == NULL) { 3063 result = BP_RESULT_BADBIOSTABLE; 3064 break; 3065 } 3066 3067 /* the end of the list */ 3068 if (record_header->record_type == 0xff || 3069 record_header->record_size == 0) { 3070 break; 3071 } 3072 3073 if (record_header->record_type == 3074 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3075 sizeof(struct atom_bracket_layout_record) 3076 <= record_header->record_size) { 3077 record = (struct atom_bracket_layout_record *) 3078 (record_header); 3079 result = BP_RESULT_OK; 3080 break; 3081 } 3082 3083 record_offset += record_header->record_size; 3084 } 3085 3086 /* return if the record not found */ 3087 if (result != BP_RESULT_OK) 3088 return result; 3089 3090 /* get slot sizes */ 3091 slot_layout_info->length = record->bracketlen; 3092 slot_layout_info->width = record->bracketwidth; 3093 3094 /* get info for each connector in the slot */ 3095 slot_layout_info->num_of_connectors = record->conn_num; 3096 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3097 slot_layout_info->connectors[j].connector_type = 3098 (enum connector_layout_type) 3099 (record->conn_info[j].connector_type); 3100 switch (record->conn_info[j].connector_type) { 3101 case CONNECTOR_TYPE_DVI_D: 3102 slot_layout_info->connectors[j].connector_type = 3103 CONNECTOR_LAYOUT_TYPE_DVI_D; 3104 slot_layout_info->connectors[j].length = 3105 CONNECTOR_SIZE_DVI; 3106 break; 3107 3108 case CONNECTOR_TYPE_HDMI: 3109 slot_layout_info->connectors[j].connector_type = 3110 CONNECTOR_LAYOUT_TYPE_HDMI; 3111 slot_layout_info->connectors[j].length = 3112 CONNECTOR_SIZE_HDMI; 3113 break; 3114 3115 case CONNECTOR_TYPE_DISPLAY_PORT: 3116 slot_layout_info->connectors[j].connector_type = 3117 CONNECTOR_LAYOUT_TYPE_DP; 3118 slot_layout_info->connectors[j].length = 3119 CONNECTOR_SIZE_DP; 3120 break; 3121 3122 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3123 slot_layout_info->connectors[j].connector_type = 3124 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3125 slot_layout_info->connectors[j].length = 3126 CONNECTOR_SIZE_MINI_DP; 3127 break; 3128 3129 default: 3130 slot_layout_info->connectors[j].connector_type = 3131 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3132 slot_layout_info->connectors[j].length = 3133 CONNECTOR_SIZE_UNKNOWN; 3134 } 3135 3136 slot_layout_info->connectors[j].position = 3137 record->conn_info[j].position; 3138 slot_layout_info->connectors[j].connector_id = 3139 object_id_from_bios_object_id( 3140 record->conn_info[j].connectorobjid); 3141 } 3142 return result; 3143 } 3144 3145 static enum bp_result update_slot_layout_info_v2( 3146 struct dc_bios *dcb, 3147 unsigned int i, 3148 struct slot_layout_info *slot_layout_info) 3149 { 3150 unsigned int record_offset; 3151 struct atom_display_object_path_v3 *object; 3152 struct atom_bracket_layout_record_v2 *record; 3153 struct atom_common_record_header *record_header; 3154 static enum bp_result result; 3155 struct bios_parser *bp; 3156 struct object_info_table *tbl; 3157 struct display_object_info_table_v1_5 *v1_5; 3158 struct graphics_object_id connector_id; 3159 3160 record = NULL; 3161 record_header = NULL; 3162 result = BP_RESULT_NORECORD; 3163 3164 bp = BP_FROM_DCB(dcb); 3165 tbl = &bp->object_info_tbl; 3166 v1_5 = tbl->v1_5; 3167 3168 object = &v1_5->display_path[i]; 3169 record_offset = (unsigned int) 3170 (object->disp_recordoffset) + 3171 (unsigned int)(bp->object_info_tbl_offset); 3172 3173 for (;;) { 3174 3175 record_header = (struct atom_common_record_header *) 3176 GET_IMAGE(struct atom_common_record_header, 3177 record_offset); 3178 if (record_header == NULL) { 3179 result = BP_RESULT_BADBIOSTABLE; 3180 break; 3181 } 3182 3183 /* the end of the list */ 3184 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3185 record_header->record_size == 0) { 3186 break; 3187 } 3188 3189 if (record_header->record_type == 3190 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3191 sizeof(struct atom_bracket_layout_record_v2) 3192 <= record_header->record_size) { 3193 record = (struct atom_bracket_layout_record_v2 *) 3194 (record_header); 3195 result = BP_RESULT_OK; 3196 break; 3197 } 3198 3199 record_offset += record_header->record_size; 3200 } 3201 3202 /* return if the record not found */ 3203 if (result != BP_RESULT_OK) 3204 return result; 3205 3206 /* get slot sizes */ 3207 connector_id = object_id_from_bios_object_id(object->display_objid); 3208 3209 slot_layout_info->length = record->bracketlen; 3210 slot_layout_info->width = record->bracketwidth; 3211 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3212 slot_layout_info->connectors[i].position = record->conn_num; 3213 slot_layout_info->connectors[i].connector_id = connector_id; 3214 3215 switch (connector_id.id) { 3216 case CONNECTOR_ID_SINGLE_LINK_DVID: 3217 case CONNECTOR_ID_DUAL_LINK_DVID: 3218 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3219 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3220 break; 3221 3222 case CONNECTOR_ID_HDMI_TYPE_A: 3223 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3224 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3225 break; 3226 3227 case CONNECTOR_ID_DISPLAY_PORT: 3228 case CONNECTOR_ID_USBC: 3229 if (record->mini_type == MINI_TYPE_NORMAL) { 3230 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3231 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3232 } else { 3233 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3234 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3235 } 3236 break; 3237 3238 default: 3239 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3240 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3241 } 3242 return result; 3243 } 3244 3245 static enum bp_result get_bracket_layout_record( 3246 struct dc_bios *dcb, 3247 unsigned int bracket_layout_id, 3248 struct slot_layout_info *slot_layout_info) 3249 { 3250 unsigned int i; 3251 struct bios_parser *bp = BP_FROM_DCB(dcb); 3252 static enum bp_result result; 3253 struct object_info_table *tbl; 3254 struct display_object_info_table_v1_4 *v1_4; 3255 struct display_object_info_table_v1_5 *v1_5; 3256 3257 if (slot_layout_info == NULL) { 3258 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3259 return BP_RESULT_BADINPUT; 3260 } 3261 tbl = &bp->object_info_tbl; 3262 v1_4 = tbl->v1_4; 3263 v1_5 = tbl->v1_5; 3264 3265 result = BP_RESULT_NORECORD; 3266 switch (bp->object_info_tbl.revision.minor) { 3267 case 4: 3268 default: 3269 for (i = 0; i < v1_4->number_of_path; ++i) { 3270 if (bracket_layout_id == 3271 v1_4->display_path[i].display_objid) { 3272 result = update_slot_layout_info(dcb, i, slot_layout_info); 3273 break; 3274 } 3275 } 3276 break; 3277 case 5: 3278 for (i = 0; i < v1_5->number_of_path; ++i) 3279 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3280 break; 3281 } 3282 return result; 3283 } 3284 3285 static enum bp_result bios_get_board_layout_info( 3286 struct dc_bios *dcb, 3287 struct board_layout_info *board_layout_info) 3288 { 3289 unsigned int i; 3290 3291 struct bios_parser *bp; 3292 3293 static enum bp_result record_result; 3294 3295 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3296 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3297 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3298 0, 0 3299 }; 3300 3301 3302 bp = BP_FROM_DCB(dcb); 3303 3304 if (board_layout_info == NULL) { 3305 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3306 return BP_RESULT_BADINPUT; 3307 } 3308 3309 board_layout_info->num_of_slots = 0; 3310 3311 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 3312 record_result = get_bracket_layout_record(dcb, 3313 slot_index_to_vbios_id[i], 3314 &board_layout_info->slots[i]); 3315 3316 if (record_result == BP_RESULT_NORECORD && i > 0) 3317 break; /* no more slots present in bios */ 3318 else if (record_result != BP_RESULT_OK) 3319 return record_result; /* fail */ 3320 3321 ++board_layout_info->num_of_slots; 3322 } 3323 3324 /* all data is valid */ 3325 board_layout_info->is_number_of_slots_valid = 1; 3326 board_layout_info->is_slots_size_valid = 1; 3327 board_layout_info->is_connector_offsets_valid = 1; 3328 board_layout_info->is_connector_lengths_valid = 1; 3329 3330 return BP_RESULT_OK; 3331 } 3332 3333 3334 static uint16_t bios_parser_pack_data_tables( 3335 struct dc_bios *dcb, 3336 void *dst) 3337 { 3338 // TODO: There is data bytes alignment issue, disable it for now. 3339 return 0; 3340 } 3341 3342 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3343 struct bios_parser *bp, 3344 uint32_t rev_major, 3345 uint32_t rev_minor, 3346 uint16_t *dc_golden_table_ver) 3347 { 3348 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3349 uint32_t dc_golden_offset = 0; 3350 *dc_golden_table_ver = 0; 3351 3352 if (!DATA_TABLES(dce_info)) 3353 return NULL; 3354 3355 /* ver.4.4 or higher */ 3356 switch (rev_major) { 3357 case 4: 3358 switch (rev_minor) { 3359 case 4: 3360 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3361 DATA_TABLES(dce_info)); 3362 if (!disp_cntl_tbl_4_4) 3363 return NULL; 3364 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3365 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3366 break; 3367 case 5: 3368 default: 3369 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3370 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3371 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3372 */ 3373 break; 3374 } 3375 break; 3376 } 3377 3378 if (!dc_golden_offset) 3379 return NULL; 3380 3381 if (*dc_golden_table_ver != 1) 3382 return NULL; 3383 3384 return GET_IMAGE(struct atom_dc_golden_table_v1, 3385 dc_golden_offset); 3386 } 3387 3388 static enum bp_result bios_get_atom_dc_golden_table( 3389 struct dc_bios *dcb) 3390 { 3391 struct bios_parser *bp = BP_FROM_DCB(dcb); 3392 enum bp_result result = BP_RESULT_OK; 3393 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3394 struct atom_common_table_header *header; 3395 struct atom_data_revision tbl_revision; 3396 uint16_t dc_golden_table_ver = 0; 3397 3398 header = GET_IMAGE(struct atom_common_table_header, 3399 DATA_TABLES(dce_info)); 3400 if (!header) 3401 return BP_RESULT_UNSUPPORTED; 3402 3403 get_atom_data_table_revision(header, &tbl_revision); 3404 3405 atom_dc_golden_table = bios_get_golden_table(bp, 3406 tbl_revision.major, 3407 tbl_revision.minor, 3408 &dc_golden_table_ver); 3409 3410 if (!atom_dc_golden_table) 3411 return BP_RESULT_UNSUPPORTED; 3412 3413 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3414 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3415 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3416 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3417 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3418 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3419 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3420 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3421 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3422 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3423 3424 return result; 3425 } 3426 3427 3428 static const struct dc_vbios_funcs vbios_funcs = { 3429 .get_connectors_number = bios_parser_get_connectors_number, 3430 3431 .get_connector_id = bios_parser_get_connector_id, 3432 3433 .get_src_obj = bios_parser_get_src_obj, 3434 3435 .get_i2c_info = bios_parser_get_i2c_info, 3436 3437 .get_hpd_info = bios_parser_get_hpd_info, 3438 3439 .get_device_tag = bios_parser_get_device_tag, 3440 3441 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3442 3443 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3444 3445 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3446 3447 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3448 3449 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3450 3451 .is_device_id_supported = bios_parser_is_device_id_supported, 3452 3453 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3454 3455 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3456 3457 3458 /* COMMANDS */ 3459 .encoder_control = bios_parser_encoder_control, 3460 3461 .transmitter_control = bios_parser_transmitter_control, 3462 3463 .enable_crtc = bios_parser_enable_crtc, 3464 3465 .set_pixel_clock = bios_parser_set_pixel_clock, 3466 3467 .set_dce_clock = bios_parser_set_dce_clock, 3468 3469 .program_crtc_timing = bios_parser_program_crtc_timing, 3470 3471 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3472 3473 .bios_parser_destroy = firmware_parser_destroy, 3474 3475 .get_board_layout_info = bios_get_board_layout_info, 3476 /* TODO: use this fn in hw init?*/ 3477 .pack_data_tables = bios_parser_pack_data_tables, 3478 3479 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3480 3481 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3482 3483 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3484 3485 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3486 3487 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3488 3489 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3490 3491 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3492 }; 3493 3494 static bool bios_parser2_construct( 3495 struct bios_parser *bp, 3496 struct bp_init_data *init, 3497 enum dce_version dce_version) 3498 { 3499 uint16_t *rom_header_offset = NULL; 3500 struct atom_rom_header_v2_2 *rom_header = NULL; 3501 struct display_object_info_table_v1_4 *object_info_tbl; 3502 struct atom_data_revision tbl_rev = {0}; 3503 3504 if (!init) 3505 return false; 3506 3507 if (!init->bios) 3508 return false; 3509 3510 bp->base.funcs = &vbios_funcs; 3511 bp->base.bios = init->bios; 3512 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3513 3514 bp->base.ctx = init->ctx; 3515 3516 bp->base.bios_local_image = NULL; 3517 3518 rom_header_offset = 3519 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3520 3521 if (!rom_header_offset) 3522 return false; 3523 3524 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3525 3526 if (!rom_header) 3527 return false; 3528 3529 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3530 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3531 return false; 3532 3533 bp->master_data_tbl = 3534 GET_IMAGE(struct atom_master_data_table_v2_1, 3535 rom_header->masterdatatable_offset); 3536 3537 if (!bp->master_data_tbl) 3538 return false; 3539 3540 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3541 3542 if (!bp->object_info_tbl_offset) 3543 return false; 3544 3545 object_info_tbl = 3546 GET_IMAGE(struct display_object_info_table_v1_4, 3547 bp->object_info_tbl_offset); 3548 3549 if (!object_info_tbl) 3550 return false; 3551 3552 get_atom_data_table_revision(&object_info_tbl->table_header, 3553 &bp->object_info_tbl.revision); 3554 3555 if (bp->object_info_tbl.revision.major == 1 3556 && bp->object_info_tbl.revision.minor == 4) { 3557 struct display_object_info_table_v1_4 *tbl_v1_4; 3558 3559 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3560 bp->object_info_tbl_offset); 3561 if (!tbl_v1_4) 3562 return false; 3563 3564 bp->object_info_tbl.v1_4 = tbl_v1_4; 3565 } else if (bp->object_info_tbl.revision.major == 1 3566 && bp->object_info_tbl.revision.minor == 5) { 3567 struct display_object_info_table_v1_5 *tbl_v1_5; 3568 3569 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3570 bp->object_info_tbl_offset); 3571 if (!tbl_v1_5) 3572 return false; 3573 3574 bp->object_info_tbl.v1_5 = tbl_v1_5; 3575 } else { 3576 ASSERT(0); 3577 return false; 3578 } 3579 3580 dal_firmware_parser_init_cmd_tbl(bp); 3581 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3582 3583 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3584 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3585 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3586 3587 return true; 3588 } 3589 3590 struct dc_bios *firmware_parser_create( 3591 struct bp_init_data *init, 3592 enum dce_version dce_version) 3593 { 3594 struct bios_parser *bp = NULL; 3595 3596 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 3597 if (!bp) 3598 return NULL; 3599 3600 if (bios_parser2_construct(bp, init, dce_version)) 3601 return &bp->base; 3602 3603 kfree(bp); 3604 return NULL; 3605 } 3606 3607 3608