1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "core_types.h" 28 29 #include "ObjectID.h" 30 #include "atomfirmware.h" 31 32 #include "dc_bios_types.h" 33 #include "include/grph_object_ctrl_defs.h" 34 #include "include/bios_parser_interface.h" 35 #include "include/logger_interface.h" 36 37 #include "command_table2.h" 38 39 #include "bios_parser_helper.h" 40 #include "command_table_helper2.h" 41 #include "bios_parser2.h" 42 #include "bios_parser_types_internal2.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 #define DC_LOGGER \ 48 bp->base.ctx->logger 49 50 #define LAST_RECORD_TYPE 0xff 51 #define SMU9_SYSPLL0_ID 0 52 53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 54 struct atom_i2c_record *record, 55 struct graphics_object_i2c_info *info); 56 57 static enum bp_result bios_parser_get_firmware_info( 58 struct dc_bios *dcb, 59 struct dc_firmware_info *info); 60 61 static enum bp_result bios_parser_get_encoder_cap_info( 62 struct dc_bios *dcb, 63 struct graphics_object_id object_id, 64 struct bp_encoder_cap_info *info); 65 66 static enum bp_result get_firmware_info_v3_1( 67 struct bios_parser *bp, 68 struct dc_firmware_info *info); 69 70 static enum bp_result get_firmware_info_v3_2( 71 struct bios_parser *bp, 72 struct dc_firmware_info *info); 73 74 static enum bp_result get_firmware_info_v3_4( 75 struct bios_parser *bp, 76 struct dc_firmware_info *info); 77 78 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 79 struct atom_display_object_path_v2 *object); 80 81 static struct atom_encoder_caps_record *get_encoder_cap_record( 82 struct bios_parser *bp, 83 struct atom_display_object_path_v2 *object); 84 85 #define BIOS_IMAGE_SIZE_OFFSET 2 86 #define BIOS_IMAGE_SIZE_UNIT 512 87 88 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 89 90 static void bios_parser2_destruct(struct bios_parser *bp) 91 { 92 kfree(bp->base.bios_local_image); 93 kfree(bp->base.integrated_info); 94 } 95 96 static void firmware_parser_destroy(struct dc_bios **dcb) 97 { 98 struct bios_parser *bp = BP_FROM_DCB(*dcb); 99 100 if (!bp) { 101 BREAK_TO_DEBUGGER(); 102 return; 103 } 104 105 bios_parser2_destruct(bp); 106 107 kfree(bp); 108 *dcb = NULL; 109 } 110 111 static void get_atom_data_table_revision( 112 struct atom_common_table_header *atom_data_tbl, 113 struct atom_data_revision *tbl_revision) 114 { 115 if (!tbl_revision) 116 return; 117 118 /* initialize the revision to 0 which is invalid revision */ 119 tbl_revision->major = 0; 120 tbl_revision->minor = 0; 121 122 if (!atom_data_tbl) 123 return; 124 125 tbl_revision->major = 126 (uint32_t) atom_data_tbl->format_revision & 0x3f; 127 tbl_revision->minor = 128 (uint32_t) atom_data_tbl->content_revision & 0x3f; 129 } 130 131 /* BIOS oject table displaypath is per connector. 132 * There is extra path not for connector. BIOS fill its encoderid as 0 133 */ 134 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 135 { 136 struct bios_parser *bp = BP_FROM_DCB(dcb); 137 unsigned int count = 0; 138 unsigned int i; 139 140 switch (bp->object_info_tbl.revision.minor) { 141 default: 142 case 4: 143 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) 144 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 145 count++; 146 147 break; 148 149 case 5: 150 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) 151 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0) 152 count++; 153 154 break; 155 } 156 return count; 157 } 158 159 static struct graphics_object_id bios_parser_get_connector_id( 160 struct dc_bios *dcb, 161 uint8_t i) 162 { 163 struct bios_parser *bp = BP_FROM_DCB(dcb); 164 struct graphics_object_id object_id = dal_graphics_object_id_init( 165 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 166 struct object_info_table *tbl = &bp->object_info_tbl; 167 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 168 169 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5; 170 171 switch (bp->object_info_tbl.revision.minor) { 172 default: 173 case 4: 174 if (v1_4->number_of_path > i) { 175 /* If display_objid is generic object id, the encoderObj 176 * /extencoderobjId should be 0 177 */ 178 if (v1_4->display_path[i].encoderobjid != 0 && 179 v1_4->display_path[i].display_objid != 0) 180 object_id = object_id_from_bios_object_id( 181 v1_4->display_path[i].display_objid); 182 } 183 break; 184 185 case 5: 186 if (v1_5->number_of_path > i) { 187 /* If display_objid is generic object id, the encoderObjId 188 * should be 0 189 */ 190 if (v1_5->display_path[i].encoderobjid != 0 && 191 v1_5->display_path[i].display_objid != 0) 192 object_id = object_id_from_bios_object_id( 193 v1_5->display_path[i].display_objid); 194 } 195 break; 196 } 197 return object_id; 198 } 199 200 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 201 struct graphics_object_id object_id, uint32_t index, 202 struct graphics_object_id *src_object_id) 203 { 204 struct bios_parser *bp = BP_FROM_DCB(dcb); 205 unsigned int i; 206 enum bp_result bp_result = BP_RESULT_BADINPUT; 207 struct graphics_object_id obj_id = { 0 }; 208 struct object_info_table *tbl = &bp->object_info_tbl; 209 210 if (!src_object_id) 211 return bp_result; 212 213 switch (object_id.type) { 214 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 215 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 216 */ 217 case OBJECT_TYPE_ENCODER: 218 /* TODO: since num of src must be less than 2. 219 * If found in for loop, should break. 220 * DAL2 implementation may be changed too 221 */ 222 switch (bp->object_info_tbl.revision.minor) { 223 default: 224 case 4: 225 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 226 obj_id = object_id_from_bios_object_id( 227 tbl->v1_4->display_path[i].encoderobjid); 228 if (object_id.type == obj_id.type && 229 object_id.id == obj_id.id && 230 object_id.enum_id == obj_id.enum_id) { 231 *src_object_id = 232 object_id_from_bios_object_id( 233 0x1100); 234 /* break; */ 235 } 236 } 237 bp_result = BP_RESULT_OK; 238 break; 239 240 case 5: 241 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 242 obj_id = object_id_from_bios_object_id( 243 tbl->v1_5->display_path[i].encoderobjid); 244 if (object_id.type == obj_id.type && 245 object_id.id == obj_id.id && 246 object_id.enum_id == obj_id.enum_id) { 247 *src_object_id = 248 object_id_from_bios_object_id( 249 0x1100); 250 /* break; */ 251 } 252 } 253 bp_result = BP_RESULT_OK; 254 break; 255 } 256 break; 257 case OBJECT_TYPE_CONNECTOR: 258 switch (bp->object_info_tbl.revision.minor) { 259 default: 260 case 4: 261 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 262 obj_id = object_id_from_bios_object_id( 263 tbl->v1_4->display_path[i] 264 .display_objid); 265 266 if (object_id.type == obj_id.type && 267 object_id.id == obj_id.id && 268 object_id.enum_id == obj_id.enum_id) { 269 *src_object_id = 270 object_id_from_bios_object_id( 271 tbl->v1_4 272 ->display_path[i] 273 .encoderobjid); 274 /* break; */ 275 } 276 } 277 bp_result = BP_RESULT_OK; 278 break; 279 } 280 bp_result = BP_RESULT_OK; 281 break; 282 case 5: 283 for (i = 0; i < tbl->v1_5->number_of_path; i++) { 284 obj_id = object_id_from_bios_object_id( 285 tbl->v1_5->display_path[i].display_objid); 286 287 if (object_id.type == obj_id.type && 288 object_id.id == obj_id.id && 289 object_id.enum_id == obj_id.enum_id) { 290 *src_object_id = object_id_from_bios_object_id( 291 tbl->v1_5->display_path[i].encoderobjid); 292 /* break; */ 293 } 294 } 295 bp_result = BP_RESULT_OK; 296 break; 297 298 default: 299 bp_result = BP_RESULT_OK; 300 break; 301 } 302 303 return bp_result; 304 } 305 306 /* from graphics_object_id, find display path which includes the object_id */ 307 static struct atom_display_object_path_v2 *get_bios_object( 308 struct bios_parser *bp, 309 struct graphics_object_id id) 310 { 311 unsigned int i; 312 struct graphics_object_id obj_id = {0}; 313 314 switch (id.type) { 315 case OBJECT_TYPE_ENCODER: 316 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 317 obj_id = object_id_from_bios_object_id( 318 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 319 if (id.type == obj_id.type && id.id == obj_id.id 320 && id.enum_id == obj_id.enum_id) 321 return &bp->object_info_tbl.v1_4->display_path[i]; 322 } 323 fallthrough; 324 case OBJECT_TYPE_CONNECTOR: 325 case OBJECT_TYPE_GENERIC: 326 /* Both Generic and Connector Object ID 327 * will be stored on display_objid 328 */ 329 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 330 obj_id = object_id_from_bios_object_id( 331 bp->object_info_tbl.v1_4->display_path[i].display_objid); 332 if (id.type == obj_id.type && id.id == obj_id.id 333 && id.enum_id == obj_id.enum_id) 334 return &bp->object_info_tbl.v1_4->display_path[i]; 335 } 336 fallthrough; 337 default: 338 return NULL; 339 } 340 } 341 342 /* from graphics_object_id, find display path which includes the object_id */ 343 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3( 344 struct bios_parser *bp, 345 struct graphics_object_id id) 346 { 347 unsigned int i; 348 struct graphics_object_id obj_id = {0}; 349 350 switch (id.type) { 351 case OBJECT_TYPE_ENCODER: 352 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 353 obj_id = object_id_from_bios_object_id( 354 bp->object_info_tbl.v1_5->display_path[i].encoderobjid); 355 if (id.type == obj_id.type && id.id == obj_id.id 356 && id.enum_id == obj_id.enum_id) 357 return &bp->object_info_tbl.v1_5->display_path[i]; 358 } 359 break; 360 361 case OBJECT_TYPE_CONNECTOR: 362 case OBJECT_TYPE_GENERIC: 363 /* Both Generic and Connector Object ID 364 * will be stored on display_objid 365 */ 366 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) { 367 obj_id = object_id_from_bios_object_id( 368 bp->object_info_tbl.v1_5->display_path[i].display_objid); 369 if (id.type == obj_id.type && id.id == obj_id.id 370 && id.enum_id == obj_id.enum_id) 371 return &bp->object_info_tbl.v1_5->display_path[i]; 372 } 373 break; 374 375 default: 376 return NULL; 377 } 378 379 return NULL; 380 } 381 382 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 383 struct graphics_object_id id, 384 struct graphics_object_i2c_info *info) 385 { 386 uint32_t offset; 387 struct atom_display_object_path_v2 *object; 388 389 struct atom_display_object_path_v3 *object_path_v3; 390 391 struct atom_common_record_header *header; 392 struct atom_i2c_record *record; 393 struct atom_i2c_record dummy_record = {0}; 394 struct bios_parser *bp = BP_FROM_DCB(dcb); 395 396 if (!info) 397 return BP_RESULT_BADINPUT; 398 399 if (id.type == OBJECT_TYPE_GENERIC) { 400 dummy_record.i2c_id = id.id; 401 402 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 403 return BP_RESULT_OK; 404 else 405 return BP_RESULT_NORECORD; 406 } 407 408 switch (bp->object_info_tbl.revision.minor) { 409 case 4: 410 default: 411 object = get_bios_object(bp, id); 412 413 if (!object) 414 return BP_RESULT_BADINPUT; 415 416 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 417 break; 418 case 5: 419 object_path_v3 = get_bios_object_from_path_v3(bp, id); 420 421 if (!object_path_v3) 422 return BP_RESULT_BADINPUT; 423 424 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset; 425 break; 426 } 427 428 for (;;) { 429 header = GET_IMAGE(struct atom_common_record_header, offset); 430 431 if (!header) 432 return BP_RESULT_BADBIOSTABLE; 433 434 if (header->record_type == LAST_RECORD_TYPE || 435 !header->record_size) 436 break; 437 438 if (header->record_type == ATOM_I2C_RECORD_TYPE 439 && sizeof(struct atom_i2c_record) <= 440 header->record_size) { 441 /* get the I2C info */ 442 record = (struct atom_i2c_record *) header; 443 444 if (get_gpio_i2c_info(bp, record, info) == 445 BP_RESULT_OK) 446 return BP_RESULT_OK; 447 } 448 449 offset += header->record_size; 450 } 451 452 return BP_RESULT_NORECORD; 453 } 454 455 static enum bp_result get_gpio_i2c_info( 456 struct bios_parser *bp, 457 struct atom_i2c_record *record, 458 struct graphics_object_i2c_info *info) 459 { 460 struct atom_gpio_pin_lut_v2_1 *header; 461 uint32_t count = 0; 462 unsigned int table_index = 0; 463 bool find_valid = false; 464 struct atom_gpio_pin_assignment *pin; 465 466 if (!info) 467 return BP_RESULT_BADINPUT; 468 469 /* get the GPIO_I2C info */ 470 if (!DATA_TABLES(gpio_pin_lut)) 471 return BP_RESULT_BADBIOSTABLE; 472 473 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 474 DATA_TABLES(gpio_pin_lut)); 475 if (!header) 476 return BP_RESULT_BADBIOSTABLE; 477 478 if (sizeof(struct atom_common_table_header) + 479 sizeof(struct atom_gpio_pin_assignment) > 480 le16_to_cpu(header->table_header.structuresize)) 481 return BP_RESULT_BADBIOSTABLE; 482 483 /* TODO: is version change? */ 484 if (header->table_header.content_revision != 1) 485 return BP_RESULT_UNSUPPORTED; 486 487 /* get data count */ 488 count = (le16_to_cpu(header->table_header.structuresize) 489 - sizeof(struct atom_common_table_header)) 490 / sizeof(struct atom_gpio_pin_assignment); 491 492 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin; 493 494 for (table_index = 0; table_index < count; table_index++) { 495 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) && 496 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) && 497 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) { 498 /* still valid */ 499 find_valid = true; 500 break; 501 } 502 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment)); 503 } 504 505 /* If we don't find the entry that we are looking for then 506 * we will return BP_Result_BadBiosTable. 507 */ 508 if (find_valid == false) 509 return BP_RESULT_BADBIOSTABLE; 510 511 /* get the GPIO_I2C_INFO */ 512 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 513 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 514 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 515 info->i2c_slave_address = record->i2c_slave_addr; 516 517 /* TODO: check how to get register offset for en, Y, etc. */ 518 info->gpio_info.clk_a_register_index = 519 le16_to_cpu( 520 header->gpio_pin[table_index].data_a_reg_index); 521 info->gpio_info.clk_a_shift = 522 header->gpio_pin[table_index].gpio_bitshift; 523 524 return BP_RESULT_OK; 525 } 526 527 static struct atom_hpd_int_record *get_hpd_record_for_path_v3( 528 struct bios_parser *bp, 529 struct atom_display_object_path_v3 *object) 530 { 531 struct atom_common_record_header *header; 532 uint32_t offset; 533 534 if (!object) { 535 BREAK_TO_DEBUGGER(); /* Invalid object */ 536 return NULL; 537 } 538 539 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 540 541 for (;;) { 542 header = GET_IMAGE(struct atom_common_record_header, offset); 543 544 if (!header) 545 return NULL; 546 547 if (header->record_type == ATOM_RECORD_END_TYPE || 548 !header->record_size) 549 break; 550 551 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 552 && sizeof(struct atom_hpd_int_record) <= 553 header->record_size) 554 return (struct atom_hpd_int_record *) header; 555 556 offset += header->record_size; 557 } 558 559 return NULL; 560 } 561 562 static enum bp_result bios_parser_get_hpd_info( 563 struct dc_bios *dcb, 564 struct graphics_object_id id, 565 struct graphics_object_hpd_info *info) 566 { 567 struct bios_parser *bp = BP_FROM_DCB(dcb); 568 struct atom_display_object_path_v2 *object; 569 struct atom_display_object_path_v3 *object_path_v3; 570 struct atom_hpd_int_record *record = NULL; 571 572 if (!info) 573 return BP_RESULT_BADINPUT; 574 575 switch (bp->object_info_tbl.revision.minor) { 576 case 4: 577 default: 578 object = get_bios_object(bp, id); 579 580 if (!object) 581 return BP_RESULT_BADINPUT; 582 583 record = get_hpd_record(bp, object); 584 585 break; 586 case 5: 587 object_path_v3 = get_bios_object_from_path_v3(bp, id); 588 589 if (!object_path_v3) 590 return BP_RESULT_BADINPUT; 591 592 record = get_hpd_record_for_path_v3(bp, object_path_v3); 593 break; 594 } 595 596 if (record != NULL) { 597 info->hpd_int_gpio_uid = record->pin_id; 598 info->hpd_active = record->plugin_pin_state; 599 return BP_RESULT_OK; 600 } 601 602 return BP_RESULT_NORECORD; 603 } 604 605 static struct atom_hpd_int_record *get_hpd_record( 606 struct bios_parser *bp, 607 struct atom_display_object_path_v2 *object) 608 { 609 struct atom_common_record_header *header; 610 uint32_t offset; 611 612 if (!object) { 613 BREAK_TO_DEBUGGER(); /* Invalid object */ 614 return NULL; 615 } 616 617 offset = le16_to_cpu(object->disp_recordoffset) 618 + bp->object_info_tbl_offset; 619 620 for (;;) { 621 header = GET_IMAGE(struct atom_common_record_header, offset); 622 623 if (!header) 624 return NULL; 625 626 if (header->record_type == LAST_RECORD_TYPE || 627 !header->record_size) 628 break; 629 630 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 631 && sizeof(struct atom_hpd_int_record) <= 632 header->record_size) 633 return (struct atom_hpd_int_record *) header; 634 635 offset += header->record_size; 636 } 637 638 return NULL; 639 } 640 641 /** 642 * bios_parser_get_gpio_pin_info 643 * Get GpioPin information of input gpio id 644 * 645 * @dcb: pointer to the DC BIOS 646 * @gpio_id: GPIO ID 647 * @info: GpioPin information structure 648 * return: Bios parser result code 649 * note: 650 * to get the GPIO PIN INFO, we need: 651 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 652 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 653 * to get the registerA offset/mask 654 */ 655 static enum bp_result bios_parser_get_gpio_pin_info( 656 struct dc_bios *dcb, 657 uint32_t gpio_id, 658 struct gpio_pin_info *info) 659 { 660 struct bios_parser *bp = BP_FROM_DCB(dcb); 661 struct atom_gpio_pin_lut_v2_1 *header; 662 uint32_t count = 0; 663 uint32_t i = 0; 664 665 if (!DATA_TABLES(gpio_pin_lut)) 666 return BP_RESULT_BADBIOSTABLE; 667 668 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 669 DATA_TABLES(gpio_pin_lut)); 670 if (!header) 671 return BP_RESULT_BADBIOSTABLE; 672 673 if (sizeof(struct atom_common_table_header) + 674 sizeof(struct atom_gpio_pin_assignment) 675 > le16_to_cpu(header->table_header.structuresize)) 676 return BP_RESULT_BADBIOSTABLE; 677 678 if (header->table_header.content_revision != 1) 679 return BP_RESULT_UNSUPPORTED; 680 681 /* Temporary hard code gpio pin info */ 682 count = (le16_to_cpu(header->table_header.structuresize) 683 - sizeof(struct atom_common_table_header)) 684 / sizeof(struct atom_gpio_pin_assignment); 685 for (i = 0; i < count; ++i) { 686 if (header->gpio_pin[i].gpio_id != gpio_id) 687 continue; 688 689 info->offset = 690 (uint32_t) le16_to_cpu( 691 header->gpio_pin[i].data_a_reg_index); 692 info->offset_y = info->offset + 2; 693 info->offset_en = info->offset + 1; 694 info->offset_mask = info->offset - 1; 695 696 info->mask = (uint32_t) (1 << 697 header->gpio_pin[i].gpio_bitshift); 698 info->mask_y = info->mask + 2; 699 info->mask_en = info->mask + 1; 700 info->mask_mask = info->mask - 1; 701 702 return BP_RESULT_OK; 703 } 704 705 return BP_RESULT_NORECORD; 706 } 707 708 static struct device_id device_type_from_device_id(uint16_t device_id) 709 { 710 711 struct device_id result_device_id; 712 713 result_device_id.raw_device_tag = device_id; 714 715 switch (device_id) { 716 case ATOM_DISPLAY_LCD1_SUPPORT: 717 result_device_id.device_type = DEVICE_TYPE_LCD; 718 result_device_id.enum_id = 1; 719 break; 720 721 case ATOM_DISPLAY_LCD2_SUPPORT: 722 result_device_id.device_type = DEVICE_TYPE_LCD; 723 result_device_id.enum_id = 2; 724 break; 725 726 case ATOM_DISPLAY_DFP1_SUPPORT: 727 result_device_id.device_type = DEVICE_TYPE_DFP; 728 result_device_id.enum_id = 1; 729 break; 730 731 case ATOM_DISPLAY_DFP2_SUPPORT: 732 result_device_id.device_type = DEVICE_TYPE_DFP; 733 result_device_id.enum_id = 2; 734 break; 735 736 case ATOM_DISPLAY_DFP3_SUPPORT: 737 result_device_id.device_type = DEVICE_TYPE_DFP; 738 result_device_id.enum_id = 3; 739 break; 740 741 case ATOM_DISPLAY_DFP4_SUPPORT: 742 result_device_id.device_type = DEVICE_TYPE_DFP; 743 result_device_id.enum_id = 4; 744 break; 745 746 case ATOM_DISPLAY_DFP5_SUPPORT: 747 result_device_id.device_type = DEVICE_TYPE_DFP; 748 result_device_id.enum_id = 5; 749 break; 750 751 case ATOM_DISPLAY_DFP6_SUPPORT: 752 result_device_id.device_type = DEVICE_TYPE_DFP; 753 result_device_id.enum_id = 6; 754 break; 755 756 default: 757 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 758 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 759 result_device_id.enum_id = 0; 760 } 761 return result_device_id; 762 } 763 764 static enum bp_result bios_parser_get_device_tag( 765 struct dc_bios *dcb, 766 struct graphics_object_id connector_object_id, 767 uint32_t device_tag_index, 768 struct connector_device_tag_info *info) 769 { 770 struct bios_parser *bp = BP_FROM_DCB(dcb); 771 struct atom_display_object_path_v2 *object; 772 773 struct atom_display_object_path_v3 *object_path_v3; 774 775 776 if (!info) 777 return BP_RESULT_BADINPUT; 778 779 switch (bp->object_info_tbl.revision.minor) { 780 case 4: 781 default: 782 /* getBiosObject will return MXM object */ 783 object = get_bios_object(bp, connector_object_id); 784 785 if (!object) { 786 BREAK_TO_DEBUGGER(); /* Invalid object id */ 787 return BP_RESULT_BADINPUT; 788 } 789 790 info->acpi_device = 0; /* BIOS no longer provides this */ 791 info->dev_id = device_type_from_device_id(object->device_tag); 792 break; 793 case 5: 794 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id); 795 796 if (!object_path_v3) { 797 BREAK_TO_DEBUGGER(); /* Invalid object id */ 798 return BP_RESULT_BADINPUT; 799 } 800 info->acpi_device = 0; /* BIOS no longer provides this */ 801 info->dev_id = device_type_from_device_id(object_path_v3->device_tag); 802 break; 803 } 804 805 return BP_RESULT_OK; 806 } 807 808 static enum bp_result get_ss_info_v4_1( 809 struct bios_parser *bp, 810 uint32_t id, 811 uint32_t index, 812 struct spread_spectrum_info *ss_info) 813 { 814 enum bp_result result = BP_RESULT_OK; 815 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 816 struct atom_smu_info_v3_3 *smu_info = NULL; 817 818 if (!ss_info) 819 return BP_RESULT_BADINPUT; 820 821 if (!DATA_TABLES(dce_info)) 822 return BP_RESULT_BADBIOSTABLE; 823 824 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 825 DATA_TABLES(dce_info)); 826 if (!disp_cntl_tbl) 827 return BP_RESULT_BADBIOSTABLE; 828 829 830 ss_info->type.STEP_AND_DELAY_INFO = false; 831 ss_info->spread_percentage_divider = 1000; 832 /* BIOS no longer uses target clock. Always enable for now */ 833 ss_info->target_clock_range = 0xffffffff; 834 835 switch (id) { 836 case AS_SIGNAL_TYPE_DVI: 837 ss_info->spread_spectrum_percentage = 838 disp_cntl_tbl->dvi_ss_percentage; 839 ss_info->spread_spectrum_range = 840 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 841 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 842 ss_info->type.CENTER_MODE = true; 843 844 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 845 break; 846 case AS_SIGNAL_TYPE_HDMI: 847 ss_info->spread_spectrum_percentage = 848 disp_cntl_tbl->hdmi_ss_percentage; 849 ss_info->spread_spectrum_range = 850 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 851 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 852 ss_info->type.CENTER_MODE = true; 853 854 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 855 break; 856 /* TODO LVDS not support anymore? */ 857 case AS_SIGNAL_TYPE_DISPLAY_PORT: 858 ss_info->spread_spectrum_percentage = 859 disp_cntl_tbl->dp_ss_percentage; 860 ss_info->spread_spectrum_range = 861 disp_cntl_tbl->dp_ss_rate_10hz * 10; 862 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 863 ss_info->type.CENTER_MODE = true; 864 865 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 866 break; 867 case AS_SIGNAL_TYPE_GPU_PLL: 868 /* atom_firmware: DAL only get data from dce_info table. 869 * if data within smu_info is needed for DAL, VBIOS should 870 * copy it into dce_info 871 */ 872 result = BP_RESULT_UNSUPPORTED; 873 break; 874 case AS_SIGNAL_TYPE_XGMI: 875 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 876 DATA_TABLES(smu_info)); 877 if (!smu_info) 878 return BP_RESULT_BADBIOSTABLE; 879 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 880 ss_info->spread_spectrum_percentage = 881 smu_info->waflclk_ss_percentage; 882 ss_info->spread_spectrum_range = 883 smu_info->gpuclk_ss_rate_10hz * 10; 884 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 885 ss_info->type.CENTER_MODE = true; 886 887 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 888 break; 889 default: 890 result = BP_RESULT_UNSUPPORTED; 891 } 892 893 return result; 894 } 895 896 static enum bp_result get_ss_info_v4_2( 897 struct bios_parser *bp, 898 uint32_t id, 899 uint32_t index, 900 struct spread_spectrum_info *ss_info) 901 { 902 enum bp_result result = BP_RESULT_OK; 903 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 904 struct atom_smu_info_v3_1 *smu_info = NULL; 905 906 if (!ss_info) 907 return BP_RESULT_BADINPUT; 908 909 if (!DATA_TABLES(dce_info)) 910 return BP_RESULT_BADBIOSTABLE; 911 912 if (!DATA_TABLES(smu_info)) 913 return BP_RESULT_BADBIOSTABLE; 914 915 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 916 DATA_TABLES(dce_info)); 917 if (!disp_cntl_tbl) 918 return BP_RESULT_BADBIOSTABLE; 919 920 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 921 if (!smu_info) 922 return BP_RESULT_BADBIOSTABLE; 923 924 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage); 925 ss_info->type.STEP_AND_DELAY_INFO = false; 926 ss_info->spread_percentage_divider = 1000; 927 /* BIOS no longer uses target clock. Always enable for now */ 928 ss_info->target_clock_range = 0xffffffff; 929 930 switch (id) { 931 case AS_SIGNAL_TYPE_DVI: 932 ss_info->spread_spectrum_percentage = 933 disp_cntl_tbl->dvi_ss_percentage; 934 ss_info->spread_spectrum_range = 935 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 936 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 937 ss_info->type.CENTER_MODE = true; 938 939 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 940 break; 941 case AS_SIGNAL_TYPE_HDMI: 942 ss_info->spread_spectrum_percentage = 943 disp_cntl_tbl->hdmi_ss_percentage; 944 ss_info->spread_spectrum_range = 945 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 946 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 947 ss_info->type.CENTER_MODE = true; 948 949 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 950 break; 951 /* TODO LVDS not support anymore? */ 952 case AS_SIGNAL_TYPE_DISPLAY_PORT: 953 ss_info->spread_spectrum_percentage = 954 smu_info->gpuclk_ss_percentage; 955 ss_info->spread_spectrum_range = 956 smu_info->gpuclk_ss_rate_10hz * 10; 957 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 958 ss_info->type.CENTER_MODE = true; 959 960 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 961 break; 962 case AS_SIGNAL_TYPE_GPU_PLL: 963 /* atom_firmware: DAL only get data from dce_info table. 964 * if data within smu_info is needed for DAL, VBIOS should 965 * copy it into dce_info 966 */ 967 result = BP_RESULT_UNSUPPORTED; 968 break; 969 default: 970 result = BP_RESULT_UNSUPPORTED; 971 } 972 973 return result; 974 } 975 976 static enum bp_result get_ss_info_v4_5( 977 struct bios_parser *bp, 978 uint32_t id, 979 uint32_t index, 980 struct spread_spectrum_info *ss_info) 981 { 982 enum bp_result result = BP_RESULT_OK; 983 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 984 985 if (!ss_info) 986 return BP_RESULT_BADINPUT; 987 988 if (!DATA_TABLES(dce_info)) 989 return BP_RESULT_BADBIOSTABLE; 990 991 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 992 DATA_TABLES(dce_info)); 993 if (!disp_cntl_tbl) 994 return BP_RESULT_BADBIOSTABLE; 995 996 ss_info->type.STEP_AND_DELAY_INFO = false; 997 ss_info->spread_percentage_divider = 1000; 998 /* BIOS no longer uses target clock. Always enable for now */ 999 ss_info->target_clock_range = 0xffffffff; 1000 1001 switch (id) { 1002 case AS_SIGNAL_TYPE_DVI: 1003 ss_info->spread_spectrum_percentage = 1004 disp_cntl_tbl->dvi_ss_percentage; 1005 ss_info->spread_spectrum_range = 1006 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 1007 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1008 ss_info->type.CENTER_MODE = true; 1009 1010 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1011 break; 1012 case AS_SIGNAL_TYPE_HDMI: 1013 ss_info->spread_spectrum_percentage = 1014 disp_cntl_tbl->hdmi_ss_percentage; 1015 ss_info->spread_spectrum_range = 1016 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 1017 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1018 ss_info->type.CENTER_MODE = true; 1019 1020 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1021 break; 1022 case AS_SIGNAL_TYPE_DISPLAY_PORT: 1023 ss_info->spread_spectrum_percentage = 1024 disp_cntl_tbl->dp_ss_percentage; 1025 ss_info->spread_spectrum_range = 1026 disp_cntl_tbl->dp_ss_rate_10hz * 10; 1027 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 1028 ss_info->type.CENTER_MODE = true; 1029 1030 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage); 1031 break; 1032 case AS_SIGNAL_TYPE_GPU_PLL: 1033 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore. 1034 * SMU Display PLL supposed to be without spread. 1035 * Better place for it would be in atom_display_controller_info_v4_5 table. 1036 */ 1037 result = BP_RESULT_UNSUPPORTED; 1038 break; 1039 default: 1040 result = BP_RESULT_UNSUPPORTED; 1041 break; 1042 } 1043 1044 return result; 1045 } 1046 1047 /** 1048 * bios_parser_get_spread_spectrum_info 1049 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1050 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1051 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 1052 * ver 3.1, 1053 * there is only one entry for each signal /ss id. However, there is 1054 * no planning of supporting multiple spread Sprectum entry for EverGreen 1055 * @dcb: pointer to the DC BIOS 1056 * @signal: ASSignalType to be converted to info index 1057 * @index: number of entries that match the converted info index 1058 * @ss_info: sprectrum information structure, 1059 * return: Bios parser result code 1060 */ 1061 static enum bp_result bios_parser_get_spread_spectrum_info( 1062 struct dc_bios *dcb, 1063 enum as_signal_type signal, 1064 uint32_t index, 1065 struct spread_spectrum_info *ss_info) 1066 { 1067 struct bios_parser *bp = BP_FROM_DCB(dcb); 1068 enum bp_result result = BP_RESULT_UNSUPPORTED; 1069 struct atom_common_table_header *header; 1070 struct atom_data_revision tbl_revision; 1071 1072 if (!ss_info) /* check for bad input */ 1073 return BP_RESULT_BADINPUT; 1074 1075 if (!DATA_TABLES(dce_info)) 1076 return BP_RESULT_UNSUPPORTED; 1077 1078 header = GET_IMAGE(struct atom_common_table_header, 1079 DATA_TABLES(dce_info)); 1080 get_atom_data_table_revision(header, &tbl_revision); 1081 1082 switch (tbl_revision.major) { 1083 case 4: 1084 switch (tbl_revision.minor) { 1085 case 1: 1086 return get_ss_info_v4_1(bp, signal, index, ss_info); 1087 case 2: 1088 case 3: 1089 case 4: 1090 return get_ss_info_v4_2(bp, signal, index, ss_info); 1091 case 5: 1092 return get_ss_info_v4_5(bp, signal, index, ss_info); 1093 1094 default: 1095 ASSERT(0); 1096 break; 1097 } 1098 break; 1099 default: 1100 break; 1101 } 1102 /* there can not be more then one entry for SS Info table */ 1103 return result; 1104 } 1105 1106 static enum bp_result get_soc_bb_info_v4_4( 1107 struct bios_parser *bp, 1108 struct bp_soc_bb_info *soc_bb_info) 1109 { 1110 enum bp_result result = BP_RESULT_OK; 1111 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1112 1113 if (!soc_bb_info) 1114 return BP_RESULT_BADINPUT; 1115 1116 if (!DATA_TABLES(dce_info)) 1117 return BP_RESULT_BADBIOSTABLE; 1118 1119 if (!DATA_TABLES(smu_info)) 1120 return BP_RESULT_BADBIOSTABLE; 1121 1122 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1123 DATA_TABLES(dce_info)); 1124 if (!disp_cntl_tbl) 1125 return BP_RESULT_BADBIOSTABLE; 1126 1127 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1128 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1129 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1130 1131 return result; 1132 } 1133 1134 static enum bp_result get_soc_bb_info_v4_5( 1135 struct bios_parser *bp, 1136 struct bp_soc_bb_info *soc_bb_info) 1137 { 1138 enum bp_result result = BP_RESULT_OK; 1139 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1140 1141 if (!soc_bb_info) 1142 return BP_RESULT_BADINPUT; 1143 1144 if (!DATA_TABLES(dce_info)) 1145 return BP_RESULT_BADBIOSTABLE; 1146 1147 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1148 DATA_TABLES(dce_info)); 1149 if (!disp_cntl_tbl) 1150 return BP_RESULT_BADBIOSTABLE; 1151 1152 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 1153 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 1154 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 1155 1156 return result; 1157 } 1158 1159 static enum bp_result bios_parser_get_soc_bb_info( 1160 struct dc_bios *dcb, 1161 struct bp_soc_bb_info *soc_bb_info) 1162 { 1163 struct bios_parser *bp = BP_FROM_DCB(dcb); 1164 enum bp_result result = BP_RESULT_UNSUPPORTED; 1165 struct atom_common_table_header *header; 1166 struct atom_data_revision tbl_revision; 1167 1168 if (!soc_bb_info) /* check for bad input */ 1169 return BP_RESULT_BADINPUT; 1170 1171 if (!DATA_TABLES(dce_info)) 1172 return BP_RESULT_UNSUPPORTED; 1173 1174 header = GET_IMAGE(struct atom_common_table_header, 1175 DATA_TABLES(dce_info)); 1176 get_atom_data_table_revision(header, &tbl_revision); 1177 1178 switch (tbl_revision.major) { 1179 case 4: 1180 switch (tbl_revision.minor) { 1181 case 1: 1182 case 2: 1183 case 3: 1184 break; 1185 case 4: 1186 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 1187 break; 1188 case 5: 1189 result = get_soc_bb_info_v4_5(bp, soc_bb_info); 1190 break; 1191 default: 1192 break; 1193 } 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 return result; 1200 } 1201 1202 static enum bp_result get_disp_caps_v4_1( 1203 struct bios_parser *bp, 1204 uint8_t *dce_caps) 1205 { 1206 enum bp_result result = BP_RESULT_OK; 1207 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 1208 1209 if (!dce_caps) 1210 return BP_RESULT_BADINPUT; 1211 1212 if (!DATA_TABLES(dce_info)) 1213 return BP_RESULT_BADBIOSTABLE; 1214 1215 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 1216 DATA_TABLES(dce_info)); 1217 1218 if (!disp_cntl_tbl) 1219 return BP_RESULT_BADBIOSTABLE; 1220 1221 *dce_caps = disp_cntl_tbl->display_caps; 1222 1223 return result; 1224 } 1225 1226 static enum bp_result get_disp_caps_v4_2( 1227 struct bios_parser *bp, 1228 uint8_t *dce_caps) 1229 { 1230 enum bp_result result = BP_RESULT_OK; 1231 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 1232 1233 if (!dce_caps) 1234 return BP_RESULT_BADINPUT; 1235 1236 if (!DATA_TABLES(dce_info)) 1237 return BP_RESULT_BADBIOSTABLE; 1238 1239 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 1240 DATA_TABLES(dce_info)); 1241 1242 if (!disp_cntl_tbl) 1243 return BP_RESULT_BADBIOSTABLE; 1244 1245 *dce_caps = disp_cntl_tbl->display_caps; 1246 1247 return result; 1248 } 1249 1250 static enum bp_result get_disp_caps_v4_3( 1251 struct bios_parser *bp, 1252 uint8_t *dce_caps) 1253 { 1254 enum bp_result result = BP_RESULT_OK; 1255 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL; 1256 1257 if (!dce_caps) 1258 return BP_RESULT_BADINPUT; 1259 1260 if (!DATA_TABLES(dce_info)) 1261 return BP_RESULT_BADBIOSTABLE; 1262 1263 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3, 1264 DATA_TABLES(dce_info)); 1265 1266 if (!disp_cntl_tbl) 1267 return BP_RESULT_BADBIOSTABLE; 1268 1269 *dce_caps = disp_cntl_tbl->display_caps; 1270 1271 return result; 1272 } 1273 1274 static enum bp_result get_disp_caps_v4_4( 1275 struct bios_parser *bp, 1276 uint8_t *dce_caps) 1277 { 1278 enum bp_result result = BP_RESULT_OK; 1279 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 1280 1281 if (!dce_caps) 1282 return BP_RESULT_BADINPUT; 1283 1284 if (!DATA_TABLES(dce_info)) 1285 return BP_RESULT_BADBIOSTABLE; 1286 1287 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 1288 DATA_TABLES(dce_info)); 1289 1290 if (!disp_cntl_tbl) 1291 return BP_RESULT_BADBIOSTABLE; 1292 1293 *dce_caps = disp_cntl_tbl->display_caps; 1294 1295 return result; 1296 } 1297 1298 static enum bp_result get_disp_caps_v4_5( 1299 struct bios_parser *bp, 1300 uint8_t *dce_caps) 1301 { 1302 enum bp_result result = BP_RESULT_OK; 1303 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL; 1304 1305 if (!dce_caps) 1306 return BP_RESULT_BADINPUT; 1307 1308 if (!DATA_TABLES(dce_info)) 1309 return BP_RESULT_BADBIOSTABLE; 1310 1311 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5, 1312 DATA_TABLES(dce_info)); 1313 1314 if (!disp_cntl_tbl) 1315 return BP_RESULT_BADBIOSTABLE; 1316 1317 *dce_caps = disp_cntl_tbl->display_caps; 1318 1319 return result; 1320 } 1321 1322 static enum bp_result bios_parser_get_lttpr_interop( 1323 struct dc_bios *dcb, 1324 uint8_t *dce_caps) 1325 { 1326 struct bios_parser *bp = BP_FROM_DCB(dcb); 1327 enum bp_result result = BP_RESULT_UNSUPPORTED; 1328 struct atom_common_table_header *header; 1329 struct atom_data_revision tbl_revision; 1330 1331 if (!DATA_TABLES(dce_info)) 1332 return BP_RESULT_UNSUPPORTED; 1333 1334 header = GET_IMAGE(struct atom_common_table_header, 1335 DATA_TABLES(dce_info)); 1336 get_atom_data_table_revision(header, &tbl_revision); 1337 switch (tbl_revision.major) { 1338 case 4: 1339 switch (tbl_revision.minor) { 1340 case 1: 1341 result = get_disp_caps_v4_1(bp, dce_caps); 1342 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1343 break; 1344 case 2: 1345 result = get_disp_caps_v4_2(bp, dce_caps); 1346 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1347 break; 1348 case 3: 1349 result = get_disp_caps_v4_3(bp, dce_caps); 1350 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1351 break; 1352 case 4: 1353 result = get_disp_caps_v4_4(bp, dce_caps); 1354 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1355 break; 1356 case 5: 1357 result = get_disp_caps_v4_5(bp, dce_caps); 1358 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE); 1359 break; 1360 1361 default: 1362 break; 1363 } 1364 break; 1365 default: 1366 break; 1367 } 1368 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1369 return result; 1370 } 1371 1372 static enum bp_result bios_parser_get_lttpr_caps( 1373 struct dc_bios *dcb, 1374 uint8_t *dce_caps) 1375 { 1376 struct bios_parser *bp = BP_FROM_DCB(dcb); 1377 enum bp_result result = BP_RESULT_UNSUPPORTED; 1378 struct atom_common_table_header *header; 1379 struct atom_data_revision tbl_revision; 1380 1381 if (!DATA_TABLES(dce_info)) 1382 return BP_RESULT_UNSUPPORTED; 1383 1384 *dce_caps = 0; 1385 header = GET_IMAGE(struct atom_common_table_header, 1386 DATA_TABLES(dce_info)); 1387 get_atom_data_table_revision(header, &tbl_revision); 1388 switch (tbl_revision.major) { 1389 case 4: 1390 switch (tbl_revision.minor) { 1391 case 1: 1392 result = get_disp_caps_v4_1(bp, dce_caps); 1393 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1394 break; 1395 case 2: 1396 result = get_disp_caps_v4_2(bp, dce_caps); 1397 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1398 break; 1399 case 3: 1400 result = get_disp_caps_v4_3(bp, dce_caps); 1401 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1402 break; 1403 case 4: 1404 result = get_disp_caps_v4_4(bp, dce_caps); 1405 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1406 break; 1407 case 5: 1408 result = get_disp_caps_v4_5(bp, dce_caps); 1409 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE); 1410 break; 1411 default: 1412 break; 1413 } 1414 break; 1415 default: 1416 break; 1417 } 1418 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor); 1419 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) { 1420 *dce_caps = 1; 1421 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled"); 1422 } 1423 return result; 1424 } 1425 1426 static enum bp_result get_embedded_panel_info_v2_1( 1427 struct bios_parser *bp, 1428 struct embedded_panel_info *info) 1429 { 1430 struct lcd_info_v2_1 *lvds; 1431 1432 if (!info) 1433 return BP_RESULT_BADINPUT; 1434 1435 if (!DATA_TABLES(lcd_info)) 1436 return BP_RESULT_UNSUPPORTED; 1437 1438 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 1439 1440 if (!lvds) 1441 return BP_RESULT_BADBIOSTABLE; 1442 1443 /* TODO: previous vv1_3, should v2_1 */ 1444 if (!((lvds->table_header.format_revision == 2) 1445 && (lvds->table_header.content_revision >= 1))) 1446 return BP_RESULT_UNSUPPORTED; 1447 1448 memset(info, 0, sizeof(struct embedded_panel_info)); 1449 1450 /* We need to convert from 10KHz units into KHz units */ 1451 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 1452 /* usHActive does not include borders, according to VBIOS team */ 1453 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 1454 /* usHBlanking_Time includes borders, so we should really be 1455 * subtractingborders duing this translation, but LVDS generally 1456 * doesn't have borders, so we should be okay leaving this as is for 1457 * now. May need to revisit if we ever have LVDS with borders 1458 */ 1459 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 1460 /* usVActive does not include borders, according to VBIOS team*/ 1461 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 1462 /* usVBlanking_Time includes borders, so we should really be 1463 * subtracting borders duing this translation, but LVDS generally 1464 * doesn't have borders, so we should be okay leaving this as is for 1465 * now. May need to revisit if we ever have LVDS with borders 1466 */ 1467 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 1468 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 1469 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 1470 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 1471 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 1472 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 1473 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 1474 1475 /* not provided by VBIOS */ 1476 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 1477 1478 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1479 & ATOM_HSYNC_POLARITY); 1480 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 1481 & ATOM_VSYNC_POLARITY); 1482 1483 /* not provided by VBIOS */ 1484 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 1485 1486 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1487 & ATOM_H_REPLICATIONBY2); 1488 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 1489 & ATOM_V_REPLICATIONBY2); 1490 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 1491 & ATOM_COMPOSITESYNC); 1492 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 1493 1494 /* not provided by VBIOS*/ 1495 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 1496 /* not provided by VBIOS*/ 1497 info->ss_id = 0; 1498 1499 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 1500 1501 return BP_RESULT_OK; 1502 } 1503 1504 static enum bp_result bios_parser_get_embedded_panel_info( 1505 struct dc_bios *dcb, 1506 struct embedded_panel_info *info) 1507 { 1508 struct bios_parser 1509 *bp = BP_FROM_DCB(dcb); 1510 struct atom_common_table_header *header; 1511 struct atom_data_revision tbl_revision; 1512 1513 if (!DATA_TABLES(lcd_info)) 1514 return BP_RESULT_FAILURE; 1515 1516 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1517 1518 if (!header) 1519 return BP_RESULT_BADBIOSTABLE; 1520 1521 get_atom_data_table_revision(header, &tbl_revision); 1522 1523 switch (tbl_revision.major) { 1524 case 2: 1525 switch (tbl_revision.minor) { 1526 case 1: 1527 return get_embedded_panel_info_v2_1(bp, info); 1528 default: 1529 break; 1530 } 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 return BP_RESULT_FAILURE; 1537 } 1538 1539 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1540 { 1541 enum dal_device_type device_type = device_id.device_type; 1542 uint32_t enum_id = device_id.enum_id; 1543 1544 switch (device_type) { 1545 case DEVICE_TYPE_LCD: 1546 switch (enum_id) { 1547 case 1: 1548 return ATOM_DISPLAY_LCD1_SUPPORT; 1549 default: 1550 break; 1551 } 1552 break; 1553 case DEVICE_TYPE_DFP: 1554 switch (enum_id) { 1555 case 1: 1556 return ATOM_DISPLAY_DFP1_SUPPORT; 1557 case 2: 1558 return ATOM_DISPLAY_DFP2_SUPPORT; 1559 case 3: 1560 return ATOM_DISPLAY_DFP3_SUPPORT; 1561 case 4: 1562 return ATOM_DISPLAY_DFP4_SUPPORT; 1563 case 5: 1564 return ATOM_DISPLAY_DFP5_SUPPORT; 1565 case 6: 1566 return ATOM_DISPLAY_DFP6_SUPPORT; 1567 default: 1568 break; 1569 } 1570 break; 1571 default: 1572 break; 1573 } 1574 1575 /* Unidentified device ID, return empty support mask. */ 1576 return 0; 1577 } 1578 1579 static bool bios_parser_is_device_id_supported( 1580 struct dc_bios *dcb, 1581 struct device_id id) 1582 { 1583 struct bios_parser *bp = BP_FROM_DCB(dcb); 1584 1585 uint32_t mask = get_support_mask_for_device_id(id); 1586 1587 switch (bp->object_info_tbl.revision.minor) { 1588 case 4: 1589 default: 1590 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0; 1591 break; 1592 case 5: 1593 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0; 1594 break; 1595 } 1596 1597 return false; 1598 } 1599 1600 static uint32_t bios_parser_get_ss_entry_number( 1601 struct dc_bios *dcb, 1602 enum as_signal_type signal) 1603 { 1604 /* TODO: DAL2 atomfirmware implementation does not need this. 1605 * why DAL3 need this? 1606 */ 1607 return 1; 1608 } 1609 1610 static enum bp_result bios_parser_transmitter_control( 1611 struct dc_bios *dcb, 1612 struct bp_transmitter_control *cntl) 1613 { 1614 struct bios_parser *bp = BP_FROM_DCB(dcb); 1615 1616 if (!bp->cmd_tbl.transmitter_control) 1617 return BP_RESULT_FAILURE; 1618 1619 return bp->cmd_tbl.transmitter_control(bp, cntl); 1620 } 1621 1622 static enum bp_result bios_parser_encoder_control( 1623 struct dc_bios *dcb, 1624 struct bp_encoder_control *cntl) 1625 { 1626 struct bios_parser *bp = BP_FROM_DCB(dcb); 1627 1628 if (!bp->cmd_tbl.dig_encoder_control) 1629 return BP_RESULT_FAILURE; 1630 1631 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1632 } 1633 1634 static enum bp_result bios_parser_set_pixel_clock( 1635 struct dc_bios *dcb, 1636 struct bp_pixel_clock_parameters *bp_params) 1637 { 1638 struct bios_parser *bp = BP_FROM_DCB(dcb); 1639 1640 if (!bp->cmd_tbl.set_pixel_clock) 1641 return BP_RESULT_FAILURE; 1642 1643 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1644 } 1645 1646 static enum bp_result bios_parser_set_dce_clock( 1647 struct dc_bios *dcb, 1648 struct bp_set_dce_clock_parameters *bp_params) 1649 { 1650 struct bios_parser *bp = BP_FROM_DCB(dcb); 1651 1652 if (!bp->cmd_tbl.set_dce_clock) 1653 return BP_RESULT_FAILURE; 1654 1655 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1656 } 1657 1658 static enum bp_result bios_parser_program_crtc_timing( 1659 struct dc_bios *dcb, 1660 struct bp_hw_crtc_timing_parameters *bp_params) 1661 { 1662 struct bios_parser *bp = BP_FROM_DCB(dcb); 1663 1664 if (!bp->cmd_tbl.set_crtc_timing) 1665 return BP_RESULT_FAILURE; 1666 1667 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1668 } 1669 1670 static enum bp_result bios_parser_enable_crtc( 1671 struct dc_bios *dcb, 1672 enum controller_id id, 1673 bool enable) 1674 { 1675 struct bios_parser *bp = BP_FROM_DCB(dcb); 1676 1677 if (!bp->cmd_tbl.enable_crtc) 1678 return BP_RESULT_FAILURE; 1679 1680 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1681 } 1682 1683 static enum bp_result bios_parser_enable_disp_power_gating( 1684 struct dc_bios *dcb, 1685 enum controller_id controller_id, 1686 enum bp_pipe_control_action action) 1687 { 1688 struct bios_parser *bp = BP_FROM_DCB(dcb); 1689 1690 if (!bp->cmd_tbl.enable_disp_power_gating) 1691 return BP_RESULT_FAILURE; 1692 1693 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1694 action); 1695 } 1696 1697 static enum bp_result bios_parser_enable_lvtma_control( 1698 struct dc_bios *dcb, 1699 uint8_t uc_pwr_on, 1700 uint8_t panel_instance, 1701 uint8_t bypass_panel_control_wait) 1702 { 1703 struct bios_parser *bp = BP_FROM_DCB(dcb); 1704 1705 if (!bp->cmd_tbl.enable_lvtma_control) 1706 return BP_RESULT_FAILURE; 1707 1708 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, panel_instance, bypass_panel_control_wait); 1709 } 1710 1711 static bool bios_parser_is_accelerated_mode( 1712 struct dc_bios *dcb) 1713 { 1714 return bios_is_accelerated_mode(dcb); 1715 } 1716 1717 /** 1718 * bios_parser_set_scratch_critical_state - update critical state bit 1719 * in VBIOS scratch register 1720 * 1721 * @dcb: pointer to the DC BIO 1722 * @state: set or reset state 1723 */ 1724 static void bios_parser_set_scratch_critical_state( 1725 struct dc_bios *dcb, 1726 bool state) 1727 { 1728 bios_set_scratch_critical_state(dcb, state); 1729 } 1730 1731 struct atom_dig_transmitter_info_header_v5_3 { 1732 struct atom_common_table_header table_header; 1733 uint16_t dpphy_hdmi_settings_offset; 1734 uint16_t dpphy_dvi_settings_offset; 1735 uint16_t dpphy_dp_setting_table_offset; 1736 uint16_t uniphy_xbar_settings_v2_table_offset; 1737 uint16_t dpphy_internal_reg_overide_offset; 1738 }; 1739 1740 static enum bp_result bios_parser_get_firmware_info( 1741 struct dc_bios *dcb, 1742 struct dc_firmware_info *info) 1743 { 1744 struct bios_parser *bp = BP_FROM_DCB(dcb); 1745 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 1746 struct atom_common_table_header *header; 1747 1748 struct atom_data_revision revision; 1749 1750 if (info && DATA_TABLES(firmwareinfo)) { 1751 header = GET_IMAGE(struct atom_common_table_header, 1752 DATA_TABLES(firmwareinfo)); 1753 get_atom_data_table_revision(header, &revision); 1754 switch (revision.major) { 1755 case 3: 1756 switch (revision.minor) { 1757 case 1: 1758 result = get_firmware_info_v3_1(bp, info); 1759 break; 1760 case 2: 1761 case 3: 1762 result = get_firmware_info_v3_2(bp, info); 1763 break; 1764 case 4: 1765 result = get_firmware_info_v3_4(bp, info); 1766 break; 1767 default: 1768 break; 1769 } 1770 break; 1771 default: 1772 break; 1773 } 1774 } 1775 1776 return result; 1777 } 1778 1779 static enum bp_result get_firmware_info_v3_1( 1780 struct bios_parser *bp, 1781 struct dc_firmware_info *info) 1782 { 1783 struct atom_firmware_info_v3_1 *firmware_info; 1784 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1785 1786 if (!info) 1787 return BP_RESULT_BADINPUT; 1788 1789 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1790 DATA_TABLES(firmwareinfo)); 1791 1792 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1793 DATA_TABLES(dce_info)); 1794 1795 if (!firmware_info || !dce_info) 1796 return BP_RESULT_BADBIOSTABLE; 1797 1798 memset(info, 0, sizeof(*info)); 1799 1800 /* Pixel clock pll information. */ 1801 /* We need to convert from 10KHz units into KHz units */ 1802 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1803 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1804 1805 /* 27MHz for Vega10: */ 1806 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1807 1808 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1809 if (info->pll_info.crystal_frequency == 0) 1810 info->pll_info.crystal_frequency = 27000; 1811 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1812 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1813 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1814 1815 /* Get GPU PLL VCO Clock */ 1816 1817 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1818 /* VBIOS gives in 10KHz */ 1819 info->smu_gpu_pll_output_freq = 1820 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1821 } 1822 1823 info->oem_i2c_present = false; 1824 1825 return BP_RESULT_OK; 1826 } 1827 1828 static enum bp_result get_firmware_info_v3_2( 1829 struct bios_parser *bp, 1830 struct dc_firmware_info *info) 1831 { 1832 struct atom_firmware_info_v3_2 *firmware_info; 1833 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1834 struct atom_common_table_header *header; 1835 struct atom_data_revision revision; 1836 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1837 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1838 1839 if (!info) 1840 return BP_RESULT_BADINPUT; 1841 1842 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1843 DATA_TABLES(firmwareinfo)); 1844 1845 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1846 DATA_TABLES(dce_info)); 1847 1848 if (!firmware_info || !dce_info) 1849 return BP_RESULT_BADBIOSTABLE; 1850 1851 memset(info, 0, sizeof(*info)); 1852 1853 header = GET_IMAGE(struct atom_common_table_header, 1854 DATA_TABLES(smu_info)); 1855 get_atom_data_table_revision(header, &revision); 1856 1857 if (revision.minor == 2) { 1858 /* Vega12 */ 1859 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1860 DATA_TABLES(smu_info)); 1861 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage); 1862 if (!smu_info_v3_2) 1863 return BP_RESULT_BADBIOSTABLE; 1864 1865 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1866 } else if (revision.minor == 3) { 1867 /* Vega20 */ 1868 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1869 DATA_TABLES(smu_info)); 1870 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage); 1871 if (!smu_info_v3_3) 1872 return BP_RESULT_BADBIOSTABLE; 1873 1874 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1875 } 1876 1877 // We need to convert from 10KHz units into KHz units. 1878 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1879 1880 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1881 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1882 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1883 if (info->pll_info.crystal_frequency == 0) { 1884 if (revision.minor == 2) 1885 info->pll_info.crystal_frequency = 27000; 1886 else if (revision.minor == 3) 1887 info->pll_info.crystal_frequency = 100000; 1888 } 1889 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1890 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1891 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1892 1893 /* Get GPU PLL VCO Clock */ 1894 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1895 if (revision.minor == 2) 1896 info->smu_gpu_pll_output_freq = 1897 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1898 else if (revision.minor == 3) 1899 info->smu_gpu_pll_output_freq = 1900 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1901 } 1902 1903 if (firmware_info->board_i2c_feature_id == 0x2) { 1904 info->oem_i2c_present = true; 1905 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1906 } else { 1907 info->oem_i2c_present = false; 1908 } 1909 1910 return BP_RESULT_OK; 1911 } 1912 1913 static enum bp_result get_firmware_info_v3_4( 1914 struct bios_parser *bp, 1915 struct dc_firmware_info *info) 1916 { 1917 struct atom_firmware_info_v3_4 *firmware_info; 1918 struct atom_common_table_header *header; 1919 struct atom_data_revision revision; 1920 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL; 1921 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL; 1922 1923 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL; 1924 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL; 1925 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL; 1926 1927 if (!info) 1928 return BP_RESULT_BADINPUT; 1929 1930 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4, 1931 DATA_TABLES(firmwareinfo)); 1932 1933 if (!firmware_info) 1934 return BP_RESULT_BADBIOSTABLE; 1935 1936 memset(info, 0, sizeof(*info)); 1937 1938 header = GET_IMAGE(struct atom_common_table_header, 1939 DATA_TABLES(dce_info)); 1940 1941 get_atom_data_table_revision(header, &revision); 1942 1943 switch (revision.major) { 1944 case 4: 1945 switch (revision.minor) { 1946 case 5: 1947 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5, 1948 DATA_TABLES(dce_info)); 1949 1950 if (!dce_info_v4_5) 1951 return BP_RESULT_BADBIOSTABLE; 1952 1953 /* 100MHz expected */ 1954 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10; 1955 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10; 1956 /* 50MHz expected */ 1957 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10; 1958 1959 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */ 1960 break; 1961 1962 case 4: 1963 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 1964 DATA_TABLES(dce_info)); 1965 1966 if (!dce_info_v4_4) 1967 return BP_RESULT_BADBIOSTABLE; 1968 1969 /* 100MHz expected */ 1970 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10; 1971 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10; 1972 /* 50MHz expected */ 1973 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10; 1974 1975 /* Get SMU Display PLL VCO Frequency in KHz*/ 1976 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10; 1977 break; 1978 1979 default: 1980 /* should not come here, keep as backup, as was before */ 1981 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1, 1982 DATA_TABLES(dce_info)); 1983 1984 if (!dce_info_v4_1) 1985 return BP_RESULT_BADBIOSTABLE; 1986 1987 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10; 1988 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10; 1989 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10; 1990 break; 1991 } 1992 break; 1993 1994 default: 1995 ASSERT(0); 1996 break; 1997 } 1998 1999 header = GET_IMAGE(struct atom_common_table_header, 2000 DATA_TABLES(smu_info)); 2001 get_atom_data_table_revision(header, &revision); 2002 2003 switch (revision.major) { 2004 case 3: 2005 switch (revision.minor) { 2006 case 5: 2007 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5, 2008 DATA_TABLES(smu_info)); 2009 2010 if (!smu_info_v3_5) 2011 return BP_RESULT_BADBIOSTABLE; 2012 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage); 2013 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10; 2014 break; 2015 2016 default: 2017 break; 2018 } 2019 break; 2020 2021 case 4: 2022 switch (revision.minor) { 2023 case 0: 2024 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0, 2025 DATA_TABLES(smu_info)); 2026 2027 if (!smu_info_v4_0) 2028 return BP_RESULT_BADBIOSTABLE; 2029 2030 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */ 2031 break; 2032 2033 default: 2034 break; 2035 } 2036 break; 2037 2038 default: 2039 break; 2040 } 2041 2042 // We need to convert from 10KHz units into KHz units. 2043 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 2044 2045 if (firmware_info->board_i2c_feature_id == 0x2) { 2046 info->oem_i2c_present = true; 2047 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 2048 } else { 2049 info->oem_i2c_present = false; 2050 } 2051 2052 return BP_RESULT_OK; 2053 } 2054 2055 static enum bp_result bios_parser_get_encoder_cap_info( 2056 struct dc_bios *dcb, 2057 struct graphics_object_id object_id, 2058 struct bp_encoder_cap_info *info) 2059 { 2060 struct bios_parser *bp = BP_FROM_DCB(dcb); 2061 struct atom_display_object_path_v2 *object; 2062 struct atom_encoder_caps_record *record = NULL; 2063 2064 if (!info) 2065 return BP_RESULT_BADINPUT; 2066 2067 #if defined(CONFIG_DRM_AMD_DC_DCN) 2068 /* encoder cap record not available in v1_5 */ 2069 if (bp->object_info_tbl.revision.minor == 5) 2070 return BP_RESULT_NORECORD; 2071 #endif 2072 2073 object = get_bios_object(bp, object_id); 2074 2075 if (!object) 2076 return BP_RESULT_BADINPUT; 2077 2078 record = get_encoder_cap_record(bp, object); 2079 if (!record) 2080 return BP_RESULT_NORECORD; 2081 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id); 2082 2083 info->DP_HBR2_CAP = (record->encodercaps & 2084 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 2085 info->DP_HBR2_EN = (record->encodercaps & 2086 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 2087 info->DP_HBR3_EN = (record->encodercaps & 2088 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 2089 info->HDMI_6GB_EN = (record->encodercaps & 2090 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 2091 info->IS_DP2_CAPABLE = (record->encodercaps & 2092 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0; 2093 info->DP_UHBR10_EN = (record->encodercaps & 2094 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0; 2095 info->DP_UHBR13_5_EN = (record->encodercaps & 2096 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0; 2097 info->DP_UHBR20_EN = (record->encodercaps & 2098 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0; 2099 info->DP_IS_USB_C = (record->encodercaps & 2100 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 2101 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C); 2102 2103 return BP_RESULT_OK; 2104 } 2105 2106 2107 static struct atom_encoder_caps_record *get_encoder_cap_record( 2108 struct bios_parser *bp, 2109 struct atom_display_object_path_v2 *object) 2110 { 2111 struct atom_common_record_header *header; 2112 uint32_t offset; 2113 2114 if (!object) { 2115 BREAK_TO_DEBUGGER(); /* Invalid object */ 2116 return NULL; 2117 } 2118 2119 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 2120 2121 for (;;) { 2122 header = GET_IMAGE(struct atom_common_record_header, offset); 2123 2124 if (!header) 2125 return NULL; 2126 2127 offset += header->record_size; 2128 2129 if (header->record_type == LAST_RECORD_TYPE || 2130 !header->record_size) 2131 break; 2132 2133 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 2134 continue; 2135 2136 if (sizeof(struct atom_encoder_caps_record) <= 2137 header->record_size) 2138 return (struct atom_encoder_caps_record *)header; 2139 } 2140 2141 return NULL; 2142 } 2143 2144 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 2145 struct bios_parser *bp, 2146 struct atom_display_object_path_v2 *object) 2147 { 2148 struct atom_common_record_header *header; 2149 uint32_t offset; 2150 2151 if (!object) { 2152 BREAK_TO_DEBUGGER(); /* Invalid object */ 2153 return NULL; 2154 } 2155 2156 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2157 2158 for (;;) { 2159 header = GET_IMAGE(struct atom_common_record_header, offset); 2160 2161 if (!header) 2162 return NULL; 2163 2164 offset += header->record_size; 2165 2166 if (header->record_type == LAST_RECORD_TYPE || 2167 !header->record_size) 2168 break; 2169 2170 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 2171 continue; 2172 2173 if (sizeof(struct atom_disp_connector_caps_record) <= 2174 header->record_size) 2175 return (struct atom_disp_connector_caps_record *)header; 2176 } 2177 2178 return NULL; 2179 } 2180 2181 static struct atom_connector_caps_record *get_connector_caps_record( 2182 struct bios_parser *bp, 2183 struct atom_display_object_path_v3 *object) 2184 { 2185 struct atom_common_record_header *header; 2186 uint32_t offset; 2187 2188 if (!object) { 2189 BREAK_TO_DEBUGGER(); /* Invalid object */ 2190 return NULL; 2191 } 2192 2193 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2194 2195 for (;;) { 2196 header = GET_IMAGE(struct atom_common_record_header, offset); 2197 2198 if (!header) 2199 return NULL; 2200 2201 offset += header->record_size; 2202 2203 if (header->record_type == ATOM_RECORD_END_TYPE || 2204 !header->record_size) 2205 break; 2206 2207 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE) 2208 continue; 2209 2210 if (sizeof(struct atom_connector_caps_record) <= header->record_size) 2211 return (struct atom_connector_caps_record *)header; 2212 } 2213 2214 return NULL; 2215 } 2216 2217 static enum bp_result bios_parser_get_disp_connector_caps_info( 2218 struct dc_bios *dcb, 2219 struct graphics_object_id object_id, 2220 struct bp_disp_connector_caps_info *info) 2221 { 2222 struct bios_parser *bp = BP_FROM_DCB(dcb); 2223 struct atom_display_object_path_v2 *object; 2224 2225 struct atom_display_object_path_v3 *object_path_v3; 2226 struct atom_connector_caps_record *record_path_v3; 2227 2228 struct atom_disp_connector_caps_record *record = NULL; 2229 2230 if (!info) 2231 return BP_RESULT_BADINPUT; 2232 2233 switch (bp->object_info_tbl.revision.minor) { 2234 case 4: 2235 default: 2236 object = get_bios_object(bp, object_id); 2237 2238 if (!object) 2239 return BP_RESULT_BADINPUT; 2240 2241 record = get_disp_connector_caps_record(bp, object); 2242 if (!record) 2243 return BP_RESULT_NORECORD; 2244 2245 info->INTERNAL_DISPLAY = 2246 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0; 2247 info->INTERNAL_DISPLAY_BL = 2248 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0; 2249 break; 2250 case 5: 2251 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2252 2253 if (!object_path_v3) 2254 return BP_RESULT_BADINPUT; 2255 2256 record_path_v3 = get_connector_caps_record(bp, object_path_v3); 2257 if (!record_path_v3) 2258 return BP_RESULT_NORECORD; 2259 2260 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 2261 ? 1 : 0; 2262 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 2263 ? 1 : 0; 2264 break; 2265 } 2266 2267 return BP_RESULT_OK; 2268 } 2269 2270 static struct atom_connector_speed_record *get_connector_speed_cap_record( 2271 struct bios_parser *bp, 2272 struct atom_display_object_path_v3 *object) 2273 { 2274 struct atom_common_record_header *header; 2275 uint32_t offset; 2276 2277 if (!object) { 2278 BREAK_TO_DEBUGGER(); /* Invalid object */ 2279 return NULL; 2280 } 2281 2282 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 2283 2284 for (;;) { 2285 header = GET_IMAGE(struct atom_common_record_header, offset); 2286 2287 if (!header) 2288 return NULL; 2289 2290 offset += header->record_size; 2291 2292 if (header->record_type == ATOM_RECORD_END_TYPE || 2293 !header->record_size) 2294 break; 2295 2296 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO) 2297 continue; 2298 2299 if (sizeof(struct atom_connector_speed_record) <= header->record_size) 2300 return (struct atom_connector_speed_record *)header; 2301 } 2302 2303 return NULL; 2304 } 2305 2306 static enum bp_result bios_parser_get_connector_speed_cap_info( 2307 struct dc_bios *dcb, 2308 struct graphics_object_id object_id, 2309 struct bp_connector_speed_cap_info *info) 2310 { 2311 struct bios_parser *bp = BP_FROM_DCB(dcb); 2312 struct atom_display_object_path_v3 *object_path_v3; 2313 //struct atom_connector_speed_record *record = NULL; 2314 struct atom_connector_speed_record *record; 2315 2316 if (!info) 2317 return BP_RESULT_BADINPUT; 2318 2319 object_path_v3 = get_bios_object_from_path_v3(bp, object_id); 2320 2321 if (!object_path_v3) 2322 return BP_RESULT_BADINPUT; 2323 2324 record = get_connector_speed_cap_record(bp, object_path_v3); 2325 if (!record) 2326 return BP_RESULT_NORECORD; 2327 2328 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0; 2329 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0; 2330 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0; 2331 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0; 2332 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0; 2333 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0; 2334 return BP_RESULT_OK; 2335 } 2336 2337 static enum bp_result get_vram_info_v23( 2338 struct bios_parser *bp, 2339 struct dc_vram_info *info) 2340 { 2341 struct atom_vram_info_header_v2_3 *info_v23; 2342 static enum bp_result result = BP_RESULT_OK; 2343 2344 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 2345 DATA_TABLES(vram_info)); 2346 2347 if (info_v23 == NULL) 2348 return BP_RESULT_BADBIOSTABLE; 2349 2350 info->num_chans = info_v23->vram_module[0].channel_num; 2351 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 2352 2353 return result; 2354 } 2355 2356 static enum bp_result get_vram_info_v24( 2357 struct bios_parser *bp, 2358 struct dc_vram_info *info) 2359 { 2360 struct atom_vram_info_header_v2_4 *info_v24; 2361 static enum bp_result result = BP_RESULT_OK; 2362 2363 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 2364 DATA_TABLES(vram_info)); 2365 2366 if (info_v24 == NULL) 2367 return BP_RESULT_BADBIOSTABLE; 2368 2369 info->num_chans = info_v24->vram_module[0].channel_num; 2370 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 2371 2372 return result; 2373 } 2374 2375 static enum bp_result get_vram_info_v25( 2376 struct bios_parser *bp, 2377 struct dc_vram_info *info) 2378 { 2379 struct atom_vram_info_header_v2_5 *info_v25; 2380 static enum bp_result result = BP_RESULT_OK; 2381 2382 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 2383 DATA_TABLES(vram_info)); 2384 2385 if (info_v25 == NULL) 2386 return BP_RESULT_BADBIOSTABLE; 2387 2388 info->num_chans = info_v25->vram_module[0].channel_num; 2389 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 2390 2391 return result; 2392 } 2393 2394 static enum bp_result get_vram_info_v30( 2395 struct bios_parser *bp, 2396 struct dc_vram_info *info) 2397 { 2398 struct atom_vram_info_header_v3_0 *info_v30; 2399 enum bp_result result = BP_RESULT_OK; 2400 2401 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0, 2402 DATA_TABLES(vram_info)); 2403 2404 if (info_v30 == NULL) 2405 return BP_RESULT_BADBIOSTABLE; 2406 2407 info->num_chans = info_v30->channel_num; 2408 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; 2409 2410 return result; 2411 } 2412 2413 2414 /* 2415 * get_integrated_info_v11 2416 * 2417 * @brief 2418 * Get V8 integrated BIOS information 2419 * 2420 * @param 2421 * bios_parser *bp - [in]BIOS parser handler to get master data table 2422 * integrated_info *info - [out] store and output integrated info 2423 * 2424 * @return 2425 * static enum bp_result - BP_RESULT_OK if information is available, 2426 * BP_RESULT_BADBIOSTABLE otherwise. 2427 */ 2428 static enum bp_result get_integrated_info_v11( 2429 struct bios_parser *bp, 2430 struct integrated_info *info) 2431 { 2432 struct atom_integrated_system_info_v1_11 *info_v11; 2433 uint32_t i; 2434 2435 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 2436 DATA_TABLES(integratedsysteminfo)); 2437 2438 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage); 2439 if (info_v11 == NULL) 2440 return BP_RESULT_BADBIOSTABLE; 2441 2442 info->gpu_cap_info = 2443 le32_to_cpu(info_v11->gpucapinfo); 2444 /* 2445 * system_config: Bit[0] = 0 : PCIE power gating disabled 2446 * = 1 : PCIE power gating enabled 2447 * Bit[1] = 0 : DDR-PLL shut down disabled 2448 * = 1 : DDR-PLL shut down enabled 2449 * Bit[2] = 0 : DDR-PLL power down disabled 2450 * = 1 : DDR-PLL power down enabled 2451 */ 2452 info->system_config = le32_to_cpu(info_v11->system_config); 2453 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 2454 info->memory_type = info_v11->memorytype; 2455 info->ma_channel_number = info_v11->umachannelnumber; 2456 info->lvds_ss_percentage = 2457 le16_to_cpu(info_v11->lvds_ss_percentage); 2458 info->dp_ss_control = 2459 le16_to_cpu(info_v11->reserved1); 2460 info->lvds_sspread_rate_in_10hz = 2461 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 2462 info->hdmi_ss_percentage = 2463 le16_to_cpu(info_v11->hdmi_ss_percentage); 2464 info->hdmi_sspread_rate_in_10hz = 2465 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 2466 info->dvi_ss_percentage = 2467 le16_to_cpu(info_v11->dvi_ss_percentage); 2468 info->dvi_sspread_rate_in_10_hz = 2469 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 2470 info->lvds_misc = info_v11->lvds_misc; 2471 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2472 info->ext_disp_conn_info.gu_id[i] = 2473 info_v11->extdispconninfo.guid[i]; 2474 } 2475 2476 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2477 info->ext_disp_conn_info.path[i].device_connector_id = 2478 object_id_from_bios_object_id( 2479 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 2480 2481 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2482 object_id_from_bios_object_id( 2483 le16_to_cpu( 2484 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 2485 2486 info->ext_disp_conn_info.path[i].device_tag = 2487 le16_to_cpu( 2488 info_v11->extdispconninfo.path[i].device_tag); 2489 info->ext_disp_conn_info.path[i].device_acpi_enum = 2490 le16_to_cpu( 2491 info_v11->extdispconninfo.path[i].device_acpi_enum); 2492 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2493 info_v11->extdispconninfo.path[i].auxddclut_index; 2494 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2495 info_v11->extdispconninfo.path[i].hpdlut_index; 2496 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2497 info_v11->extdispconninfo.path[i].channelmapping; 2498 info->ext_disp_conn_info.path[i].caps = 2499 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 2500 } 2501 info->ext_disp_conn_info.checksum = 2502 info_v11->extdispconninfo.checksum; 2503 2504 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 2505 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 2506 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2507 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2508 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2509 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2510 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2511 } 2512 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 2513 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2514 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2515 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2516 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2517 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2518 } 2519 2520 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 2521 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 2522 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2523 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2524 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2525 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2526 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2527 } 2528 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 2529 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2530 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2531 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2532 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2533 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2534 } 2535 2536 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 2537 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 2538 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2539 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2540 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2541 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2542 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2543 } 2544 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 2545 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2546 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2547 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2548 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2549 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2550 } 2551 2552 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 2553 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 2554 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2555 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2556 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2557 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2558 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2559 } 2560 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 2561 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2562 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2563 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2564 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2565 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2566 } 2567 2568 2569 /** TODO - review **/ 2570 #if 0 2571 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 2572 * 10; 2573 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 2574 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2575 2576 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2577 /* Convert [10KHz] into [KHz] */ 2578 info->disp_clk_voltage[i].max_supported_clk = 2579 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 2580 ulMaximumSupportedCLK) * 10; 2581 info->disp_clk_voltage[i].voltage_index = 2582 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 2583 } 2584 2585 info->boot_up_req_display_vector = 2586 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 2587 info->boot_up_nb_voltage = 2588 le16_to_cpu(info_v11->usBootUpNBVoltage); 2589 info->ext_disp_conn_info_offset = 2590 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 2591 info->gmc_restore_reset_time = 2592 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 2593 info->minimum_n_clk = 2594 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 2595 for (i = 1; i < 4; ++i) 2596 info->minimum_n_clk = 2597 info->minimum_n_clk < 2598 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 2599 info->minimum_n_clk : le32_to_cpu( 2600 info_v11->ulNbpStateNClkFreq[i]); 2601 2602 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 2603 info->ddr_dll_power_up_time = 2604 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 2605 info->ddr_pll_power_up_time = 2606 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 2607 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 2608 info->max_lvds_pclk_freq_in_single_link = 2609 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2610 info->max_lvds_pclk_freq_in_single_link = 2611 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 2612 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2613 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2614 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2615 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2616 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2617 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2618 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2619 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2620 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2621 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2622 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2623 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2624 info->lvds_off_to_on_delay_in_4ms = 2625 info_v11->ucLVDSOffToOnDelay_in4Ms; 2626 info->lvds_bit_depth_control_val = 2627 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 2628 2629 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2630 /* Convert [10KHz] into [KHz] */ 2631 info->avail_s_clk[i].supported_s_clk = 2632 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 2633 * 10; 2634 info->avail_s_clk[i].voltage_index = 2635 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 2636 info->avail_s_clk[i].voltage_id = 2637 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 2638 } 2639 #endif /* TODO*/ 2640 2641 return BP_RESULT_OK; 2642 } 2643 2644 static enum bp_result get_integrated_info_v2_1( 2645 struct bios_parser *bp, 2646 struct integrated_info *info) 2647 { 2648 struct atom_integrated_system_info_v2_1 *info_v2_1; 2649 uint32_t i; 2650 2651 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 2652 DATA_TABLES(integratedsysteminfo)); 2653 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage); 2654 2655 if (info_v2_1 == NULL) 2656 return BP_RESULT_BADBIOSTABLE; 2657 2658 info->gpu_cap_info = 2659 le32_to_cpu(info_v2_1->gpucapinfo); 2660 /* 2661 * system_config: Bit[0] = 0 : PCIE power gating disabled 2662 * = 1 : PCIE power gating enabled 2663 * Bit[1] = 0 : DDR-PLL shut down disabled 2664 * = 1 : DDR-PLL shut down enabled 2665 * Bit[2] = 0 : DDR-PLL power down disabled 2666 * = 1 : DDR-PLL power down enabled 2667 */ 2668 info->system_config = le32_to_cpu(info_v2_1->system_config); 2669 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 2670 info->memory_type = info_v2_1->memorytype; 2671 info->ma_channel_number = info_v2_1->umachannelnumber; 2672 info->dp_ss_control = 2673 le16_to_cpu(info_v2_1->reserved1); 2674 2675 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2676 info->ext_disp_conn_info.gu_id[i] = 2677 info_v2_1->extdispconninfo.guid[i]; 2678 } 2679 2680 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2681 info->ext_disp_conn_info.path[i].device_connector_id = 2682 object_id_from_bios_object_id( 2683 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 2684 2685 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2686 object_id_from_bios_object_id( 2687 le16_to_cpu( 2688 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 2689 2690 info->ext_disp_conn_info.path[i].device_tag = 2691 le16_to_cpu( 2692 info_v2_1->extdispconninfo.path[i].device_tag); 2693 info->ext_disp_conn_info.path[i].device_acpi_enum = 2694 le16_to_cpu( 2695 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 2696 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2697 info_v2_1->extdispconninfo.path[i].auxddclut_index; 2698 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2699 info_v2_1->extdispconninfo.path[i].hpdlut_index; 2700 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2701 info_v2_1->extdispconninfo.path[i].channelmapping; 2702 info->ext_disp_conn_info.path[i].caps = 2703 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 2704 } 2705 2706 info->ext_disp_conn_info.checksum = 2707 info_v2_1->extdispconninfo.checksum; 2708 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 2709 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 2710 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 2711 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 2712 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2713 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 2714 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2715 } 2716 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 2717 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 2718 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2719 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2720 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2721 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2722 } 2723 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 2724 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 2725 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 2726 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 2727 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2728 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 2729 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2730 } 2731 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 2732 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 2733 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2734 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2735 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2736 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2737 } 2738 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 2739 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 2740 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 2741 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 2742 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2743 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 2744 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2745 } 2746 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 2747 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 2748 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2749 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2750 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2751 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2752 } 2753 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 2754 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 2755 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 2756 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 2757 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 2758 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 2759 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 2760 } 2761 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 2762 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 2763 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 2764 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 2765 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 2766 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 2767 } 2768 2769 info->edp1_info.edp_backlight_pwm_hz = 2770 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 2771 info->edp1_info.edp_ss_percentage = 2772 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 2773 info->edp1_info.edp_ss_rate_10hz = 2774 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 2775 info->edp1_info.edp_pwr_on_off_delay = 2776 info_v2_1->edp1_info.edp_pwr_on_off_delay; 2777 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2778 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 2779 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2780 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2781 info->edp1_info.edp_panel_bpc = 2782 info_v2_1->edp1_info.edp_panel_bpc; 2783 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level; 2784 2785 info->edp2_info.edp_backlight_pwm_hz = 2786 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 2787 info->edp2_info.edp_ss_percentage = 2788 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 2789 info->edp2_info.edp_ss_rate_10hz = 2790 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 2791 info->edp2_info.edp_pwr_on_off_delay = 2792 info_v2_1->edp2_info.edp_pwr_on_off_delay; 2793 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2794 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 2795 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2796 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2797 info->edp2_info.edp_panel_bpc = 2798 info_v2_1->edp2_info.edp_panel_bpc; 2799 info->edp2_info.edp_bootup_bl_level = 2800 info_v2_1->edp2_info.edp_bootup_bl_level; 2801 2802 return BP_RESULT_OK; 2803 } 2804 2805 static enum bp_result get_integrated_info_v2_2( 2806 struct bios_parser *bp, 2807 struct integrated_info *info) 2808 { 2809 struct atom_integrated_system_info_v2_2 *info_v2_2; 2810 uint32_t i; 2811 2812 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2, 2813 DATA_TABLES(integratedsysteminfo)); 2814 2815 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage); 2816 2817 if (info_v2_2 == NULL) 2818 return BP_RESULT_BADBIOSTABLE; 2819 2820 info->gpu_cap_info = 2821 le32_to_cpu(info_v2_2->gpucapinfo); 2822 /* 2823 * system_config: Bit[0] = 0 : PCIE power gating disabled 2824 * = 1 : PCIE power gating enabled 2825 * Bit[1] = 0 : DDR-PLL shut down disabled 2826 * = 1 : DDR-PLL shut down enabled 2827 * Bit[2] = 0 : DDR-PLL power down disabled 2828 * = 1 : DDR-PLL power down enabled 2829 */ 2830 info->system_config = le32_to_cpu(info_v2_2->system_config); 2831 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo); 2832 info->memory_type = info_v2_2->memorytype; 2833 info->ma_channel_number = info_v2_2->umachannelnumber; 2834 info->dp_ss_control = 2835 le16_to_cpu(info_v2_2->reserved1); 2836 2837 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2838 info->ext_disp_conn_info.gu_id[i] = 2839 info_v2_2->extdispconninfo.guid[i]; 2840 } 2841 2842 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2843 info->ext_disp_conn_info.path[i].device_connector_id = 2844 object_id_from_bios_object_id( 2845 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid)); 2846 2847 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2848 object_id_from_bios_object_id( 2849 le16_to_cpu( 2850 info_v2_2->extdispconninfo.path[i].ext_encoder_objid)); 2851 2852 info->ext_disp_conn_info.path[i].device_tag = 2853 le16_to_cpu( 2854 info_v2_2->extdispconninfo.path[i].device_tag); 2855 info->ext_disp_conn_info.path[i].device_acpi_enum = 2856 le16_to_cpu( 2857 info_v2_2->extdispconninfo.path[i].device_acpi_enum); 2858 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2859 info_v2_2->extdispconninfo.path[i].auxddclut_index; 2860 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2861 info_v2_2->extdispconninfo.path[i].hpdlut_index; 2862 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2863 info_v2_2->extdispconninfo.path[i].channelmapping; 2864 info->ext_disp_conn_info.path[i].caps = 2865 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps); 2866 } 2867 2868 info->ext_disp_conn_info.checksum = 2869 info_v2_2->extdispconninfo.checksum; 2870 info->ext_disp_conn_info.fixdpvoltageswing = 2871 info_v2_2->extdispconninfo.fixdpvoltageswing; 2872 2873 info->edp1_info.edp_backlight_pwm_hz = 2874 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz); 2875 info->edp1_info.edp_ss_percentage = 2876 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage); 2877 info->edp1_info.edp_ss_rate_10hz = 2878 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz); 2879 info->edp1_info.edp_pwr_on_off_delay = 2880 info_v2_2->edp1_info.edp_pwr_on_off_delay; 2881 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 2882 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon; 2883 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 2884 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 2885 info->edp1_info.edp_panel_bpc = 2886 info_v2_2->edp1_info.edp_panel_bpc; 2887 info->edp1_info.edp_bootup_bl_level = 2888 2889 info->edp2_info.edp_backlight_pwm_hz = 2890 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz); 2891 info->edp2_info.edp_ss_percentage = 2892 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage); 2893 info->edp2_info.edp_ss_rate_10hz = 2894 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz); 2895 info->edp2_info.edp_pwr_on_off_delay = 2896 info_v2_2->edp2_info.edp_pwr_on_off_delay; 2897 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 2898 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon; 2899 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 2900 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 2901 info->edp2_info.edp_panel_bpc = 2902 info_v2_2->edp2_info.edp_panel_bpc; 2903 info->edp2_info.edp_bootup_bl_level = 2904 info_v2_2->edp2_info.edp_bootup_bl_level; 2905 2906 return BP_RESULT_OK; 2907 } 2908 2909 /* 2910 * construct_integrated_info 2911 * 2912 * @brief 2913 * Get integrated BIOS information based on table revision 2914 * 2915 * @param 2916 * bios_parser *bp - [in]BIOS parser handler to get master data table 2917 * integrated_info *info - [out] store and output integrated info 2918 * 2919 * @return 2920 * static enum bp_result - BP_RESULT_OK if information is available, 2921 * BP_RESULT_BADBIOSTABLE otherwise. 2922 */ 2923 static enum bp_result construct_integrated_info( 2924 struct bios_parser *bp, 2925 struct integrated_info *info) 2926 { 2927 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 2928 2929 struct atom_common_table_header *header; 2930 struct atom_data_revision revision; 2931 2932 uint32_t i; 2933 uint32_t j; 2934 2935 if (info && DATA_TABLES(integratedsysteminfo)) { 2936 header = GET_IMAGE(struct atom_common_table_header, 2937 DATA_TABLES(integratedsysteminfo)); 2938 2939 get_atom_data_table_revision(header, &revision); 2940 2941 switch (revision.major) { 2942 case 1: 2943 switch (revision.minor) { 2944 case 11: 2945 case 12: 2946 result = get_integrated_info_v11(bp, info); 2947 break; 2948 default: 2949 return result; 2950 } 2951 break; 2952 case 2: 2953 switch (revision.minor) { 2954 case 1: 2955 result = get_integrated_info_v2_1(bp, info); 2956 break; 2957 case 2: 2958 result = get_integrated_info_v2_2(bp, info); 2959 break; 2960 default: 2961 return result; 2962 } 2963 break; 2964 default: 2965 return result; 2966 } 2967 if (result == BP_RESULT_OK) { 2968 2969 DC_LOG_BIOS("edp1:\n" 2970 "\tedp_pwr_on_off_delay = %d\n" 2971 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2972 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2973 "\tedp_bootup_bl_level = %d\n", 2974 info->edp1_info.edp_pwr_on_off_delay, 2975 info->edp1_info.edp_pwr_on_vary_bl_to_blon, 2976 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff, 2977 info->edp1_info.edp_bootup_bl_level); 2978 DC_LOG_BIOS("edp2:\n" 2979 "\tedp_pwr_on_off_delayv = %d\n" 2980 "\tedp_pwr_on_vary_bl_to_blon = %d\n" 2981 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n" 2982 "\tedp_bootup_bl_level = %d\n", 2983 info->edp2_info.edp_pwr_on_off_delay, 2984 info->edp2_info.edp_pwr_on_vary_bl_to_blon, 2985 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff, 2986 info->edp2_info.edp_bootup_bl_level); 2987 } 2988 } 2989 2990 if (result != BP_RESULT_OK) 2991 return result; 2992 else { 2993 // Log each external path 2994 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 2995 if (info->ext_disp_conn_info.path[i].device_tag != 0) 2996 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n" 2997 "DEVICE_TAG: 0x%x\n" 2998 "DEVICE_ACPI_ENUM: 0x%x\n" 2999 "DEVICE_CONNECTOR_ID: 0x%x\n" 3000 "EXT_AUX_DDC_LUT_INDEX: %d\n" 3001 "EXT_HPD_PIN_LUT_INDEX: %d\n" 3002 "EXT_ENCODER_OBJ_ID: 0x%x\n" 3003 "Encoder CAPS: 0x%x\n", 3004 i, 3005 info->ext_disp_conn_info.path[i].device_tag, 3006 info->ext_disp_conn_info.path[i].device_acpi_enum, 3007 info->ext_disp_conn_info.path[i].device_connector_id.id, 3008 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index, 3009 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index, 3010 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id, 3011 info->ext_disp_conn_info.path[i].caps 3012 ); 3013 if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) 3014 DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3015 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) { 3016 info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN; 3017 DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i); 3018 } 3019 } 3020 // Log the Checksum and Voltage Swing 3021 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n" 3022 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n", 3023 info->ext_disp_conn_info.checksum, 3024 info->ext_disp_conn_info.fixdpvoltageswing); 3025 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) { 3026 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF; 3027 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing); 3028 } 3029 } 3030 /* Sort voltage table from low to high*/ 3031 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 3032 for (j = i; j > 0; --j) { 3033 if (info->disp_clk_voltage[j].max_supported_clk < 3034 info->disp_clk_voltage[j-1].max_supported_clk) 3035 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]); 3036 } 3037 } 3038 3039 return result; 3040 } 3041 3042 static enum bp_result bios_parser_get_vram_info( 3043 struct dc_bios *dcb, 3044 struct dc_vram_info *info) 3045 { 3046 struct bios_parser *bp = BP_FROM_DCB(dcb); 3047 static enum bp_result result = BP_RESULT_BADBIOSTABLE; 3048 struct atom_common_table_header *header; 3049 struct atom_data_revision revision; 3050 3051 if (info && DATA_TABLES(vram_info)) { 3052 header = GET_IMAGE(struct atom_common_table_header, 3053 DATA_TABLES(vram_info)); 3054 3055 get_atom_data_table_revision(header, &revision); 3056 3057 switch (revision.major) { 3058 case 2: 3059 switch (revision.minor) { 3060 case 3: 3061 result = get_vram_info_v23(bp, info); 3062 break; 3063 case 4: 3064 result = get_vram_info_v24(bp, info); 3065 break; 3066 case 5: 3067 result = get_vram_info_v25(bp, info); 3068 break; 3069 default: 3070 break; 3071 } 3072 break; 3073 3074 case 3: 3075 switch (revision.minor) { 3076 case 0: 3077 result = get_vram_info_v30(bp, info); 3078 break; 3079 default: 3080 break; 3081 } 3082 break; 3083 3084 default: 3085 return result; 3086 } 3087 3088 } 3089 return result; 3090 } 3091 3092 static struct integrated_info *bios_parser_create_integrated_info( 3093 struct dc_bios *dcb) 3094 { 3095 struct bios_parser *bp = BP_FROM_DCB(dcb); 3096 struct integrated_info *info = NULL; 3097 3098 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 3099 3100 if (info == NULL) { 3101 ASSERT_CRITICAL(0); 3102 return NULL; 3103 } 3104 3105 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 3106 return info; 3107 3108 kfree(info); 3109 3110 return NULL; 3111 } 3112 3113 static enum bp_result update_slot_layout_info( 3114 struct dc_bios *dcb, 3115 unsigned int i, 3116 struct slot_layout_info *slot_layout_info) 3117 { 3118 unsigned int record_offset; 3119 unsigned int j; 3120 struct atom_display_object_path_v2 *object; 3121 struct atom_bracket_layout_record *record; 3122 struct atom_common_record_header *record_header; 3123 static enum bp_result result; 3124 struct bios_parser *bp; 3125 struct object_info_table *tbl; 3126 struct display_object_info_table_v1_4 *v1_4; 3127 3128 record = NULL; 3129 record_header = NULL; 3130 result = BP_RESULT_NORECORD; 3131 3132 bp = BP_FROM_DCB(dcb); 3133 tbl = &bp->object_info_tbl; 3134 v1_4 = tbl->v1_4; 3135 3136 object = &v1_4->display_path[i]; 3137 record_offset = (unsigned int) 3138 (object->disp_recordoffset) + 3139 (unsigned int)(bp->object_info_tbl_offset); 3140 3141 for (;;) { 3142 3143 record_header = (struct atom_common_record_header *) 3144 GET_IMAGE(struct atom_common_record_header, 3145 record_offset); 3146 if (record_header == NULL) { 3147 result = BP_RESULT_BADBIOSTABLE; 3148 break; 3149 } 3150 3151 /* the end of the list */ 3152 if (record_header->record_type == 0xff || 3153 record_header->record_size == 0) { 3154 break; 3155 } 3156 3157 if (record_header->record_type == 3158 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 3159 sizeof(struct atom_bracket_layout_record) 3160 <= record_header->record_size) { 3161 record = (struct atom_bracket_layout_record *) 3162 (record_header); 3163 result = BP_RESULT_OK; 3164 break; 3165 } 3166 3167 record_offset += record_header->record_size; 3168 } 3169 3170 /* return if the record not found */ 3171 if (result != BP_RESULT_OK) 3172 return result; 3173 3174 /* get slot sizes */ 3175 slot_layout_info->length = record->bracketlen; 3176 slot_layout_info->width = record->bracketwidth; 3177 3178 /* get info for each connector in the slot */ 3179 slot_layout_info->num_of_connectors = record->conn_num; 3180 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 3181 slot_layout_info->connectors[j].connector_type = 3182 (enum connector_layout_type) 3183 (record->conn_info[j].connector_type); 3184 switch (record->conn_info[j].connector_type) { 3185 case CONNECTOR_TYPE_DVI_D: 3186 slot_layout_info->connectors[j].connector_type = 3187 CONNECTOR_LAYOUT_TYPE_DVI_D; 3188 slot_layout_info->connectors[j].length = 3189 CONNECTOR_SIZE_DVI; 3190 break; 3191 3192 case CONNECTOR_TYPE_HDMI: 3193 slot_layout_info->connectors[j].connector_type = 3194 CONNECTOR_LAYOUT_TYPE_HDMI; 3195 slot_layout_info->connectors[j].length = 3196 CONNECTOR_SIZE_HDMI; 3197 break; 3198 3199 case CONNECTOR_TYPE_DISPLAY_PORT: 3200 slot_layout_info->connectors[j].connector_type = 3201 CONNECTOR_LAYOUT_TYPE_DP; 3202 slot_layout_info->connectors[j].length = 3203 CONNECTOR_SIZE_DP; 3204 break; 3205 3206 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 3207 slot_layout_info->connectors[j].connector_type = 3208 CONNECTOR_LAYOUT_TYPE_MINI_DP; 3209 slot_layout_info->connectors[j].length = 3210 CONNECTOR_SIZE_MINI_DP; 3211 break; 3212 3213 default: 3214 slot_layout_info->connectors[j].connector_type = 3215 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3216 slot_layout_info->connectors[j].length = 3217 CONNECTOR_SIZE_UNKNOWN; 3218 } 3219 3220 slot_layout_info->connectors[j].position = 3221 record->conn_info[j].position; 3222 slot_layout_info->connectors[j].connector_id = 3223 object_id_from_bios_object_id( 3224 record->conn_info[j].connectorobjid); 3225 } 3226 return result; 3227 } 3228 3229 static enum bp_result update_slot_layout_info_v2( 3230 struct dc_bios *dcb, 3231 unsigned int i, 3232 struct slot_layout_info *slot_layout_info) 3233 { 3234 unsigned int record_offset; 3235 struct atom_display_object_path_v3 *object; 3236 struct atom_bracket_layout_record_v2 *record; 3237 struct atom_common_record_header *record_header; 3238 static enum bp_result result; 3239 struct bios_parser *bp; 3240 struct object_info_table *tbl; 3241 struct display_object_info_table_v1_5 *v1_5; 3242 struct graphics_object_id connector_id; 3243 3244 record = NULL; 3245 record_header = NULL; 3246 result = BP_RESULT_NORECORD; 3247 3248 bp = BP_FROM_DCB(dcb); 3249 tbl = &bp->object_info_tbl; 3250 v1_5 = tbl->v1_5; 3251 3252 object = &v1_5->display_path[i]; 3253 record_offset = (unsigned int) 3254 (object->disp_recordoffset) + 3255 (unsigned int)(bp->object_info_tbl_offset); 3256 3257 for (;;) { 3258 3259 record_header = (struct atom_common_record_header *) 3260 GET_IMAGE(struct atom_common_record_header, 3261 record_offset); 3262 if (record_header == NULL) { 3263 result = BP_RESULT_BADBIOSTABLE; 3264 break; 3265 } 3266 3267 /* the end of the list */ 3268 if (record_header->record_type == ATOM_RECORD_END_TYPE || 3269 record_header->record_size == 0) { 3270 break; 3271 } 3272 3273 if (record_header->record_type == 3274 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE && 3275 sizeof(struct atom_bracket_layout_record_v2) 3276 <= record_header->record_size) { 3277 record = (struct atom_bracket_layout_record_v2 *) 3278 (record_header); 3279 result = BP_RESULT_OK; 3280 break; 3281 } 3282 3283 record_offset += record_header->record_size; 3284 } 3285 3286 /* return if the record not found */ 3287 if (result != BP_RESULT_OK) 3288 return result; 3289 3290 /* get slot sizes */ 3291 connector_id = object_id_from_bios_object_id(object->display_objid); 3292 3293 slot_layout_info->length = record->bracketlen; 3294 slot_layout_info->width = record->bracketwidth; 3295 slot_layout_info->num_of_connectors = v1_5->number_of_path; 3296 slot_layout_info->connectors[i].position = record->conn_num; 3297 slot_layout_info->connectors[i].connector_id = connector_id; 3298 3299 switch (connector_id.id) { 3300 case CONNECTOR_ID_SINGLE_LINK_DVID: 3301 case CONNECTOR_ID_DUAL_LINK_DVID: 3302 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D; 3303 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI; 3304 break; 3305 3306 case CONNECTOR_ID_HDMI_TYPE_A: 3307 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI; 3308 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI; 3309 break; 3310 3311 case CONNECTOR_ID_DISPLAY_PORT: 3312 case CONNECTOR_ID_USBC: 3313 if (record->mini_type == MINI_TYPE_NORMAL) { 3314 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP; 3315 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP; 3316 } else { 3317 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP; 3318 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP; 3319 } 3320 break; 3321 3322 default: 3323 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN; 3324 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN; 3325 } 3326 return result; 3327 } 3328 3329 static enum bp_result get_bracket_layout_record( 3330 struct dc_bios *dcb, 3331 unsigned int bracket_layout_id, 3332 struct slot_layout_info *slot_layout_info) 3333 { 3334 unsigned int i; 3335 struct bios_parser *bp = BP_FROM_DCB(dcb); 3336 static enum bp_result result; 3337 struct object_info_table *tbl; 3338 struct display_object_info_table_v1_4 *v1_4; 3339 struct display_object_info_table_v1_5 *v1_5; 3340 3341 if (slot_layout_info == NULL) { 3342 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 3343 return BP_RESULT_BADINPUT; 3344 } 3345 tbl = &bp->object_info_tbl; 3346 v1_4 = tbl->v1_4; 3347 v1_5 = tbl->v1_5; 3348 3349 result = BP_RESULT_NORECORD; 3350 switch (bp->object_info_tbl.revision.minor) { 3351 case 4: 3352 default: 3353 for (i = 0; i < v1_4->number_of_path; ++i) { 3354 if (bracket_layout_id == 3355 v1_4->display_path[i].display_objid) { 3356 result = update_slot_layout_info(dcb, i, slot_layout_info); 3357 break; 3358 } 3359 } 3360 break; 3361 case 5: 3362 for (i = 0; i < v1_5->number_of_path; ++i) 3363 result = update_slot_layout_info_v2(dcb, i, slot_layout_info); 3364 break; 3365 } 3366 return result; 3367 } 3368 3369 static enum bp_result bios_get_board_layout_info( 3370 struct dc_bios *dcb, 3371 struct board_layout_info *board_layout_info) 3372 { 3373 unsigned int i; 3374 3375 struct bios_parser *bp; 3376 3377 static enum bp_result record_result; 3378 unsigned int max_slots; 3379 3380 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 3381 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 3382 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 3383 0, 0 3384 }; 3385 3386 3387 bp = BP_FROM_DCB(dcb); 3388 3389 if (board_layout_info == NULL) { 3390 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 3391 return BP_RESULT_BADINPUT; 3392 } 3393 3394 board_layout_info->num_of_slots = 0; 3395 max_slots = MAX_BOARD_SLOTS; 3396 3397 // Assume single slot on v1_5 3398 if (bp->object_info_tbl.revision.minor == 5) { 3399 max_slots = 1; 3400 } 3401 3402 for (i = 0; i < max_slots; ++i) { 3403 record_result = get_bracket_layout_record(dcb, 3404 slot_index_to_vbios_id[i], 3405 &board_layout_info->slots[i]); 3406 3407 if (record_result == BP_RESULT_NORECORD && i > 0) 3408 break; /* no more slots present in bios */ 3409 else if (record_result != BP_RESULT_OK) 3410 return record_result; /* fail */ 3411 3412 ++board_layout_info->num_of_slots; 3413 } 3414 3415 /* all data is valid */ 3416 board_layout_info->is_number_of_slots_valid = 1; 3417 board_layout_info->is_slots_size_valid = 1; 3418 board_layout_info->is_connector_offsets_valid = 1; 3419 board_layout_info->is_connector_lengths_valid = 1; 3420 3421 return BP_RESULT_OK; 3422 } 3423 3424 3425 static uint16_t bios_parser_pack_data_tables( 3426 struct dc_bios *dcb, 3427 void *dst) 3428 { 3429 // TODO: There is data bytes alignment issue, disable it for now. 3430 return 0; 3431 } 3432 3433 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 3434 struct bios_parser *bp, 3435 uint32_t rev_major, 3436 uint32_t rev_minor, 3437 uint16_t *dc_golden_table_ver) 3438 { 3439 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 3440 uint32_t dc_golden_offset = 0; 3441 *dc_golden_table_ver = 0; 3442 3443 if (!DATA_TABLES(dce_info)) 3444 return NULL; 3445 3446 /* ver.4.4 or higher */ 3447 switch (rev_major) { 3448 case 4: 3449 switch (rev_minor) { 3450 case 4: 3451 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 3452 DATA_TABLES(dce_info)); 3453 if (!disp_cntl_tbl_4_4) 3454 return NULL; 3455 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 3456 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 3457 break; 3458 case 5: 3459 default: 3460 /* For atom_display_controller_info_v4_5 there is no need to get golden table from 3461 * dc_golden_table_offset as all these fields previously in golden table used for AUX 3462 * pre-charge settings are now available directly in atom_display_controller_info_v4_5. 3463 */ 3464 break; 3465 } 3466 break; 3467 } 3468 3469 if (!dc_golden_offset) 3470 return NULL; 3471 3472 if (*dc_golden_table_ver != 1) 3473 return NULL; 3474 3475 return GET_IMAGE(struct atom_dc_golden_table_v1, 3476 dc_golden_offset); 3477 } 3478 3479 static enum bp_result bios_get_atom_dc_golden_table( 3480 struct dc_bios *dcb) 3481 { 3482 struct bios_parser *bp = BP_FROM_DCB(dcb); 3483 enum bp_result result = BP_RESULT_OK; 3484 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 3485 struct atom_common_table_header *header; 3486 struct atom_data_revision tbl_revision; 3487 uint16_t dc_golden_table_ver = 0; 3488 3489 header = GET_IMAGE(struct atom_common_table_header, 3490 DATA_TABLES(dce_info)); 3491 if (!header) 3492 return BP_RESULT_UNSUPPORTED; 3493 3494 get_atom_data_table_revision(header, &tbl_revision); 3495 3496 atom_dc_golden_table = bios_get_golden_table(bp, 3497 tbl_revision.major, 3498 tbl_revision.minor, 3499 &dc_golden_table_ver); 3500 3501 if (!atom_dc_golden_table) 3502 return BP_RESULT_UNSUPPORTED; 3503 3504 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 3505 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 3506 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 3507 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 3508 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 3509 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 3510 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 3511 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 3512 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 3513 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 3514 3515 return result; 3516 } 3517 3518 3519 static const struct dc_vbios_funcs vbios_funcs = { 3520 .get_connectors_number = bios_parser_get_connectors_number, 3521 3522 .get_connector_id = bios_parser_get_connector_id, 3523 3524 .get_src_obj = bios_parser_get_src_obj, 3525 3526 .get_i2c_info = bios_parser_get_i2c_info, 3527 3528 .get_hpd_info = bios_parser_get_hpd_info, 3529 3530 .get_device_tag = bios_parser_get_device_tag, 3531 3532 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 3533 3534 .get_ss_entry_number = bios_parser_get_ss_entry_number, 3535 3536 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 3537 3538 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 3539 3540 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 3541 3542 .is_device_id_supported = bios_parser_is_device_id_supported, 3543 3544 .is_accelerated_mode = bios_parser_is_accelerated_mode, 3545 3546 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 3547 3548 3549 /* COMMANDS */ 3550 .encoder_control = bios_parser_encoder_control, 3551 3552 .transmitter_control = bios_parser_transmitter_control, 3553 3554 .enable_crtc = bios_parser_enable_crtc, 3555 3556 .set_pixel_clock = bios_parser_set_pixel_clock, 3557 3558 .set_dce_clock = bios_parser_set_dce_clock, 3559 3560 .program_crtc_timing = bios_parser_program_crtc_timing, 3561 3562 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 3563 3564 .bios_parser_destroy = firmware_parser_destroy, 3565 3566 .get_board_layout_info = bios_get_board_layout_info, 3567 /* TODO: use this fn in hw init?*/ 3568 .pack_data_tables = bios_parser_pack_data_tables, 3569 3570 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 3571 3572 .enable_lvtma_control = bios_parser_enable_lvtma_control, 3573 3574 .get_soc_bb_info = bios_parser_get_soc_bb_info, 3575 3576 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 3577 3578 .get_lttpr_caps = bios_parser_get_lttpr_caps, 3579 3580 .get_lttpr_interop = bios_parser_get_lttpr_interop, 3581 3582 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info, 3583 }; 3584 3585 static bool bios_parser2_construct( 3586 struct bios_parser *bp, 3587 struct bp_init_data *init, 3588 enum dce_version dce_version) 3589 { 3590 uint16_t *rom_header_offset = NULL; 3591 struct atom_rom_header_v2_2 *rom_header = NULL; 3592 struct display_object_info_table_v1_4 *object_info_tbl; 3593 struct atom_data_revision tbl_rev = {0}; 3594 3595 if (!init) 3596 return false; 3597 3598 if (!init->bios) 3599 return false; 3600 3601 bp->base.funcs = &vbios_funcs; 3602 bp->base.bios = init->bios; 3603 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 3604 3605 bp->base.ctx = init->ctx; 3606 3607 bp->base.bios_local_image = NULL; 3608 3609 rom_header_offset = 3610 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 3611 3612 if (!rom_header_offset) 3613 return false; 3614 3615 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 3616 3617 if (!rom_header) 3618 return false; 3619 3620 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 3621 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 3622 return false; 3623 3624 bp->master_data_tbl = 3625 GET_IMAGE(struct atom_master_data_table_v2_1, 3626 rom_header->masterdatatable_offset); 3627 3628 if (!bp->master_data_tbl) 3629 return false; 3630 3631 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 3632 3633 if (!bp->object_info_tbl_offset) 3634 return false; 3635 3636 object_info_tbl = 3637 GET_IMAGE(struct display_object_info_table_v1_4, 3638 bp->object_info_tbl_offset); 3639 3640 if (!object_info_tbl) 3641 return false; 3642 3643 get_atom_data_table_revision(&object_info_tbl->table_header, 3644 &bp->object_info_tbl.revision); 3645 3646 if (bp->object_info_tbl.revision.major == 1 3647 && bp->object_info_tbl.revision.minor == 4) { 3648 struct display_object_info_table_v1_4 *tbl_v1_4; 3649 3650 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 3651 bp->object_info_tbl_offset); 3652 if (!tbl_v1_4) 3653 return false; 3654 3655 bp->object_info_tbl.v1_4 = tbl_v1_4; 3656 } else if (bp->object_info_tbl.revision.major == 1 3657 && bp->object_info_tbl.revision.minor == 5) { 3658 struct display_object_info_table_v1_5 *tbl_v1_5; 3659 3660 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5, 3661 bp->object_info_tbl_offset); 3662 if (!tbl_v1_5) 3663 return false; 3664 3665 bp->object_info_tbl.v1_5 = tbl_v1_5; 3666 } else { 3667 ASSERT(0); 3668 return false; 3669 } 3670 3671 dal_firmware_parser_init_cmd_tbl(bp); 3672 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 3673 3674 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3675 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3676 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 3677 3678 return true; 3679 } 3680 3681 struct dc_bios *firmware_parser_create( 3682 struct bp_init_data *init, 3683 enum dce_version dce_version) 3684 { 3685 struct bios_parser *bp = NULL; 3686 3687 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 3688 if (!bp) 3689 return NULL; 3690 3691 if (bios_parser2_construct(bp, init, dce_version)) 3692 return &bp->base; 3693 3694 kfree(bp); 3695 return NULL; 3696 } 3697 3698 3699