1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @dcb: pointer to the DC BIOS 489 * @gpio_id: GPIO ID 490 * @info: GpioPin information structure 491 * return: Bios parser result code 492 * note: 493 * to get the GPIO PIN INFO, we need: 494 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 495 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 496 * to get the registerA offset/mask 497 */ 498 static enum bp_result bios_parser_get_gpio_pin_info( 499 struct dc_bios *dcb, 500 uint32_t gpio_id, 501 struct gpio_pin_info *info) 502 { 503 struct bios_parser *bp = BP_FROM_DCB(dcb); 504 struct atom_gpio_pin_lut_v2_1 *header; 505 uint32_t count = 0; 506 uint32_t i = 0; 507 508 if (!DATA_TABLES(gpio_pin_lut)) 509 return BP_RESULT_BADBIOSTABLE; 510 511 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 512 DATA_TABLES(gpio_pin_lut)); 513 if (!header) 514 return BP_RESULT_BADBIOSTABLE; 515 516 if (sizeof(struct atom_common_table_header) + 517 sizeof(struct atom_gpio_pin_assignment) 518 > le16_to_cpu(header->table_header.structuresize)) 519 return BP_RESULT_BADBIOSTABLE; 520 521 if (header->table_header.content_revision != 1) 522 return BP_RESULT_UNSUPPORTED; 523 524 /* Temporary hard code gpio pin info */ 525 #if defined(FOR_SIMNOW_BOOT) 526 { 527 struct atom_gpio_pin_assignment gpio_pin[8] = { 528 {0x5db5, 0, 0, 1, 0}, 529 {0x5db5, 8, 8, 2, 0}, 530 {0x5db5, 0x10, 0x10, 3, 0}, 531 {0x5db5, 0x18, 0x14, 4, 0}, 532 {0x5db5, 0x1A, 0x18, 5, 0}, 533 {0x5db5, 0x1C, 0x1C, 6, 0}, 534 }; 535 536 count = 6; 537 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 538 } 539 #else 540 count = (le16_to_cpu(header->table_header.structuresize) 541 - sizeof(struct atom_common_table_header)) 542 / sizeof(struct atom_gpio_pin_assignment); 543 #endif 544 for (i = 0; i < count; ++i) { 545 if (header->gpio_pin[i].gpio_id != gpio_id) 546 continue; 547 548 info->offset = 549 (uint32_t) le16_to_cpu( 550 header->gpio_pin[i].data_a_reg_index); 551 info->offset_y = info->offset + 2; 552 info->offset_en = info->offset + 1; 553 info->offset_mask = info->offset - 1; 554 555 info->mask = (uint32_t) (1 << 556 header->gpio_pin[i].gpio_bitshift); 557 info->mask_y = info->mask + 2; 558 info->mask_en = info->mask + 1; 559 info->mask_mask = info->mask - 1; 560 561 return BP_RESULT_OK; 562 } 563 564 return BP_RESULT_NORECORD; 565 } 566 567 static struct device_id device_type_from_device_id(uint16_t device_id) 568 { 569 570 struct device_id result_device_id; 571 572 result_device_id.raw_device_tag = device_id; 573 574 switch (device_id) { 575 case ATOM_DISPLAY_LCD1_SUPPORT: 576 result_device_id.device_type = DEVICE_TYPE_LCD; 577 result_device_id.enum_id = 1; 578 break; 579 580 case ATOM_DISPLAY_DFP1_SUPPORT: 581 result_device_id.device_type = DEVICE_TYPE_DFP; 582 result_device_id.enum_id = 1; 583 break; 584 585 case ATOM_DISPLAY_DFP2_SUPPORT: 586 result_device_id.device_type = DEVICE_TYPE_DFP; 587 result_device_id.enum_id = 2; 588 break; 589 590 case ATOM_DISPLAY_DFP3_SUPPORT: 591 result_device_id.device_type = DEVICE_TYPE_DFP; 592 result_device_id.enum_id = 3; 593 break; 594 595 case ATOM_DISPLAY_DFP4_SUPPORT: 596 result_device_id.device_type = DEVICE_TYPE_DFP; 597 result_device_id.enum_id = 4; 598 break; 599 600 case ATOM_DISPLAY_DFP5_SUPPORT: 601 result_device_id.device_type = DEVICE_TYPE_DFP; 602 result_device_id.enum_id = 5; 603 break; 604 605 case ATOM_DISPLAY_DFP6_SUPPORT: 606 result_device_id.device_type = DEVICE_TYPE_DFP; 607 result_device_id.enum_id = 6; 608 break; 609 610 default: 611 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 612 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 613 result_device_id.enum_id = 0; 614 } 615 return result_device_id; 616 } 617 618 static enum bp_result bios_parser_get_device_tag( 619 struct dc_bios *dcb, 620 struct graphics_object_id connector_object_id, 621 uint32_t device_tag_index, 622 struct connector_device_tag_info *info) 623 { 624 struct bios_parser *bp = BP_FROM_DCB(dcb); 625 struct atom_display_object_path_v2 *object; 626 627 if (!info) 628 return BP_RESULT_BADINPUT; 629 630 /* getBiosObject will return MXM object */ 631 object = get_bios_object(bp, connector_object_id); 632 633 if (!object) { 634 BREAK_TO_DEBUGGER(); /* Invalid object id */ 635 return BP_RESULT_BADINPUT; 636 } 637 638 info->acpi_device = 0; /* BIOS no longer provides this */ 639 info->dev_id = device_type_from_device_id(object->device_tag); 640 641 return BP_RESULT_OK; 642 } 643 644 static enum bp_result get_ss_info_v4_1( 645 struct bios_parser *bp, 646 uint32_t id, 647 uint32_t index, 648 struct spread_spectrum_info *ss_info) 649 { 650 enum bp_result result = BP_RESULT_OK; 651 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 652 struct atom_smu_info_v3_3 *smu_info = NULL; 653 654 if (!ss_info) 655 return BP_RESULT_BADINPUT; 656 657 if (!DATA_TABLES(dce_info)) 658 return BP_RESULT_BADBIOSTABLE; 659 660 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 661 DATA_TABLES(dce_info)); 662 if (!disp_cntl_tbl) 663 return BP_RESULT_BADBIOSTABLE; 664 665 666 ss_info->type.STEP_AND_DELAY_INFO = false; 667 ss_info->spread_percentage_divider = 1000; 668 /* BIOS no longer uses target clock. Always enable for now */ 669 ss_info->target_clock_range = 0xffffffff; 670 671 switch (id) { 672 case AS_SIGNAL_TYPE_DVI: 673 ss_info->spread_spectrum_percentage = 674 disp_cntl_tbl->dvi_ss_percentage; 675 ss_info->spread_spectrum_range = 676 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 677 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 678 ss_info->type.CENTER_MODE = true; 679 break; 680 case AS_SIGNAL_TYPE_HDMI: 681 ss_info->spread_spectrum_percentage = 682 disp_cntl_tbl->hdmi_ss_percentage; 683 ss_info->spread_spectrum_range = 684 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 685 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 686 ss_info->type.CENTER_MODE = true; 687 break; 688 /* TODO LVDS not support anymore? */ 689 case AS_SIGNAL_TYPE_DISPLAY_PORT: 690 ss_info->spread_spectrum_percentage = 691 disp_cntl_tbl->dp_ss_percentage; 692 ss_info->spread_spectrum_range = 693 disp_cntl_tbl->dp_ss_rate_10hz * 10; 694 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 695 ss_info->type.CENTER_MODE = true; 696 break; 697 case AS_SIGNAL_TYPE_GPU_PLL: 698 /* atom_firmware: DAL only get data from dce_info table. 699 * if data within smu_info is needed for DAL, VBIOS should 700 * copy it into dce_info 701 */ 702 result = BP_RESULT_UNSUPPORTED; 703 break; 704 case AS_SIGNAL_TYPE_XGMI: 705 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 706 DATA_TABLES(smu_info)); 707 if (!smu_info) 708 return BP_RESULT_BADBIOSTABLE; 709 710 ss_info->spread_spectrum_percentage = 711 smu_info->waflclk_ss_percentage; 712 ss_info->spread_spectrum_range = 713 smu_info->gpuclk_ss_rate_10hz * 10; 714 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 715 ss_info->type.CENTER_MODE = true; 716 break; 717 default: 718 result = BP_RESULT_UNSUPPORTED; 719 } 720 721 return result; 722 } 723 724 static enum bp_result get_ss_info_v4_2( 725 struct bios_parser *bp, 726 uint32_t id, 727 uint32_t index, 728 struct spread_spectrum_info *ss_info) 729 { 730 enum bp_result result = BP_RESULT_OK; 731 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 732 struct atom_smu_info_v3_1 *smu_info = NULL; 733 734 if (!ss_info) 735 return BP_RESULT_BADINPUT; 736 737 if (!DATA_TABLES(dce_info)) 738 return BP_RESULT_BADBIOSTABLE; 739 740 if (!DATA_TABLES(smu_info)) 741 return BP_RESULT_BADBIOSTABLE; 742 743 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 744 DATA_TABLES(dce_info)); 745 if (!disp_cntl_tbl) 746 return BP_RESULT_BADBIOSTABLE; 747 748 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 749 if (!smu_info) 750 return BP_RESULT_BADBIOSTABLE; 751 752 ss_info->type.STEP_AND_DELAY_INFO = false; 753 ss_info->spread_percentage_divider = 1000; 754 /* BIOS no longer uses target clock. Always enable for now */ 755 ss_info->target_clock_range = 0xffffffff; 756 757 switch (id) { 758 case AS_SIGNAL_TYPE_DVI: 759 ss_info->spread_spectrum_percentage = 760 disp_cntl_tbl->dvi_ss_percentage; 761 ss_info->spread_spectrum_range = 762 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 763 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 764 ss_info->type.CENTER_MODE = true; 765 break; 766 case AS_SIGNAL_TYPE_HDMI: 767 ss_info->spread_spectrum_percentage = 768 disp_cntl_tbl->hdmi_ss_percentage; 769 ss_info->spread_spectrum_range = 770 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 771 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 772 ss_info->type.CENTER_MODE = true; 773 break; 774 /* TODO LVDS not support anymore? */ 775 case AS_SIGNAL_TYPE_DISPLAY_PORT: 776 ss_info->spread_spectrum_percentage = 777 smu_info->gpuclk_ss_percentage; 778 ss_info->spread_spectrum_range = 779 smu_info->gpuclk_ss_rate_10hz * 10; 780 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 781 ss_info->type.CENTER_MODE = true; 782 break; 783 case AS_SIGNAL_TYPE_GPU_PLL: 784 /* atom_firmware: DAL only get data from dce_info table. 785 * if data within smu_info is needed for DAL, VBIOS should 786 * copy it into dce_info 787 */ 788 result = BP_RESULT_UNSUPPORTED; 789 break; 790 default: 791 result = BP_RESULT_UNSUPPORTED; 792 } 793 794 return result; 795 } 796 797 /** 798 * bios_parser_get_spread_spectrum_info 799 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 800 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 801 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 802 * ver 3.1, 803 * there is only one entry for each signal /ss id. However, there is 804 * no planning of supporting multiple spread Sprectum entry for EverGreen 805 * @dcb: pointer to the DC BIOS 806 * @signal: ASSignalType to be converted to info index 807 * @index: number of entries that match the converted info index 808 * @ss_info: sprectrum information structure, 809 * return: Bios parser result code 810 */ 811 static enum bp_result bios_parser_get_spread_spectrum_info( 812 struct dc_bios *dcb, 813 enum as_signal_type signal, 814 uint32_t index, 815 struct spread_spectrum_info *ss_info) 816 { 817 struct bios_parser *bp = BP_FROM_DCB(dcb); 818 enum bp_result result = BP_RESULT_UNSUPPORTED; 819 struct atom_common_table_header *header; 820 struct atom_data_revision tbl_revision; 821 822 if (!ss_info) /* check for bad input */ 823 return BP_RESULT_BADINPUT; 824 825 if (!DATA_TABLES(dce_info)) 826 return BP_RESULT_UNSUPPORTED; 827 828 header = GET_IMAGE(struct atom_common_table_header, 829 DATA_TABLES(dce_info)); 830 get_atom_data_table_revision(header, &tbl_revision); 831 832 switch (tbl_revision.major) { 833 case 4: 834 switch (tbl_revision.minor) { 835 case 1: 836 return get_ss_info_v4_1(bp, signal, index, ss_info); 837 case 2: 838 case 3: 839 return get_ss_info_v4_2(bp, signal, index, ss_info); 840 default: 841 break; 842 } 843 break; 844 default: 845 break; 846 } 847 /* there can not be more then one entry for SS Info table */ 848 return result; 849 } 850 851 static enum bp_result get_soc_bb_info_v4_4( 852 struct bios_parser *bp, 853 struct bp_soc_bb_info *soc_bb_info) 854 { 855 enum bp_result result = BP_RESULT_OK; 856 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 857 858 if (!soc_bb_info) 859 return BP_RESULT_BADINPUT; 860 861 if (!DATA_TABLES(dce_info)) 862 return BP_RESULT_BADBIOSTABLE; 863 864 if (!DATA_TABLES(smu_info)) 865 return BP_RESULT_BADBIOSTABLE; 866 867 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 868 DATA_TABLES(dce_info)); 869 if (!disp_cntl_tbl) 870 return BP_RESULT_BADBIOSTABLE; 871 872 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 873 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 874 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 875 876 return result; 877 } 878 879 static enum bp_result bios_parser_get_soc_bb_info( 880 struct dc_bios *dcb, 881 struct bp_soc_bb_info *soc_bb_info) 882 { 883 struct bios_parser *bp = BP_FROM_DCB(dcb); 884 enum bp_result result = BP_RESULT_UNSUPPORTED; 885 struct atom_common_table_header *header; 886 struct atom_data_revision tbl_revision; 887 888 if (!soc_bb_info) /* check for bad input */ 889 return BP_RESULT_BADINPUT; 890 891 if (!DATA_TABLES(dce_info)) 892 return BP_RESULT_UNSUPPORTED; 893 894 header = GET_IMAGE(struct atom_common_table_header, 895 DATA_TABLES(dce_info)); 896 get_atom_data_table_revision(header, &tbl_revision); 897 898 switch (tbl_revision.major) { 899 case 4: 900 switch (tbl_revision.minor) { 901 case 1: 902 case 2: 903 case 3: 904 break; 905 case 4: 906 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 907 break; 908 default: 909 break; 910 } 911 break; 912 default: 913 break; 914 } 915 916 return result; 917 } 918 919 static enum bp_result get_embedded_panel_info_v2_1( 920 struct bios_parser *bp, 921 struct embedded_panel_info *info) 922 { 923 struct lcd_info_v2_1 *lvds; 924 925 if (!info) 926 return BP_RESULT_BADINPUT; 927 928 if (!DATA_TABLES(lcd_info)) 929 return BP_RESULT_UNSUPPORTED; 930 931 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 932 933 if (!lvds) 934 return BP_RESULT_BADBIOSTABLE; 935 936 /* TODO: previous vv1_3, should v2_1 */ 937 if (!((lvds->table_header.format_revision == 2) 938 && (lvds->table_header.content_revision >= 1))) 939 return BP_RESULT_UNSUPPORTED; 940 941 memset(info, 0, sizeof(struct embedded_panel_info)); 942 943 /* We need to convert from 10KHz units into KHz units */ 944 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 945 /* usHActive does not include borders, according to VBIOS team */ 946 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 947 /* usHBlanking_Time includes borders, so we should really be 948 * subtractingborders duing this translation, but LVDS generally 949 * doesn't have borders, so we should be okay leaving this as is for 950 * now. May need to revisit if we ever have LVDS with borders 951 */ 952 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 953 /* usVActive does not include borders, according to VBIOS team*/ 954 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 955 /* usVBlanking_Time includes borders, so we should really be 956 * subtracting borders duing this translation, but LVDS generally 957 * doesn't have borders, so we should be okay leaving this as is for 958 * now. May need to revisit if we ever have LVDS with borders 959 */ 960 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 961 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 962 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 963 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 964 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 965 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 966 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 967 968 /* not provided by VBIOS */ 969 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 970 971 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 972 & ATOM_HSYNC_POLARITY); 973 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 974 & ATOM_VSYNC_POLARITY); 975 976 /* not provided by VBIOS */ 977 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 978 979 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 980 & ATOM_H_REPLICATIONBY2); 981 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 982 & ATOM_V_REPLICATIONBY2); 983 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 984 & ATOM_COMPOSITESYNC); 985 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 986 987 /* not provided by VBIOS*/ 988 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 989 /* not provided by VBIOS*/ 990 info->ss_id = 0; 991 992 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 993 994 return BP_RESULT_OK; 995 } 996 997 static enum bp_result bios_parser_get_embedded_panel_info( 998 struct dc_bios *dcb, 999 struct embedded_panel_info *info) 1000 { 1001 struct bios_parser 1002 *bp = BP_FROM_DCB(dcb); 1003 struct atom_common_table_header *header; 1004 struct atom_data_revision tbl_revision; 1005 1006 if (!DATA_TABLES(lcd_info)) 1007 return BP_RESULT_FAILURE; 1008 1009 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1010 1011 if (!header) 1012 return BP_RESULT_BADBIOSTABLE; 1013 1014 get_atom_data_table_revision(header, &tbl_revision); 1015 1016 switch (tbl_revision.major) { 1017 case 2: 1018 switch (tbl_revision.minor) { 1019 case 1: 1020 return get_embedded_panel_info_v2_1(bp, info); 1021 default: 1022 break; 1023 } 1024 break; 1025 default: 1026 break; 1027 } 1028 1029 return BP_RESULT_FAILURE; 1030 } 1031 1032 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1033 { 1034 enum dal_device_type device_type = device_id.device_type; 1035 uint32_t enum_id = device_id.enum_id; 1036 1037 switch (device_type) { 1038 case DEVICE_TYPE_LCD: 1039 switch (enum_id) { 1040 case 1: 1041 return ATOM_DISPLAY_LCD1_SUPPORT; 1042 default: 1043 break; 1044 } 1045 break; 1046 case DEVICE_TYPE_DFP: 1047 switch (enum_id) { 1048 case 1: 1049 return ATOM_DISPLAY_DFP1_SUPPORT; 1050 case 2: 1051 return ATOM_DISPLAY_DFP2_SUPPORT; 1052 case 3: 1053 return ATOM_DISPLAY_DFP3_SUPPORT; 1054 case 4: 1055 return ATOM_DISPLAY_DFP4_SUPPORT; 1056 case 5: 1057 return ATOM_DISPLAY_DFP5_SUPPORT; 1058 case 6: 1059 return ATOM_DISPLAY_DFP6_SUPPORT; 1060 default: 1061 break; 1062 } 1063 break; 1064 default: 1065 break; 1066 } 1067 1068 /* Unidentified device ID, return empty support mask. */ 1069 return 0; 1070 } 1071 1072 static bool bios_parser_is_device_id_supported( 1073 struct dc_bios *dcb, 1074 struct device_id id) 1075 { 1076 struct bios_parser *bp = BP_FROM_DCB(dcb); 1077 1078 uint32_t mask = get_support_mask_for_device_id(id); 1079 1080 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1081 mask) != 0; 1082 } 1083 1084 static uint32_t bios_parser_get_ss_entry_number( 1085 struct dc_bios *dcb, 1086 enum as_signal_type signal) 1087 { 1088 /* TODO: DAL2 atomfirmware implementation does not need this. 1089 * why DAL3 need this? 1090 */ 1091 return 1; 1092 } 1093 1094 static enum bp_result bios_parser_transmitter_control( 1095 struct dc_bios *dcb, 1096 struct bp_transmitter_control *cntl) 1097 { 1098 struct bios_parser *bp = BP_FROM_DCB(dcb); 1099 1100 if (!bp->cmd_tbl.transmitter_control) 1101 return BP_RESULT_FAILURE; 1102 1103 return bp->cmd_tbl.transmitter_control(bp, cntl); 1104 } 1105 1106 static enum bp_result bios_parser_encoder_control( 1107 struct dc_bios *dcb, 1108 struct bp_encoder_control *cntl) 1109 { 1110 struct bios_parser *bp = BP_FROM_DCB(dcb); 1111 1112 if (!bp->cmd_tbl.dig_encoder_control) 1113 return BP_RESULT_FAILURE; 1114 1115 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1116 } 1117 1118 static enum bp_result bios_parser_set_pixel_clock( 1119 struct dc_bios *dcb, 1120 struct bp_pixel_clock_parameters *bp_params) 1121 { 1122 struct bios_parser *bp = BP_FROM_DCB(dcb); 1123 1124 if (!bp->cmd_tbl.set_pixel_clock) 1125 return BP_RESULT_FAILURE; 1126 1127 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1128 } 1129 1130 static enum bp_result bios_parser_set_dce_clock( 1131 struct dc_bios *dcb, 1132 struct bp_set_dce_clock_parameters *bp_params) 1133 { 1134 struct bios_parser *bp = BP_FROM_DCB(dcb); 1135 1136 if (!bp->cmd_tbl.set_dce_clock) 1137 return BP_RESULT_FAILURE; 1138 1139 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1140 } 1141 1142 static enum bp_result bios_parser_program_crtc_timing( 1143 struct dc_bios *dcb, 1144 struct bp_hw_crtc_timing_parameters *bp_params) 1145 { 1146 struct bios_parser *bp = BP_FROM_DCB(dcb); 1147 1148 if (!bp->cmd_tbl.set_crtc_timing) 1149 return BP_RESULT_FAILURE; 1150 1151 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1152 } 1153 1154 static enum bp_result bios_parser_enable_crtc( 1155 struct dc_bios *dcb, 1156 enum controller_id id, 1157 bool enable) 1158 { 1159 struct bios_parser *bp = BP_FROM_DCB(dcb); 1160 1161 if (!bp->cmd_tbl.enable_crtc) 1162 return BP_RESULT_FAILURE; 1163 1164 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1165 } 1166 1167 static enum bp_result bios_parser_enable_disp_power_gating( 1168 struct dc_bios *dcb, 1169 enum controller_id controller_id, 1170 enum bp_pipe_control_action action) 1171 { 1172 struct bios_parser *bp = BP_FROM_DCB(dcb); 1173 1174 if (!bp->cmd_tbl.enable_disp_power_gating) 1175 return BP_RESULT_FAILURE; 1176 1177 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1178 action); 1179 } 1180 1181 static enum bp_result bios_parser_enable_lvtma_control( 1182 struct dc_bios *dcb, 1183 uint8_t uc_pwr_on) 1184 { 1185 struct bios_parser *bp = BP_FROM_DCB(dcb); 1186 1187 if (!bp->cmd_tbl.enable_lvtma_control) 1188 return BP_RESULT_FAILURE; 1189 1190 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on); 1191 } 1192 1193 static bool bios_parser_is_accelerated_mode( 1194 struct dc_bios *dcb) 1195 { 1196 return bios_is_accelerated_mode(dcb); 1197 } 1198 1199 /** 1200 * bios_parser_set_scratch_critical_state - update critical state bit 1201 * in VBIOS scratch register 1202 * 1203 * @dcb: pointer to the DC BIO 1204 * @state: set or reset state 1205 */ 1206 static void bios_parser_set_scratch_critical_state( 1207 struct dc_bios *dcb, 1208 bool state) 1209 { 1210 bios_set_scratch_critical_state(dcb, state); 1211 } 1212 1213 static enum bp_result bios_parser_get_firmware_info( 1214 struct dc_bios *dcb, 1215 struct dc_firmware_info *info) 1216 { 1217 struct bios_parser *bp = BP_FROM_DCB(dcb); 1218 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1219 struct atom_common_table_header *header; 1220 1221 struct atom_data_revision revision; 1222 1223 if (info && DATA_TABLES(firmwareinfo)) { 1224 header = GET_IMAGE(struct atom_common_table_header, 1225 DATA_TABLES(firmwareinfo)); 1226 get_atom_data_table_revision(header, &revision); 1227 switch (revision.major) { 1228 case 3: 1229 switch (revision.minor) { 1230 case 1: 1231 result = get_firmware_info_v3_1(bp, info); 1232 break; 1233 case 2: 1234 case 3: 1235 case 4: 1236 result = get_firmware_info_v3_2(bp, info); 1237 break; 1238 default: 1239 break; 1240 } 1241 break; 1242 default: 1243 break; 1244 } 1245 } 1246 1247 return result; 1248 } 1249 1250 static enum bp_result get_firmware_info_v3_1( 1251 struct bios_parser *bp, 1252 struct dc_firmware_info *info) 1253 { 1254 struct atom_firmware_info_v3_1 *firmware_info; 1255 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1256 1257 if (!info) 1258 return BP_RESULT_BADINPUT; 1259 1260 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1261 DATA_TABLES(firmwareinfo)); 1262 1263 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1264 DATA_TABLES(dce_info)); 1265 1266 if (!firmware_info || !dce_info) 1267 return BP_RESULT_BADBIOSTABLE; 1268 1269 memset(info, 0, sizeof(*info)); 1270 1271 /* Pixel clock pll information. */ 1272 /* We need to convert from 10KHz units into KHz units */ 1273 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1274 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1275 1276 /* 27MHz for Vega10: */ 1277 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1278 1279 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1280 if (info->pll_info.crystal_frequency == 0) 1281 info->pll_info.crystal_frequency = 27000; 1282 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1283 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1284 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1285 1286 /* Get GPU PLL VCO Clock */ 1287 1288 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1289 /* VBIOS gives in 10KHz */ 1290 info->smu_gpu_pll_output_freq = 1291 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1292 } 1293 1294 info->oem_i2c_present = false; 1295 1296 return BP_RESULT_OK; 1297 } 1298 1299 static enum bp_result get_firmware_info_v3_2( 1300 struct bios_parser *bp, 1301 struct dc_firmware_info *info) 1302 { 1303 struct atom_firmware_info_v3_2 *firmware_info; 1304 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1305 struct atom_common_table_header *header; 1306 struct atom_data_revision revision; 1307 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1308 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1309 1310 if (!info) 1311 return BP_RESULT_BADINPUT; 1312 1313 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1314 DATA_TABLES(firmwareinfo)); 1315 1316 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1317 DATA_TABLES(dce_info)); 1318 1319 if (!firmware_info || !dce_info) 1320 return BP_RESULT_BADBIOSTABLE; 1321 1322 memset(info, 0, sizeof(*info)); 1323 1324 header = GET_IMAGE(struct atom_common_table_header, 1325 DATA_TABLES(smu_info)); 1326 get_atom_data_table_revision(header, &revision); 1327 1328 if (revision.minor == 2) { 1329 /* Vega12 */ 1330 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1331 DATA_TABLES(smu_info)); 1332 1333 if (!smu_info_v3_2) 1334 return BP_RESULT_BADBIOSTABLE; 1335 1336 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1337 } else if (revision.minor == 3) { 1338 /* Vega20 */ 1339 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1340 DATA_TABLES(smu_info)); 1341 1342 if (!smu_info_v3_3) 1343 return BP_RESULT_BADBIOSTABLE; 1344 1345 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1346 } 1347 1348 // We need to convert from 10KHz units into KHz units. 1349 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1350 1351 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1352 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1353 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1354 if (info->pll_info.crystal_frequency == 0) { 1355 if (revision.minor == 2) 1356 info->pll_info.crystal_frequency = 27000; 1357 else if (revision.minor == 3) 1358 info->pll_info.crystal_frequency = 100000; 1359 } 1360 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1361 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1362 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1363 1364 /* Get GPU PLL VCO Clock */ 1365 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1366 if (revision.minor == 2) 1367 info->smu_gpu_pll_output_freq = 1368 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1369 else if (revision.minor == 3) 1370 info->smu_gpu_pll_output_freq = 1371 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1372 } 1373 1374 if (firmware_info->board_i2c_feature_id == 0x2) { 1375 info->oem_i2c_present = true; 1376 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1377 } else { 1378 info->oem_i2c_present = false; 1379 } 1380 1381 return BP_RESULT_OK; 1382 } 1383 1384 static enum bp_result bios_parser_get_encoder_cap_info( 1385 struct dc_bios *dcb, 1386 struct graphics_object_id object_id, 1387 struct bp_encoder_cap_info *info) 1388 { 1389 struct bios_parser *bp = BP_FROM_DCB(dcb); 1390 struct atom_display_object_path_v2 *object; 1391 struct atom_encoder_caps_record *record = NULL; 1392 1393 if (!info) 1394 return BP_RESULT_BADINPUT; 1395 1396 object = get_bios_object(bp, object_id); 1397 1398 if (!object) 1399 return BP_RESULT_BADINPUT; 1400 1401 record = get_encoder_cap_record(bp, object); 1402 if (!record) 1403 return BP_RESULT_NORECORD; 1404 1405 info->DP_HBR2_CAP = (record->encodercaps & 1406 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1407 info->DP_HBR2_EN = (record->encodercaps & 1408 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1409 info->DP_HBR3_EN = (record->encodercaps & 1410 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1411 info->HDMI_6GB_EN = (record->encodercaps & 1412 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1413 info->DP_IS_USB_C = (record->encodercaps & 1414 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1415 1416 return BP_RESULT_OK; 1417 } 1418 1419 1420 static struct atom_encoder_caps_record *get_encoder_cap_record( 1421 struct bios_parser *bp, 1422 struct atom_display_object_path_v2 *object) 1423 { 1424 struct atom_common_record_header *header; 1425 uint32_t offset; 1426 1427 if (!object) { 1428 BREAK_TO_DEBUGGER(); /* Invalid object */ 1429 return NULL; 1430 } 1431 1432 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1433 1434 for (;;) { 1435 header = GET_IMAGE(struct atom_common_record_header, offset); 1436 1437 if (!header) 1438 return NULL; 1439 1440 offset += header->record_size; 1441 1442 if (header->record_type == LAST_RECORD_TYPE || 1443 !header->record_size) 1444 break; 1445 1446 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1447 continue; 1448 1449 if (sizeof(struct atom_encoder_caps_record) <= 1450 header->record_size) 1451 return (struct atom_encoder_caps_record *)header; 1452 } 1453 1454 return NULL; 1455 } 1456 1457 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record( 1458 struct bios_parser *bp, 1459 struct atom_display_object_path_v2 *object) 1460 { 1461 struct atom_common_record_header *header; 1462 uint32_t offset; 1463 1464 if (!object) { 1465 BREAK_TO_DEBUGGER(); /* Invalid object */ 1466 return NULL; 1467 } 1468 1469 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 1470 1471 for (;;) { 1472 header = GET_IMAGE(struct atom_common_record_header, offset); 1473 1474 if (!header) 1475 return NULL; 1476 1477 offset += header->record_size; 1478 1479 if (header->record_type == LAST_RECORD_TYPE || 1480 !header->record_size) 1481 break; 1482 1483 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE) 1484 continue; 1485 1486 if (sizeof(struct atom_disp_connector_caps_record) <= 1487 header->record_size) 1488 return (struct atom_disp_connector_caps_record *)header; 1489 } 1490 1491 return NULL; 1492 } 1493 1494 static enum bp_result bios_parser_get_disp_connector_caps_info( 1495 struct dc_bios *dcb, 1496 struct graphics_object_id object_id, 1497 struct bp_disp_connector_caps_info *info) 1498 { 1499 struct bios_parser *bp = BP_FROM_DCB(dcb); 1500 struct atom_display_object_path_v2 *object; 1501 struct atom_disp_connector_caps_record *record = NULL; 1502 1503 if (!info) 1504 return BP_RESULT_BADINPUT; 1505 1506 object = get_bios_object(bp, object_id); 1507 1508 if (!object) 1509 return BP_RESULT_BADINPUT; 1510 1511 record = get_disp_connector_caps_record(bp, object); 1512 if (!record) 1513 return BP_RESULT_NORECORD; 1514 1515 info->INTERNAL_DISPLAY = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) 1516 ? 1 : 0; 1517 info->INTERNAL_DISPLAY_BL = (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) 1518 ? 1 : 0; 1519 1520 return BP_RESULT_OK; 1521 } 1522 1523 static enum bp_result get_vram_info_v23( 1524 struct bios_parser *bp, 1525 struct dc_vram_info *info) 1526 { 1527 struct atom_vram_info_header_v2_3 *info_v23; 1528 enum bp_result result = BP_RESULT_OK; 1529 1530 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1531 DATA_TABLES(vram_info)); 1532 1533 if (info_v23 == NULL) 1534 return BP_RESULT_BADBIOSTABLE; 1535 1536 info->num_chans = info_v23->vram_module[0].channel_num; 1537 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1538 1539 return result; 1540 } 1541 1542 static enum bp_result get_vram_info_v24( 1543 struct bios_parser *bp, 1544 struct dc_vram_info *info) 1545 { 1546 struct atom_vram_info_header_v2_4 *info_v24; 1547 enum bp_result result = BP_RESULT_OK; 1548 1549 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1550 DATA_TABLES(vram_info)); 1551 1552 if (info_v24 == NULL) 1553 return BP_RESULT_BADBIOSTABLE; 1554 1555 info->num_chans = info_v24->vram_module[0].channel_num; 1556 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1557 1558 return result; 1559 } 1560 1561 static enum bp_result get_vram_info_v25( 1562 struct bios_parser *bp, 1563 struct dc_vram_info *info) 1564 { 1565 struct atom_vram_info_header_v2_5 *info_v25; 1566 enum bp_result result = BP_RESULT_OK; 1567 1568 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1569 DATA_TABLES(vram_info)); 1570 1571 if (info_v25 == NULL) 1572 return BP_RESULT_BADBIOSTABLE; 1573 1574 info->num_chans = info_v25->vram_module[0].channel_num; 1575 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1576 1577 return result; 1578 } 1579 1580 /* 1581 * get_integrated_info_v11 1582 * 1583 * @brief 1584 * Get V8 integrated BIOS information 1585 * 1586 * @param 1587 * bios_parser *bp - [in]BIOS parser handler to get master data table 1588 * integrated_info *info - [out] store and output integrated info 1589 * 1590 * @return 1591 * enum bp_result - BP_RESULT_OK if information is available, 1592 * BP_RESULT_BADBIOSTABLE otherwise. 1593 */ 1594 static enum bp_result get_integrated_info_v11( 1595 struct bios_parser *bp, 1596 struct integrated_info *info) 1597 { 1598 struct atom_integrated_system_info_v1_11 *info_v11; 1599 uint32_t i; 1600 1601 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1602 DATA_TABLES(integratedsysteminfo)); 1603 1604 if (info_v11 == NULL) 1605 return BP_RESULT_BADBIOSTABLE; 1606 1607 info->gpu_cap_info = 1608 le32_to_cpu(info_v11->gpucapinfo); 1609 /* 1610 * system_config: Bit[0] = 0 : PCIE power gating disabled 1611 * = 1 : PCIE power gating enabled 1612 * Bit[1] = 0 : DDR-PLL shut down disabled 1613 * = 1 : DDR-PLL shut down enabled 1614 * Bit[2] = 0 : DDR-PLL power down disabled 1615 * = 1 : DDR-PLL power down enabled 1616 */ 1617 info->system_config = le32_to_cpu(info_v11->system_config); 1618 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1619 info->memory_type = info_v11->memorytype; 1620 info->ma_channel_number = info_v11->umachannelnumber; 1621 info->lvds_ss_percentage = 1622 le16_to_cpu(info_v11->lvds_ss_percentage); 1623 info->dp_ss_control = 1624 le16_to_cpu(info_v11->reserved1); 1625 info->lvds_sspread_rate_in_10hz = 1626 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1627 info->hdmi_ss_percentage = 1628 le16_to_cpu(info_v11->hdmi_ss_percentage); 1629 info->hdmi_sspread_rate_in_10hz = 1630 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1631 info->dvi_ss_percentage = 1632 le16_to_cpu(info_v11->dvi_ss_percentage); 1633 info->dvi_sspread_rate_in_10_hz = 1634 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1635 info->lvds_misc = info_v11->lvds_misc; 1636 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1637 info->ext_disp_conn_info.gu_id[i] = 1638 info_v11->extdispconninfo.guid[i]; 1639 } 1640 1641 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1642 info->ext_disp_conn_info.path[i].device_connector_id = 1643 object_id_from_bios_object_id( 1644 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1645 1646 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1647 object_id_from_bios_object_id( 1648 le16_to_cpu( 1649 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1650 1651 info->ext_disp_conn_info.path[i].device_tag = 1652 le16_to_cpu( 1653 info_v11->extdispconninfo.path[i].device_tag); 1654 info->ext_disp_conn_info.path[i].device_acpi_enum = 1655 le16_to_cpu( 1656 info_v11->extdispconninfo.path[i].device_acpi_enum); 1657 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1658 info_v11->extdispconninfo.path[i].auxddclut_index; 1659 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1660 info_v11->extdispconninfo.path[i].hpdlut_index; 1661 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1662 info_v11->extdispconninfo.path[i].channelmapping; 1663 info->ext_disp_conn_info.path[i].caps = 1664 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1665 } 1666 info->ext_disp_conn_info.checksum = 1667 info_v11->extdispconninfo.checksum; 1668 1669 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1670 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1671 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1672 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1673 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1674 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1675 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1676 } 1677 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1678 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1679 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1680 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1681 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1682 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1683 } 1684 1685 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1686 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1687 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1688 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1689 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1690 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1691 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1692 } 1693 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1694 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1695 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1696 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1697 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1698 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1699 } 1700 1701 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1702 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1703 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1704 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1705 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1706 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1707 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1708 } 1709 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1710 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1711 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1712 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1713 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1714 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1715 } 1716 1717 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1718 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1719 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1720 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1721 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1722 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1723 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1724 } 1725 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1726 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1727 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1728 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1729 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1730 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1731 } 1732 1733 1734 /** TODO - review **/ 1735 #if 0 1736 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1737 * 10; 1738 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1739 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1740 1741 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1742 /* Convert [10KHz] into [KHz] */ 1743 info->disp_clk_voltage[i].max_supported_clk = 1744 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1745 ulMaximumSupportedCLK) * 10; 1746 info->disp_clk_voltage[i].voltage_index = 1747 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1748 } 1749 1750 info->boot_up_req_display_vector = 1751 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1752 info->boot_up_nb_voltage = 1753 le16_to_cpu(info_v11->usBootUpNBVoltage); 1754 info->ext_disp_conn_info_offset = 1755 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1756 info->gmc_restore_reset_time = 1757 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1758 info->minimum_n_clk = 1759 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1760 for (i = 1; i < 4; ++i) 1761 info->minimum_n_clk = 1762 info->minimum_n_clk < 1763 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1764 info->minimum_n_clk : le32_to_cpu( 1765 info_v11->ulNbpStateNClkFreq[i]); 1766 1767 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1768 info->ddr_dll_power_up_time = 1769 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1770 info->ddr_pll_power_up_time = 1771 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1772 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1773 info->max_lvds_pclk_freq_in_single_link = 1774 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1775 info->max_lvds_pclk_freq_in_single_link = 1776 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1777 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1778 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1779 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1780 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1781 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1782 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1783 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1784 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1785 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1786 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1787 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1788 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1789 info->lvds_off_to_on_delay_in_4ms = 1790 info_v11->ucLVDSOffToOnDelay_in4Ms; 1791 info->lvds_bit_depth_control_val = 1792 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1793 1794 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1795 /* Convert [10KHz] into [KHz] */ 1796 info->avail_s_clk[i].supported_s_clk = 1797 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1798 * 10; 1799 info->avail_s_clk[i].voltage_index = 1800 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1801 info->avail_s_clk[i].voltage_id = 1802 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1803 } 1804 #endif /* TODO*/ 1805 1806 return BP_RESULT_OK; 1807 } 1808 1809 static enum bp_result get_integrated_info_v2_1( 1810 struct bios_parser *bp, 1811 struct integrated_info *info) 1812 { 1813 struct atom_integrated_system_info_v2_1 *info_v2_1; 1814 uint32_t i; 1815 1816 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 1817 DATA_TABLES(integratedsysteminfo)); 1818 1819 if (info_v2_1 == NULL) 1820 return BP_RESULT_BADBIOSTABLE; 1821 1822 info->gpu_cap_info = 1823 le32_to_cpu(info_v2_1->gpucapinfo); 1824 /* 1825 * system_config: Bit[0] = 0 : PCIE power gating disabled 1826 * = 1 : PCIE power gating enabled 1827 * Bit[1] = 0 : DDR-PLL shut down disabled 1828 * = 1 : DDR-PLL shut down enabled 1829 * Bit[2] = 0 : DDR-PLL power down disabled 1830 * = 1 : DDR-PLL power down enabled 1831 */ 1832 info->system_config = le32_to_cpu(info_v2_1->system_config); 1833 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 1834 info->memory_type = info_v2_1->memorytype; 1835 info->ma_channel_number = info_v2_1->umachannelnumber; 1836 info->dp_ss_control = 1837 le16_to_cpu(info_v2_1->reserved1); 1838 1839 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1840 info->ext_disp_conn_info.gu_id[i] = 1841 info_v2_1->extdispconninfo.guid[i]; 1842 } 1843 1844 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1845 info->ext_disp_conn_info.path[i].device_connector_id = 1846 object_id_from_bios_object_id( 1847 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 1848 1849 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1850 object_id_from_bios_object_id( 1851 le16_to_cpu( 1852 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 1853 1854 info->ext_disp_conn_info.path[i].device_tag = 1855 le16_to_cpu( 1856 info_v2_1->extdispconninfo.path[i].device_tag); 1857 info->ext_disp_conn_info.path[i].device_acpi_enum = 1858 le16_to_cpu( 1859 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 1860 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1861 info_v2_1->extdispconninfo.path[i].auxddclut_index; 1862 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1863 info_v2_1->extdispconninfo.path[i].hpdlut_index; 1864 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1865 info_v2_1->extdispconninfo.path[i].channelmapping; 1866 info->ext_disp_conn_info.path[i].caps = 1867 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 1868 } 1869 1870 info->ext_disp_conn_info.checksum = 1871 info_v2_1->extdispconninfo.checksum; 1872 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 1873 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 1874 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1875 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1876 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1877 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1878 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1879 } 1880 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 1881 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1882 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1883 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1884 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1885 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1886 } 1887 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 1888 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 1889 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1890 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1891 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1892 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1893 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1894 } 1895 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 1896 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1897 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1898 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1899 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1900 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1901 } 1902 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 1903 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 1904 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1905 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1906 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1907 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1908 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1909 } 1910 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 1911 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1912 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1913 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1914 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1915 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1916 } 1917 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 1918 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 1919 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1920 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1921 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1922 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1923 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1924 } 1925 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 1926 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1927 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1928 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1929 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1930 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1931 } 1932 1933 info->edp1_info.edp_backlight_pwm_hz = 1934 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 1935 info->edp1_info.edp_ss_percentage = 1936 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 1937 info->edp1_info.edp_ss_rate_10hz = 1938 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 1939 info->edp1_info.edp_pwr_on_off_delay = 1940 info_v2_1->edp1_info.edp_pwr_on_off_delay; 1941 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 1942 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 1943 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 1944 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 1945 info->edp1_info.edp_panel_bpc = 1946 info_v2_1->edp1_info.edp_panel_bpc; 1947 info->edp1_info.edp_bootup_bl_level = 1948 1949 info->edp2_info.edp_backlight_pwm_hz = 1950 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 1951 info->edp2_info.edp_ss_percentage = 1952 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 1953 info->edp2_info.edp_ss_rate_10hz = 1954 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 1955 info->edp2_info.edp_pwr_on_off_delay = 1956 info_v2_1->edp2_info.edp_pwr_on_off_delay; 1957 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 1958 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 1959 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 1960 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 1961 info->edp2_info.edp_panel_bpc = 1962 info_v2_1->edp2_info.edp_panel_bpc; 1963 info->edp2_info.edp_bootup_bl_level = 1964 info_v2_1->edp2_info.edp_bootup_bl_level; 1965 1966 return BP_RESULT_OK; 1967 } 1968 1969 /* 1970 * construct_integrated_info 1971 * 1972 * @brief 1973 * Get integrated BIOS information based on table revision 1974 * 1975 * @param 1976 * bios_parser *bp - [in]BIOS parser handler to get master data table 1977 * integrated_info *info - [out] store and output integrated info 1978 * 1979 * @return 1980 * enum bp_result - BP_RESULT_OK if information is available, 1981 * BP_RESULT_BADBIOSTABLE otherwise. 1982 */ 1983 static enum bp_result construct_integrated_info( 1984 struct bios_parser *bp, 1985 struct integrated_info *info) 1986 { 1987 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1988 1989 struct atom_common_table_header *header; 1990 struct atom_data_revision revision; 1991 uint32_t i; 1992 uint32_t j; 1993 1994 if (info && DATA_TABLES(integratedsysteminfo)) { 1995 header = GET_IMAGE(struct atom_common_table_header, 1996 DATA_TABLES(integratedsysteminfo)); 1997 1998 get_atom_data_table_revision(header, &revision); 1999 2000 switch (revision.major) { 2001 case 1: 2002 switch (revision.minor) { 2003 case 11: 2004 case 12: 2005 result = get_integrated_info_v11(bp, info); 2006 break; 2007 default: 2008 return result; 2009 } 2010 break; 2011 case 2: 2012 switch (revision.minor) { 2013 case 1: 2014 result = get_integrated_info_v2_1(bp, info); 2015 break; 2016 default: 2017 return result; 2018 } 2019 break; 2020 default: 2021 return result; 2022 } 2023 } 2024 2025 if (result != BP_RESULT_OK) 2026 return result; 2027 2028 /* Sort voltage table from low to high*/ 2029 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2030 for (j = i; j > 0; --j) { 2031 if (info->disp_clk_voltage[j].max_supported_clk < 2032 info->disp_clk_voltage[j-1].max_supported_clk 2033 ) { 2034 /* swap j and j - 1*/ 2035 swap(info->disp_clk_voltage[j - 1], 2036 info->disp_clk_voltage[j]); 2037 } 2038 } 2039 } 2040 2041 return result; 2042 } 2043 2044 static enum bp_result bios_parser_get_vram_info( 2045 struct dc_bios *dcb, 2046 struct dc_vram_info *info) 2047 { 2048 struct bios_parser *bp = BP_FROM_DCB(dcb); 2049 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2050 struct atom_common_table_header *header; 2051 struct atom_data_revision revision; 2052 2053 if (info && DATA_TABLES(vram_info)) { 2054 header = GET_IMAGE(struct atom_common_table_header, 2055 DATA_TABLES(vram_info)); 2056 2057 get_atom_data_table_revision(header, &revision); 2058 2059 switch (revision.major) { 2060 case 2: 2061 switch (revision.minor) { 2062 case 3: 2063 result = get_vram_info_v23(bp, info); 2064 break; 2065 case 4: 2066 result = get_vram_info_v24(bp, info); 2067 break; 2068 case 5: 2069 result = get_vram_info_v25(bp, info); 2070 break; 2071 default: 2072 break; 2073 } 2074 break; 2075 2076 default: 2077 return result; 2078 } 2079 2080 } 2081 return result; 2082 } 2083 2084 static struct integrated_info *bios_parser_create_integrated_info( 2085 struct dc_bios *dcb) 2086 { 2087 struct bios_parser *bp = BP_FROM_DCB(dcb); 2088 struct integrated_info *info = NULL; 2089 2090 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2091 2092 if (info == NULL) { 2093 ASSERT_CRITICAL(0); 2094 return NULL; 2095 } 2096 2097 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2098 return info; 2099 2100 kfree(info); 2101 2102 return NULL; 2103 } 2104 2105 static enum bp_result update_slot_layout_info( 2106 struct dc_bios *dcb, 2107 unsigned int i, 2108 struct slot_layout_info *slot_layout_info) 2109 { 2110 unsigned int record_offset; 2111 unsigned int j; 2112 struct atom_display_object_path_v2 *object; 2113 struct atom_bracket_layout_record *record; 2114 struct atom_common_record_header *record_header; 2115 enum bp_result result; 2116 struct bios_parser *bp; 2117 struct object_info_table *tbl; 2118 struct display_object_info_table_v1_4 *v1_4; 2119 2120 record = NULL; 2121 record_header = NULL; 2122 result = BP_RESULT_NORECORD; 2123 2124 bp = BP_FROM_DCB(dcb); 2125 tbl = &bp->object_info_tbl; 2126 v1_4 = tbl->v1_4; 2127 2128 object = &v1_4->display_path[i]; 2129 record_offset = (unsigned int) 2130 (object->disp_recordoffset) + 2131 (unsigned int)(bp->object_info_tbl_offset); 2132 2133 for (;;) { 2134 2135 record_header = (struct atom_common_record_header *) 2136 GET_IMAGE(struct atom_common_record_header, 2137 record_offset); 2138 if (record_header == NULL) { 2139 result = BP_RESULT_BADBIOSTABLE; 2140 break; 2141 } 2142 2143 /* the end of the list */ 2144 if (record_header->record_type == 0xff || 2145 record_header->record_size == 0) { 2146 break; 2147 } 2148 2149 if (record_header->record_type == 2150 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2151 sizeof(struct atom_bracket_layout_record) 2152 <= record_header->record_size) { 2153 record = (struct atom_bracket_layout_record *) 2154 (record_header); 2155 result = BP_RESULT_OK; 2156 break; 2157 } 2158 2159 record_offset += record_header->record_size; 2160 } 2161 2162 /* return if the record not found */ 2163 if (result != BP_RESULT_OK) 2164 return result; 2165 2166 /* get slot sizes */ 2167 slot_layout_info->length = record->bracketlen; 2168 slot_layout_info->width = record->bracketwidth; 2169 2170 /* get info for each connector in the slot */ 2171 slot_layout_info->num_of_connectors = record->conn_num; 2172 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2173 slot_layout_info->connectors[j].connector_type = 2174 (enum connector_layout_type) 2175 (record->conn_info[j].connector_type); 2176 switch (record->conn_info[j].connector_type) { 2177 case CONNECTOR_TYPE_DVI_D: 2178 slot_layout_info->connectors[j].connector_type = 2179 CONNECTOR_LAYOUT_TYPE_DVI_D; 2180 slot_layout_info->connectors[j].length = 2181 CONNECTOR_SIZE_DVI; 2182 break; 2183 2184 case CONNECTOR_TYPE_HDMI: 2185 slot_layout_info->connectors[j].connector_type = 2186 CONNECTOR_LAYOUT_TYPE_HDMI; 2187 slot_layout_info->connectors[j].length = 2188 CONNECTOR_SIZE_HDMI; 2189 break; 2190 2191 case CONNECTOR_TYPE_DISPLAY_PORT: 2192 slot_layout_info->connectors[j].connector_type = 2193 CONNECTOR_LAYOUT_TYPE_DP; 2194 slot_layout_info->connectors[j].length = 2195 CONNECTOR_SIZE_DP; 2196 break; 2197 2198 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2199 slot_layout_info->connectors[j].connector_type = 2200 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2201 slot_layout_info->connectors[j].length = 2202 CONNECTOR_SIZE_MINI_DP; 2203 break; 2204 2205 default: 2206 slot_layout_info->connectors[j].connector_type = 2207 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2208 slot_layout_info->connectors[j].length = 2209 CONNECTOR_SIZE_UNKNOWN; 2210 } 2211 2212 slot_layout_info->connectors[j].position = 2213 record->conn_info[j].position; 2214 slot_layout_info->connectors[j].connector_id = 2215 object_id_from_bios_object_id( 2216 record->conn_info[j].connectorobjid); 2217 } 2218 return result; 2219 } 2220 2221 2222 static enum bp_result get_bracket_layout_record( 2223 struct dc_bios *dcb, 2224 unsigned int bracket_layout_id, 2225 struct slot_layout_info *slot_layout_info) 2226 { 2227 unsigned int i; 2228 struct bios_parser *bp = BP_FROM_DCB(dcb); 2229 enum bp_result result; 2230 struct object_info_table *tbl; 2231 struct display_object_info_table_v1_4 *v1_4; 2232 2233 if (slot_layout_info == NULL) { 2234 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2235 return BP_RESULT_BADINPUT; 2236 } 2237 tbl = &bp->object_info_tbl; 2238 v1_4 = tbl->v1_4; 2239 2240 result = BP_RESULT_NORECORD; 2241 for (i = 0; i < v1_4->number_of_path; ++i) { 2242 2243 if (bracket_layout_id == 2244 v1_4->display_path[i].display_objid) { 2245 result = update_slot_layout_info(dcb, i, 2246 slot_layout_info); 2247 break; 2248 } 2249 } 2250 return result; 2251 } 2252 2253 static enum bp_result bios_get_board_layout_info( 2254 struct dc_bios *dcb, 2255 struct board_layout_info *board_layout_info) 2256 { 2257 unsigned int i; 2258 enum bp_result record_result; 2259 2260 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2261 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2262 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2263 0, 0 2264 }; 2265 2266 if (board_layout_info == NULL) { 2267 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2268 return BP_RESULT_BADINPUT; 2269 } 2270 2271 board_layout_info->num_of_slots = 0; 2272 2273 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2274 record_result = get_bracket_layout_record(dcb, 2275 slot_index_to_vbios_id[i], 2276 &board_layout_info->slots[i]); 2277 2278 if (record_result == BP_RESULT_NORECORD && i > 0) 2279 break; /* no more slots present in bios */ 2280 else if (record_result != BP_RESULT_OK) 2281 return record_result; /* fail */ 2282 2283 ++board_layout_info->num_of_slots; 2284 } 2285 2286 /* all data is valid */ 2287 board_layout_info->is_number_of_slots_valid = 1; 2288 board_layout_info->is_slots_size_valid = 1; 2289 board_layout_info->is_connector_offsets_valid = 1; 2290 board_layout_info->is_connector_lengths_valid = 1; 2291 2292 return BP_RESULT_OK; 2293 } 2294 2295 2296 static uint16_t bios_parser_pack_data_tables( 2297 struct dc_bios *dcb, 2298 void *dst) 2299 { 2300 #ifdef PACK_BIOS_DATA 2301 struct bios_parser *bp = BP_FROM_DCB(dcb); 2302 struct atom_rom_header_v2_2 *rom_header = NULL; 2303 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2304 struct atom_common_table_header *data_tbl_header = NULL; 2305 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2306 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2307 struct atom_data_revision tbl_rev = {0}; 2308 uint16_t *rom_header_offset = NULL; 2309 const uint8_t *bios = bp->base.bios; 2310 uint8_t *bios_dst = (uint8_t *)dst; 2311 uint16_t packed_rom_header_offset; 2312 uint16_t packed_masterdatatable_offset; 2313 uint16_t packed_data_tbl_offset; 2314 uint16_t data_tbl_offset; 2315 unsigned int i; 2316 2317 rom_header_offset = 2318 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2319 2320 if (!rom_header_offset) 2321 return 0; 2322 2323 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2324 2325 if (!rom_header) 2326 return 0; 2327 2328 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2329 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2330 return 0; 2331 2332 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2333 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2334 return 0; 2335 2336 packed_rom_header_offset = 2337 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2338 2339 packed_masterdatatable_offset = 2340 packed_rom_header_offset + rom_header->table_header.structuresize; 2341 2342 packed_data_tbl_offset = 2343 packed_masterdatatable_offset + 2344 bp->master_data_tbl->table_header.structuresize; 2345 2346 packed_rom_header = 2347 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2348 2349 packed_master_data_tbl = 2350 (struct atom_master_data_table_v2_1 *)(bios_dst + 2351 packed_masterdatatable_offset); 2352 2353 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2354 2355 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2356 packed_rom_header_offset; 2357 2358 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2359 rom_header->table_header.structuresize); 2360 2361 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2362 2363 memcpy(&packed_master_data_tbl->table_header, 2364 &bp->master_data_tbl->table_header, 2365 sizeof(bp->master_data_tbl->table_header)); 2366 2367 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2368 2369 /* Each data table offset in data table list is 2 bytes, 2370 * we can use that to iterate through listOfdatatables 2371 * without knowing the name of each member. 2372 */ 2373 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2374 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2375 2376 if (data_tbl_offset) { 2377 data_tbl_header = 2378 (struct atom_common_table_header *)(bios + data_tbl_offset); 2379 2380 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2381 data_tbl_header->structuresize); 2382 2383 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2384 packed_data_tbl_offset; 2385 2386 packed_data_tbl_offset += data_tbl_header->structuresize; 2387 } else { 2388 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2389 } 2390 } 2391 return packed_data_tbl_offset; 2392 #endif 2393 // TODO: There is data bytes alignment issue, disable it for now. 2394 return 0; 2395 } 2396 2397 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2398 struct bios_parser *bp, 2399 uint32_t rev_major, 2400 uint32_t rev_minor, 2401 uint16_t *dc_golden_table_ver) 2402 { 2403 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2404 uint32_t dc_golden_offset = 0; 2405 *dc_golden_table_ver = 0; 2406 2407 if (!DATA_TABLES(dce_info)) 2408 return NULL; 2409 2410 /* ver.4.4 or higher */ 2411 switch (rev_major) { 2412 case 4: 2413 switch (rev_minor) { 2414 case 4: 2415 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2416 DATA_TABLES(dce_info)); 2417 if (!disp_cntl_tbl_4_4) 2418 return NULL; 2419 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2420 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2421 break; 2422 } 2423 break; 2424 } 2425 2426 if (!dc_golden_offset) 2427 return NULL; 2428 2429 if (*dc_golden_table_ver != 1) 2430 return NULL; 2431 2432 return GET_IMAGE(struct atom_dc_golden_table_v1, 2433 dc_golden_offset); 2434 } 2435 2436 static enum bp_result bios_get_atom_dc_golden_table( 2437 struct dc_bios *dcb) 2438 { 2439 struct bios_parser *bp = BP_FROM_DCB(dcb); 2440 enum bp_result result = BP_RESULT_OK; 2441 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2442 struct atom_common_table_header *header; 2443 struct atom_data_revision tbl_revision; 2444 uint16_t dc_golden_table_ver = 0; 2445 2446 header = GET_IMAGE(struct atom_common_table_header, 2447 DATA_TABLES(dce_info)); 2448 if (!header) 2449 return BP_RESULT_UNSUPPORTED; 2450 2451 get_atom_data_table_revision(header, &tbl_revision); 2452 2453 atom_dc_golden_table = bios_get_golden_table(bp, 2454 tbl_revision.major, 2455 tbl_revision.minor, 2456 &dc_golden_table_ver); 2457 2458 if (!atom_dc_golden_table) 2459 return BP_RESULT_UNSUPPORTED; 2460 2461 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2462 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2463 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2464 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2465 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2466 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2467 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2468 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2469 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2470 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2471 2472 return result; 2473 } 2474 2475 2476 static const struct dc_vbios_funcs vbios_funcs = { 2477 .get_connectors_number = bios_parser_get_connectors_number, 2478 2479 .get_connector_id = bios_parser_get_connector_id, 2480 2481 .get_src_obj = bios_parser_get_src_obj, 2482 2483 .get_i2c_info = bios_parser_get_i2c_info, 2484 2485 .get_hpd_info = bios_parser_get_hpd_info, 2486 2487 .get_device_tag = bios_parser_get_device_tag, 2488 2489 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2490 2491 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2492 2493 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2494 2495 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2496 2497 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2498 2499 .is_device_id_supported = bios_parser_is_device_id_supported, 2500 2501 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2502 2503 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2504 2505 2506 /* COMMANDS */ 2507 .encoder_control = bios_parser_encoder_control, 2508 2509 .transmitter_control = bios_parser_transmitter_control, 2510 2511 .enable_crtc = bios_parser_enable_crtc, 2512 2513 .set_pixel_clock = bios_parser_set_pixel_clock, 2514 2515 .set_dce_clock = bios_parser_set_dce_clock, 2516 2517 .program_crtc_timing = bios_parser_program_crtc_timing, 2518 2519 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2520 2521 .bios_parser_destroy = firmware_parser_destroy, 2522 2523 .get_board_layout_info = bios_get_board_layout_info, 2524 .pack_data_tables = bios_parser_pack_data_tables, 2525 2526 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2527 2528 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2529 2530 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2531 2532 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info, 2533 }; 2534 2535 static bool bios_parser2_construct( 2536 struct bios_parser *bp, 2537 struct bp_init_data *init, 2538 enum dce_version dce_version) 2539 { 2540 uint16_t *rom_header_offset = NULL; 2541 struct atom_rom_header_v2_2 *rom_header = NULL; 2542 struct display_object_info_table_v1_4 *object_info_tbl; 2543 struct atom_data_revision tbl_rev = {0}; 2544 2545 if (!init) 2546 return false; 2547 2548 if (!init->bios) 2549 return false; 2550 2551 bp->base.funcs = &vbios_funcs; 2552 bp->base.bios = init->bios; 2553 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2554 2555 bp->base.ctx = init->ctx; 2556 2557 bp->base.bios_local_image = NULL; 2558 2559 rom_header_offset = 2560 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2561 2562 if (!rom_header_offset) 2563 return false; 2564 2565 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2566 2567 if (!rom_header) 2568 return false; 2569 2570 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2571 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2572 return false; 2573 2574 bp->master_data_tbl = 2575 GET_IMAGE(struct atom_master_data_table_v2_1, 2576 rom_header->masterdatatable_offset); 2577 2578 if (!bp->master_data_tbl) 2579 return false; 2580 2581 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2582 2583 if (!bp->object_info_tbl_offset) 2584 return false; 2585 2586 object_info_tbl = 2587 GET_IMAGE(struct display_object_info_table_v1_4, 2588 bp->object_info_tbl_offset); 2589 2590 if (!object_info_tbl) 2591 return false; 2592 2593 get_atom_data_table_revision(&object_info_tbl->table_header, 2594 &bp->object_info_tbl.revision); 2595 2596 if (bp->object_info_tbl.revision.major == 1 2597 && bp->object_info_tbl.revision.minor >= 4) { 2598 struct display_object_info_table_v1_4 *tbl_v1_4; 2599 2600 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2601 bp->object_info_tbl_offset); 2602 if (!tbl_v1_4) 2603 return false; 2604 2605 bp->object_info_tbl.v1_4 = tbl_v1_4; 2606 } else 2607 return false; 2608 2609 dal_firmware_parser_init_cmd_tbl(bp); 2610 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2611 2612 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2613 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2614 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2615 2616 return true; 2617 } 2618 2619 struct dc_bios *firmware_parser_create( 2620 struct bp_init_data *init, 2621 enum dce_version dce_version) 2622 { 2623 struct bios_parser *bp = NULL; 2624 2625 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2626 if (!bp) 2627 return NULL; 2628 2629 if (bios_parser2_construct(bp, init, dce_version)) 2630 return &bp->base; 2631 2632 kfree(bp); 2633 return NULL; 2634 } 2635 2636 2637