1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "ObjectID.h" 31 #include "atomfirmware.h" 32 33 #include "dc_bios_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/i2caux_interface.h" 37 #include "include/logger_interface.h" 38 39 #include "command_table2.h" 40 41 #include "bios_parser_helper.h" 42 #include "command_table_helper2.h" 43 #include "bios_parser2.h" 44 #include "bios_parser_types_internal2.h" 45 #include "bios_parser_interface.h" 46 47 #include "bios_parser_common.h" 48 49 /* Temporarily add in defines until ObjectID.h patch is updated in a few days */ 50 #ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT 51 #define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05 52 #endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */ 53 54 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 55 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \ 56 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 57 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 58 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 59 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */ 60 61 #ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 62 #define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \ 63 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\ 64 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 65 GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT) 66 #endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */ 67 68 #define DC_LOGGER \ 69 bp->base.ctx->logger 70 71 #define LAST_RECORD_TYPE 0xff 72 #define SMU9_SYSPLL0_ID 0 73 74 struct i2c_id_config_access { 75 uint8_t bfI2C_LineMux:4; 76 uint8_t bfHW_EngineID:3; 77 uint8_t bfHW_Capable:1; 78 uint8_t ucAccess; 79 }; 80 81 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 82 struct atom_i2c_record *record, 83 struct graphics_object_i2c_info *info); 84 85 static enum bp_result bios_parser_get_firmware_info( 86 struct dc_bios *dcb, 87 struct dc_firmware_info *info); 88 89 static enum bp_result bios_parser_get_encoder_cap_info( 90 struct dc_bios *dcb, 91 struct graphics_object_id object_id, 92 struct bp_encoder_cap_info *info); 93 94 static enum bp_result get_firmware_info_v3_1( 95 struct bios_parser *bp, 96 struct dc_firmware_info *info); 97 98 static enum bp_result get_firmware_info_v3_2( 99 struct bios_parser *bp, 100 struct dc_firmware_info *info); 101 102 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, 103 struct atom_display_object_path_v2 *object); 104 105 static struct atom_encoder_caps_record *get_encoder_cap_record( 106 struct bios_parser *bp, 107 struct atom_display_object_path_v2 *object); 108 109 #define BIOS_IMAGE_SIZE_OFFSET 2 110 #define BIOS_IMAGE_SIZE_UNIT 512 111 112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table) 113 114 static void bios_parser2_destruct(struct bios_parser *bp) 115 { 116 kfree(bp->base.bios_local_image); 117 kfree(bp->base.integrated_info); 118 } 119 120 static void firmware_parser_destroy(struct dc_bios **dcb) 121 { 122 struct bios_parser *bp = BP_FROM_DCB(*dcb); 123 124 if (!bp) { 125 BREAK_TO_DEBUGGER(); 126 return; 127 } 128 129 bios_parser2_destruct(bp); 130 131 kfree(bp); 132 *dcb = NULL; 133 } 134 135 static void get_atom_data_table_revision( 136 struct atom_common_table_header *atom_data_tbl, 137 struct atom_data_revision *tbl_revision) 138 { 139 if (!tbl_revision) 140 return; 141 142 /* initialize the revision to 0 which is invalid revision */ 143 tbl_revision->major = 0; 144 tbl_revision->minor = 0; 145 146 if (!atom_data_tbl) 147 return; 148 149 tbl_revision->major = 150 (uint32_t) atom_data_tbl->format_revision & 0x3f; 151 tbl_revision->minor = 152 (uint32_t) atom_data_tbl->content_revision & 0x3f; 153 } 154 155 /* BIOS oject table displaypath is per connector. 156 * There is extra path not for connector. BIOS fill its encoderid as 0 157 */ 158 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 159 { 160 struct bios_parser *bp = BP_FROM_DCB(dcb); 161 unsigned int count = 0; 162 unsigned int i; 163 164 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 165 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0) 166 count++; 167 } 168 return count; 169 } 170 171 static struct graphics_object_id bios_parser_get_connector_id( 172 struct dc_bios *dcb, 173 uint8_t i) 174 { 175 struct bios_parser *bp = BP_FROM_DCB(dcb); 176 struct graphics_object_id object_id = dal_graphics_object_id_init( 177 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 178 struct object_info_table *tbl = &bp->object_info_tbl; 179 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4; 180 181 if (v1_4->number_of_path > i) { 182 /* If display_objid is generic object id, the encoderObj 183 * /extencoderobjId should be 0 184 */ 185 if (v1_4->display_path[i].encoderobjid != 0 && 186 v1_4->display_path[i].display_objid != 0) 187 object_id = object_id_from_bios_object_id( 188 v1_4->display_path[i].display_objid); 189 } 190 191 return object_id; 192 } 193 194 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 195 struct graphics_object_id object_id, uint32_t index, 196 struct graphics_object_id *src_object_id) 197 { 198 struct bios_parser *bp = BP_FROM_DCB(dcb); 199 unsigned int i; 200 enum bp_result bp_result = BP_RESULT_BADINPUT; 201 struct graphics_object_id obj_id = {0}; 202 struct object_info_table *tbl = &bp->object_info_tbl; 203 204 if (!src_object_id) 205 return bp_result; 206 207 switch (object_id.type) { 208 /* Encoder's Source is GPU. BIOS does not provide GPU, since all 209 * displaypaths point to same GPU (0x1100). Hardcode GPU object type 210 */ 211 case OBJECT_TYPE_ENCODER: 212 /* TODO: since num of src must be less than 2. 213 * If found in for loop, should break. 214 * DAL2 implementation may be changed too 215 */ 216 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 217 obj_id = object_id_from_bios_object_id( 218 tbl->v1_4->display_path[i].encoderobjid); 219 if (object_id.type == obj_id.type && 220 object_id.id == obj_id.id && 221 object_id.enum_id == 222 obj_id.enum_id) { 223 *src_object_id = 224 object_id_from_bios_object_id(0x1100); 225 /* break; */ 226 } 227 } 228 bp_result = BP_RESULT_OK; 229 break; 230 case OBJECT_TYPE_CONNECTOR: 231 for (i = 0; i < tbl->v1_4->number_of_path; i++) { 232 obj_id = object_id_from_bios_object_id( 233 tbl->v1_4->display_path[i].display_objid); 234 235 if (object_id.type == obj_id.type && 236 object_id.id == obj_id.id && 237 object_id.enum_id == obj_id.enum_id) { 238 *src_object_id = 239 object_id_from_bios_object_id( 240 tbl->v1_4->display_path[i].encoderobjid); 241 /* break; */ 242 } 243 } 244 bp_result = BP_RESULT_OK; 245 break; 246 default: 247 break; 248 } 249 250 return bp_result; 251 } 252 253 /* from graphics_object_id, find display path which includes the object_id */ 254 static struct atom_display_object_path_v2 *get_bios_object( 255 struct bios_parser *bp, 256 struct graphics_object_id id) 257 { 258 unsigned int i; 259 struct graphics_object_id obj_id = {0}; 260 261 switch (id.type) { 262 case OBJECT_TYPE_ENCODER: 263 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 264 obj_id = object_id_from_bios_object_id( 265 bp->object_info_tbl.v1_4->display_path[i].encoderobjid); 266 if (id.type == obj_id.type && id.id == obj_id.id 267 && id.enum_id == obj_id.enum_id) 268 return &bp->object_info_tbl.v1_4->display_path[i]; 269 } 270 fallthrough; 271 case OBJECT_TYPE_CONNECTOR: 272 case OBJECT_TYPE_GENERIC: 273 /* Both Generic and Connector Object ID 274 * will be stored on display_objid 275 */ 276 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) { 277 obj_id = object_id_from_bios_object_id( 278 bp->object_info_tbl.v1_4->display_path[i].display_objid); 279 if (id.type == obj_id.type && id.id == obj_id.id 280 && id.enum_id == obj_id.enum_id) 281 return &bp->object_info_tbl.v1_4->display_path[i]; 282 } 283 fallthrough; 284 default: 285 return NULL; 286 } 287 } 288 289 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 290 struct graphics_object_id id, 291 struct graphics_object_i2c_info *info) 292 { 293 uint32_t offset; 294 struct atom_display_object_path_v2 *object; 295 struct atom_common_record_header *header; 296 struct atom_i2c_record *record; 297 struct atom_i2c_record dummy_record = {0}; 298 struct bios_parser *bp = BP_FROM_DCB(dcb); 299 300 if (!info) 301 return BP_RESULT_BADINPUT; 302 303 if (id.type == OBJECT_TYPE_GENERIC) { 304 dummy_record.i2c_id = id.id; 305 306 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK) 307 return BP_RESULT_OK; 308 else 309 return BP_RESULT_NORECORD; 310 } 311 312 object = get_bios_object(bp, id); 313 314 if (!object) 315 return BP_RESULT_BADINPUT; 316 317 offset = object->disp_recordoffset + bp->object_info_tbl_offset; 318 319 for (;;) { 320 header = GET_IMAGE(struct atom_common_record_header, offset); 321 322 if (!header) 323 return BP_RESULT_BADBIOSTABLE; 324 325 if (header->record_type == LAST_RECORD_TYPE || 326 !header->record_size) 327 break; 328 329 if (header->record_type == ATOM_I2C_RECORD_TYPE 330 && sizeof(struct atom_i2c_record) <= 331 header->record_size) { 332 /* get the I2C info */ 333 record = (struct atom_i2c_record *) header; 334 335 if (get_gpio_i2c_info(bp, record, info) == 336 BP_RESULT_OK) 337 return BP_RESULT_OK; 338 } 339 340 offset += header->record_size; 341 } 342 343 return BP_RESULT_NORECORD; 344 } 345 346 static enum bp_result get_gpio_i2c_info( 347 struct bios_parser *bp, 348 struct atom_i2c_record *record, 349 struct graphics_object_i2c_info *info) 350 { 351 struct atom_gpio_pin_lut_v2_1 *header; 352 uint32_t count = 0; 353 unsigned int table_index = 0; 354 bool find_valid = false; 355 356 if (!info) 357 return BP_RESULT_BADINPUT; 358 359 /* get the GPIO_I2C info */ 360 if (!DATA_TABLES(gpio_pin_lut)) 361 return BP_RESULT_BADBIOSTABLE; 362 363 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 364 DATA_TABLES(gpio_pin_lut)); 365 if (!header) 366 return BP_RESULT_BADBIOSTABLE; 367 368 if (sizeof(struct atom_common_table_header) + 369 sizeof(struct atom_gpio_pin_assignment) > 370 le16_to_cpu(header->table_header.structuresize)) 371 return BP_RESULT_BADBIOSTABLE; 372 373 /* TODO: is version change? */ 374 if (header->table_header.content_revision != 1) 375 return BP_RESULT_UNSUPPORTED; 376 377 /* get data count */ 378 count = (le16_to_cpu(header->table_header.structuresize) 379 - sizeof(struct atom_common_table_header)) 380 / sizeof(struct atom_gpio_pin_assignment); 381 382 for (table_index = 0; table_index < count; table_index++) { 383 if (((record->i2c_id & I2C_HW_CAP) == ( 384 header->gpio_pin[table_index].gpio_id & 385 I2C_HW_CAP)) && 386 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == 387 (header->gpio_pin[table_index].gpio_id & 388 I2C_HW_ENGINE_ID_MASK)) && 389 ((record->i2c_id & I2C_HW_LANE_MUX) == 390 (header->gpio_pin[table_index].gpio_id & 391 I2C_HW_LANE_MUX))) { 392 /* still valid */ 393 find_valid = true; 394 break; 395 } 396 } 397 398 /* If we don't find the entry that we are looking for then 399 * we will return BP_Result_BadBiosTable. 400 */ 401 if (find_valid == false) 402 return BP_RESULT_BADBIOSTABLE; 403 404 /* get the GPIO_I2C_INFO */ 405 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false; 406 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX; 407 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4; 408 info->i2c_slave_address = record->i2c_slave_addr; 409 410 /* TODO: check how to get register offset for en, Y, etc. */ 411 info->gpio_info.clk_a_register_index = 412 le16_to_cpu( 413 header->gpio_pin[table_index].data_a_reg_index); 414 info->gpio_info.clk_a_shift = 415 header->gpio_pin[table_index].gpio_bitshift; 416 417 return BP_RESULT_OK; 418 } 419 420 static enum bp_result bios_parser_get_hpd_info( 421 struct dc_bios *dcb, 422 struct graphics_object_id id, 423 struct graphics_object_hpd_info *info) 424 { 425 struct bios_parser *bp = BP_FROM_DCB(dcb); 426 struct atom_display_object_path_v2 *object; 427 struct atom_hpd_int_record *record = NULL; 428 429 if (!info) 430 return BP_RESULT_BADINPUT; 431 432 object = get_bios_object(bp, id); 433 434 if (!object) 435 return BP_RESULT_BADINPUT; 436 437 record = get_hpd_record(bp, object); 438 439 if (record != NULL) { 440 info->hpd_int_gpio_uid = record->pin_id; 441 info->hpd_active = record->plugin_pin_state; 442 return BP_RESULT_OK; 443 } 444 445 return BP_RESULT_NORECORD; 446 } 447 448 static struct atom_hpd_int_record *get_hpd_record( 449 struct bios_parser *bp, 450 struct atom_display_object_path_v2 *object) 451 { 452 struct atom_common_record_header *header; 453 uint32_t offset; 454 455 if (!object) { 456 BREAK_TO_DEBUGGER(); /* Invalid object */ 457 return NULL; 458 } 459 460 offset = le16_to_cpu(object->disp_recordoffset) 461 + bp->object_info_tbl_offset; 462 463 for (;;) { 464 header = GET_IMAGE(struct atom_common_record_header, offset); 465 466 if (!header) 467 return NULL; 468 469 if (header->record_type == LAST_RECORD_TYPE || 470 !header->record_size) 471 break; 472 473 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE 474 && sizeof(struct atom_hpd_int_record) <= 475 header->record_size) 476 return (struct atom_hpd_int_record *) header; 477 478 offset += header->record_size; 479 } 480 481 return NULL; 482 } 483 484 /** 485 * bios_parser_get_gpio_pin_info 486 * Get GpioPin information of input gpio id 487 * 488 * @param gpio_id, GPIO ID 489 * @param info, GpioPin information structure 490 * @return Bios parser result code 491 * @note 492 * to get the GPIO PIN INFO, we need: 493 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 494 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, 495 * to get the registerA offset/mask 496 */ 497 static enum bp_result bios_parser_get_gpio_pin_info( 498 struct dc_bios *dcb, 499 uint32_t gpio_id, 500 struct gpio_pin_info *info) 501 { 502 struct bios_parser *bp = BP_FROM_DCB(dcb); 503 struct atom_gpio_pin_lut_v2_1 *header; 504 uint32_t count = 0; 505 uint32_t i = 0; 506 507 if (!DATA_TABLES(gpio_pin_lut)) 508 return BP_RESULT_BADBIOSTABLE; 509 510 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1, 511 DATA_TABLES(gpio_pin_lut)); 512 if (!header) 513 return BP_RESULT_BADBIOSTABLE; 514 515 if (sizeof(struct atom_common_table_header) + 516 sizeof(struct atom_gpio_pin_assignment) 517 > le16_to_cpu(header->table_header.structuresize)) 518 return BP_RESULT_BADBIOSTABLE; 519 520 if (header->table_header.content_revision != 1) 521 return BP_RESULT_UNSUPPORTED; 522 523 /* Temporary hard code gpio pin info */ 524 #if defined(FOR_SIMNOW_BOOT) 525 { 526 struct atom_gpio_pin_assignment gpio_pin[8] = { 527 {0x5db5, 0, 0, 1, 0}, 528 {0x5db5, 8, 8, 2, 0}, 529 {0x5db5, 0x10, 0x10, 3, 0}, 530 {0x5db5, 0x18, 0x14, 4, 0}, 531 {0x5db5, 0x1A, 0x18, 5, 0}, 532 {0x5db5, 0x1C, 0x1C, 6, 0}, 533 }; 534 535 count = 6; 536 memmove(header->gpio_pin, gpio_pin, sizeof(gpio_pin)); 537 } 538 #else 539 count = (le16_to_cpu(header->table_header.structuresize) 540 - sizeof(struct atom_common_table_header)) 541 / sizeof(struct atom_gpio_pin_assignment); 542 #endif 543 for (i = 0; i < count; ++i) { 544 if (header->gpio_pin[i].gpio_id != gpio_id) 545 continue; 546 547 info->offset = 548 (uint32_t) le16_to_cpu( 549 header->gpio_pin[i].data_a_reg_index); 550 info->offset_y = info->offset + 2; 551 info->offset_en = info->offset + 1; 552 info->offset_mask = info->offset - 1; 553 554 info->mask = (uint32_t) (1 << 555 header->gpio_pin[i].gpio_bitshift); 556 info->mask_y = info->mask + 2; 557 info->mask_en = info->mask + 1; 558 info->mask_mask = info->mask - 1; 559 560 return BP_RESULT_OK; 561 } 562 563 return BP_RESULT_NORECORD; 564 } 565 566 static struct device_id device_type_from_device_id(uint16_t device_id) 567 { 568 569 struct device_id result_device_id; 570 571 result_device_id.raw_device_tag = device_id; 572 573 switch (device_id) { 574 case ATOM_DISPLAY_LCD1_SUPPORT: 575 result_device_id.device_type = DEVICE_TYPE_LCD; 576 result_device_id.enum_id = 1; 577 break; 578 579 case ATOM_DISPLAY_DFP1_SUPPORT: 580 result_device_id.device_type = DEVICE_TYPE_DFP; 581 result_device_id.enum_id = 1; 582 break; 583 584 case ATOM_DISPLAY_DFP2_SUPPORT: 585 result_device_id.device_type = DEVICE_TYPE_DFP; 586 result_device_id.enum_id = 2; 587 break; 588 589 case ATOM_DISPLAY_DFP3_SUPPORT: 590 result_device_id.device_type = DEVICE_TYPE_DFP; 591 result_device_id.enum_id = 3; 592 break; 593 594 case ATOM_DISPLAY_DFP4_SUPPORT: 595 result_device_id.device_type = DEVICE_TYPE_DFP; 596 result_device_id.enum_id = 4; 597 break; 598 599 case ATOM_DISPLAY_DFP5_SUPPORT: 600 result_device_id.device_type = DEVICE_TYPE_DFP; 601 result_device_id.enum_id = 5; 602 break; 603 604 case ATOM_DISPLAY_DFP6_SUPPORT: 605 result_device_id.device_type = DEVICE_TYPE_DFP; 606 result_device_id.enum_id = 6; 607 break; 608 609 default: 610 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 611 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 612 result_device_id.enum_id = 0; 613 } 614 return result_device_id; 615 } 616 617 static enum bp_result bios_parser_get_device_tag( 618 struct dc_bios *dcb, 619 struct graphics_object_id connector_object_id, 620 uint32_t device_tag_index, 621 struct connector_device_tag_info *info) 622 { 623 struct bios_parser *bp = BP_FROM_DCB(dcb); 624 struct atom_display_object_path_v2 *object; 625 626 if (!info) 627 return BP_RESULT_BADINPUT; 628 629 /* getBiosObject will return MXM object */ 630 object = get_bios_object(bp, connector_object_id); 631 632 if (!object) { 633 BREAK_TO_DEBUGGER(); /* Invalid object id */ 634 return BP_RESULT_BADINPUT; 635 } 636 637 info->acpi_device = 0; /* BIOS no longer provides this */ 638 info->dev_id = device_type_from_device_id(object->device_tag); 639 640 return BP_RESULT_OK; 641 } 642 643 static enum bp_result get_ss_info_v4_1( 644 struct bios_parser *bp, 645 uint32_t id, 646 uint32_t index, 647 struct spread_spectrum_info *ss_info) 648 { 649 enum bp_result result = BP_RESULT_OK; 650 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL; 651 struct atom_smu_info_v3_3 *smu_info = NULL; 652 653 if (!ss_info) 654 return BP_RESULT_BADINPUT; 655 656 if (!DATA_TABLES(dce_info)) 657 return BP_RESULT_BADBIOSTABLE; 658 659 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1, 660 DATA_TABLES(dce_info)); 661 if (!disp_cntl_tbl) 662 return BP_RESULT_BADBIOSTABLE; 663 664 665 ss_info->type.STEP_AND_DELAY_INFO = false; 666 ss_info->spread_percentage_divider = 1000; 667 /* BIOS no longer uses target clock. Always enable for now */ 668 ss_info->target_clock_range = 0xffffffff; 669 670 switch (id) { 671 case AS_SIGNAL_TYPE_DVI: 672 ss_info->spread_spectrum_percentage = 673 disp_cntl_tbl->dvi_ss_percentage; 674 ss_info->spread_spectrum_range = 675 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 676 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 677 ss_info->type.CENTER_MODE = true; 678 break; 679 case AS_SIGNAL_TYPE_HDMI: 680 ss_info->spread_spectrum_percentage = 681 disp_cntl_tbl->hdmi_ss_percentage; 682 ss_info->spread_spectrum_range = 683 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 684 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 685 ss_info->type.CENTER_MODE = true; 686 break; 687 /* TODO LVDS not support anymore? */ 688 case AS_SIGNAL_TYPE_DISPLAY_PORT: 689 ss_info->spread_spectrum_percentage = 690 disp_cntl_tbl->dp_ss_percentage; 691 ss_info->spread_spectrum_range = 692 disp_cntl_tbl->dp_ss_rate_10hz * 10; 693 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 694 ss_info->type.CENTER_MODE = true; 695 break; 696 case AS_SIGNAL_TYPE_GPU_PLL: 697 /* atom_firmware: DAL only get data from dce_info table. 698 * if data within smu_info is needed for DAL, VBIOS should 699 * copy it into dce_info 700 */ 701 result = BP_RESULT_UNSUPPORTED; 702 break; 703 case AS_SIGNAL_TYPE_XGMI: 704 smu_info = GET_IMAGE(struct atom_smu_info_v3_3, 705 DATA_TABLES(smu_info)); 706 if (!smu_info) 707 return BP_RESULT_BADBIOSTABLE; 708 709 ss_info->spread_spectrum_percentage = 710 smu_info->waflclk_ss_percentage; 711 ss_info->spread_spectrum_range = 712 smu_info->gpuclk_ss_rate_10hz * 10; 713 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 714 ss_info->type.CENTER_MODE = true; 715 break; 716 default: 717 result = BP_RESULT_UNSUPPORTED; 718 } 719 720 return result; 721 } 722 723 static enum bp_result get_ss_info_v4_2( 724 struct bios_parser *bp, 725 uint32_t id, 726 uint32_t index, 727 struct spread_spectrum_info *ss_info) 728 { 729 enum bp_result result = BP_RESULT_OK; 730 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL; 731 struct atom_smu_info_v3_1 *smu_info = NULL; 732 733 if (!ss_info) 734 return BP_RESULT_BADINPUT; 735 736 if (!DATA_TABLES(dce_info)) 737 return BP_RESULT_BADBIOSTABLE; 738 739 if (!DATA_TABLES(smu_info)) 740 return BP_RESULT_BADBIOSTABLE; 741 742 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2, 743 DATA_TABLES(dce_info)); 744 if (!disp_cntl_tbl) 745 return BP_RESULT_BADBIOSTABLE; 746 747 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info)); 748 if (!smu_info) 749 return BP_RESULT_BADBIOSTABLE; 750 751 ss_info->type.STEP_AND_DELAY_INFO = false; 752 ss_info->spread_percentage_divider = 1000; 753 /* BIOS no longer uses target clock. Always enable for now */ 754 ss_info->target_clock_range = 0xffffffff; 755 756 switch (id) { 757 case AS_SIGNAL_TYPE_DVI: 758 ss_info->spread_spectrum_percentage = 759 disp_cntl_tbl->dvi_ss_percentage; 760 ss_info->spread_spectrum_range = 761 disp_cntl_tbl->dvi_ss_rate_10hz * 10; 762 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 763 ss_info->type.CENTER_MODE = true; 764 break; 765 case AS_SIGNAL_TYPE_HDMI: 766 ss_info->spread_spectrum_percentage = 767 disp_cntl_tbl->hdmi_ss_percentage; 768 ss_info->spread_spectrum_range = 769 disp_cntl_tbl->hdmi_ss_rate_10hz * 10; 770 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 771 ss_info->type.CENTER_MODE = true; 772 break; 773 /* TODO LVDS not support anymore? */ 774 case AS_SIGNAL_TYPE_DISPLAY_PORT: 775 ss_info->spread_spectrum_percentage = 776 smu_info->gpuclk_ss_percentage; 777 ss_info->spread_spectrum_range = 778 smu_info->gpuclk_ss_rate_10hz * 10; 779 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE) 780 ss_info->type.CENTER_MODE = true; 781 break; 782 case AS_SIGNAL_TYPE_GPU_PLL: 783 /* atom_firmware: DAL only get data from dce_info table. 784 * if data within smu_info is needed for DAL, VBIOS should 785 * copy it into dce_info 786 */ 787 result = BP_RESULT_UNSUPPORTED; 788 break; 789 default: 790 result = BP_RESULT_UNSUPPORTED; 791 } 792 793 return result; 794 } 795 796 /** 797 * bios_parser_get_spread_spectrum_info 798 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 799 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 800 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info 801 * ver 3.1, 802 * there is only one entry for each signal /ss id. However, there is 803 * no planning of supporting multiple spread Sprectum entry for EverGreen 804 * @param [in] this 805 * @param [in] signal, ASSignalType to be converted to info index 806 * @param [in] index, number of entries that match the converted info index 807 * @param [out] ss_info, sprectrum information structure, 808 * @return Bios parser result code 809 */ 810 static enum bp_result bios_parser_get_spread_spectrum_info( 811 struct dc_bios *dcb, 812 enum as_signal_type signal, 813 uint32_t index, 814 struct spread_spectrum_info *ss_info) 815 { 816 struct bios_parser *bp = BP_FROM_DCB(dcb); 817 enum bp_result result = BP_RESULT_UNSUPPORTED; 818 struct atom_common_table_header *header; 819 struct atom_data_revision tbl_revision; 820 821 if (!ss_info) /* check for bad input */ 822 return BP_RESULT_BADINPUT; 823 824 if (!DATA_TABLES(dce_info)) 825 return BP_RESULT_UNSUPPORTED; 826 827 header = GET_IMAGE(struct atom_common_table_header, 828 DATA_TABLES(dce_info)); 829 get_atom_data_table_revision(header, &tbl_revision); 830 831 switch (tbl_revision.major) { 832 case 4: 833 switch (tbl_revision.minor) { 834 case 1: 835 return get_ss_info_v4_1(bp, signal, index, ss_info); 836 case 2: 837 case 3: 838 return get_ss_info_v4_2(bp, signal, index, ss_info); 839 default: 840 break; 841 } 842 break; 843 default: 844 break; 845 } 846 /* there can not be more then one entry for SS Info table */ 847 return result; 848 } 849 850 static enum bp_result get_soc_bb_info_v4_4( 851 struct bios_parser *bp, 852 struct bp_soc_bb_info *soc_bb_info) 853 { 854 enum bp_result result = BP_RESULT_OK; 855 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL; 856 857 if (!soc_bb_info) 858 return BP_RESULT_BADINPUT; 859 860 if (!DATA_TABLES(dce_info)) 861 return BP_RESULT_BADBIOSTABLE; 862 863 if (!DATA_TABLES(smu_info)) 864 return BP_RESULT_BADBIOSTABLE; 865 866 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4, 867 DATA_TABLES(dce_info)); 868 if (!disp_cntl_tbl) 869 return BP_RESULT_BADBIOSTABLE; 870 871 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat; 872 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat; 873 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat; 874 875 return result; 876 } 877 878 static enum bp_result bios_parser_get_soc_bb_info( 879 struct dc_bios *dcb, 880 struct bp_soc_bb_info *soc_bb_info) 881 { 882 struct bios_parser *bp = BP_FROM_DCB(dcb); 883 enum bp_result result = BP_RESULT_UNSUPPORTED; 884 struct atom_common_table_header *header; 885 struct atom_data_revision tbl_revision; 886 887 if (!soc_bb_info) /* check for bad input */ 888 return BP_RESULT_BADINPUT; 889 890 if (!DATA_TABLES(dce_info)) 891 return BP_RESULT_UNSUPPORTED; 892 893 header = GET_IMAGE(struct atom_common_table_header, 894 DATA_TABLES(dce_info)); 895 get_atom_data_table_revision(header, &tbl_revision); 896 897 switch (tbl_revision.major) { 898 case 4: 899 switch (tbl_revision.minor) { 900 case 1: 901 case 2: 902 case 3: 903 break; 904 case 4: 905 result = get_soc_bb_info_v4_4(bp, soc_bb_info); 906 break; 907 default: 908 break; 909 } 910 break; 911 default: 912 break; 913 } 914 915 return result; 916 } 917 918 static enum bp_result get_embedded_panel_info_v2_1( 919 struct bios_parser *bp, 920 struct embedded_panel_info *info) 921 { 922 struct lcd_info_v2_1 *lvds; 923 924 if (!info) 925 return BP_RESULT_BADINPUT; 926 927 if (!DATA_TABLES(lcd_info)) 928 return BP_RESULT_UNSUPPORTED; 929 930 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info)); 931 932 if (!lvds) 933 return BP_RESULT_BADBIOSTABLE; 934 935 /* TODO: previous vv1_3, should v2_1 */ 936 if (!((lvds->table_header.format_revision == 2) 937 && (lvds->table_header.content_revision >= 1))) 938 return BP_RESULT_UNSUPPORTED; 939 940 memset(info, 0, sizeof(struct embedded_panel_info)); 941 942 /* We need to convert from 10KHz units into KHz units */ 943 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; 944 /* usHActive does not include borders, according to VBIOS team */ 945 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active); 946 /* usHBlanking_Time includes borders, so we should really be 947 * subtractingborders duing this translation, but LVDS generally 948 * doesn't have borders, so we should be okay leaving this as is for 949 * now. May need to revisit if we ever have LVDS with borders 950 */ 951 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time); 952 /* usVActive does not include borders, according to VBIOS team*/ 953 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active); 954 /* usVBlanking_Time includes borders, so we should really be 955 * subtracting borders duing this translation, but LVDS generally 956 * doesn't have borders, so we should be okay leaving this as is for 957 * now. May need to revisit if we ever have LVDS with borders 958 */ 959 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time); 960 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset); 961 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); 962 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset); 963 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth); 964 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border; 965 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border; 966 967 /* not provided by VBIOS */ 968 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0; 969 970 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 971 & ATOM_HSYNC_POLARITY); 972 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo 973 & ATOM_VSYNC_POLARITY); 974 975 /* not provided by VBIOS */ 976 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0; 977 978 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 979 & ATOM_H_REPLICATIONBY2); 980 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo 981 & ATOM_V_REPLICATIONBY2); 982 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo 983 & ATOM_COMPOSITESYNC); 984 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE); 985 986 /* not provided by VBIOS*/ 987 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0; 988 /* not provided by VBIOS*/ 989 info->ss_id = 0; 990 991 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID); 992 993 return BP_RESULT_OK; 994 } 995 996 static enum bp_result bios_parser_get_embedded_panel_info( 997 struct dc_bios *dcb, 998 struct embedded_panel_info *info) 999 { 1000 struct bios_parser 1001 *bp = BP_FROM_DCB(dcb); 1002 struct atom_common_table_header *header; 1003 struct atom_data_revision tbl_revision; 1004 1005 if (!DATA_TABLES(lcd_info)) 1006 return BP_RESULT_FAILURE; 1007 1008 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info)); 1009 1010 if (!header) 1011 return BP_RESULT_BADBIOSTABLE; 1012 1013 get_atom_data_table_revision(header, &tbl_revision); 1014 1015 switch (tbl_revision.major) { 1016 case 2: 1017 switch (tbl_revision.minor) { 1018 case 1: 1019 return get_embedded_panel_info_v2_1(bp, info); 1020 default: 1021 break; 1022 } 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 return BP_RESULT_FAILURE; 1029 } 1030 1031 static uint32_t get_support_mask_for_device_id(struct device_id device_id) 1032 { 1033 enum dal_device_type device_type = device_id.device_type; 1034 uint32_t enum_id = device_id.enum_id; 1035 1036 switch (device_type) { 1037 case DEVICE_TYPE_LCD: 1038 switch (enum_id) { 1039 case 1: 1040 return ATOM_DISPLAY_LCD1_SUPPORT; 1041 default: 1042 break; 1043 } 1044 break; 1045 case DEVICE_TYPE_DFP: 1046 switch (enum_id) { 1047 case 1: 1048 return ATOM_DISPLAY_DFP1_SUPPORT; 1049 case 2: 1050 return ATOM_DISPLAY_DFP2_SUPPORT; 1051 case 3: 1052 return ATOM_DISPLAY_DFP3_SUPPORT; 1053 case 4: 1054 return ATOM_DISPLAY_DFP4_SUPPORT; 1055 case 5: 1056 return ATOM_DISPLAY_DFP5_SUPPORT; 1057 case 6: 1058 return ATOM_DISPLAY_DFP6_SUPPORT; 1059 default: 1060 break; 1061 } 1062 break; 1063 default: 1064 break; 1065 } 1066 1067 /* Unidentified device ID, return empty support mask. */ 1068 return 0; 1069 } 1070 1071 static bool bios_parser_is_device_id_supported( 1072 struct dc_bios *dcb, 1073 struct device_id id) 1074 { 1075 struct bios_parser *bp = BP_FROM_DCB(dcb); 1076 1077 uint32_t mask = get_support_mask_for_device_id(id); 1078 1079 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & 1080 mask) != 0; 1081 } 1082 1083 static uint32_t bios_parser_get_ss_entry_number( 1084 struct dc_bios *dcb, 1085 enum as_signal_type signal) 1086 { 1087 /* TODO: DAL2 atomfirmware implementation does not need this. 1088 * why DAL3 need this? 1089 */ 1090 return 1; 1091 } 1092 1093 static enum bp_result bios_parser_transmitter_control( 1094 struct dc_bios *dcb, 1095 struct bp_transmitter_control *cntl) 1096 { 1097 struct bios_parser *bp = BP_FROM_DCB(dcb); 1098 1099 if (!bp->cmd_tbl.transmitter_control) 1100 return BP_RESULT_FAILURE; 1101 1102 return bp->cmd_tbl.transmitter_control(bp, cntl); 1103 } 1104 1105 static enum bp_result bios_parser_encoder_control( 1106 struct dc_bios *dcb, 1107 struct bp_encoder_control *cntl) 1108 { 1109 struct bios_parser *bp = BP_FROM_DCB(dcb); 1110 1111 if (!bp->cmd_tbl.dig_encoder_control) 1112 return BP_RESULT_FAILURE; 1113 1114 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 1115 } 1116 1117 static enum bp_result bios_parser_set_pixel_clock( 1118 struct dc_bios *dcb, 1119 struct bp_pixel_clock_parameters *bp_params) 1120 { 1121 struct bios_parser *bp = BP_FROM_DCB(dcb); 1122 1123 if (!bp->cmd_tbl.set_pixel_clock) 1124 return BP_RESULT_FAILURE; 1125 1126 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 1127 } 1128 1129 static enum bp_result bios_parser_set_dce_clock( 1130 struct dc_bios *dcb, 1131 struct bp_set_dce_clock_parameters *bp_params) 1132 { 1133 struct bios_parser *bp = BP_FROM_DCB(dcb); 1134 1135 if (!bp->cmd_tbl.set_dce_clock) 1136 return BP_RESULT_FAILURE; 1137 1138 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 1139 } 1140 1141 static enum bp_result bios_parser_program_crtc_timing( 1142 struct dc_bios *dcb, 1143 struct bp_hw_crtc_timing_parameters *bp_params) 1144 { 1145 struct bios_parser *bp = BP_FROM_DCB(dcb); 1146 1147 if (!bp->cmd_tbl.set_crtc_timing) 1148 return BP_RESULT_FAILURE; 1149 1150 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 1151 } 1152 1153 static enum bp_result bios_parser_enable_crtc( 1154 struct dc_bios *dcb, 1155 enum controller_id id, 1156 bool enable) 1157 { 1158 struct bios_parser *bp = BP_FROM_DCB(dcb); 1159 1160 if (!bp->cmd_tbl.enable_crtc) 1161 return BP_RESULT_FAILURE; 1162 1163 return bp->cmd_tbl.enable_crtc(bp, id, enable); 1164 } 1165 1166 static enum bp_result bios_parser_enable_disp_power_gating( 1167 struct dc_bios *dcb, 1168 enum controller_id controller_id, 1169 enum bp_pipe_control_action action) 1170 { 1171 struct bios_parser *bp = BP_FROM_DCB(dcb); 1172 1173 if (!bp->cmd_tbl.enable_disp_power_gating) 1174 return BP_RESULT_FAILURE; 1175 1176 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 1177 action); 1178 } 1179 1180 static enum bp_result bios_parser_enable_lvtma_control( 1181 struct dc_bios *dcb, 1182 uint8_t uc_pwr_on) 1183 { 1184 struct bios_parser *bp = BP_FROM_DCB(dcb); 1185 1186 if (!bp->cmd_tbl.enable_lvtma_control) 1187 return BP_RESULT_FAILURE; 1188 1189 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on); 1190 } 1191 1192 static bool bios_parser_is_accelerated_mode( 1193 struct dc_bios *dcb) 1194 { 1195 return bios_is_accelerated_mode(dcb); 1196 } 1197 1198 /** 1199 * bios_parser_set_scratch_critical_state 1200 * 1201 * @brief 1202 * update critical state bit in VBIOS scratch register 1203 * 1204 * @param 1205 * bool - to set or reset state 1206 */ 1207 static void bios_parser_set_scratch_critical_state( 1208 struct dc_bios *dcb, 1209 bool state) 1210 { 1211 bios_set_scratch_critical_state(dcb, state); 1212 } 1213 1214 static enum bp_result bios_parser_get_firmware_info( 1215 struct dc_bios *dcb, 1216 struct dc_firmware_info *info) 1217 { 1218 struct bios_parser *bp = BP_FROM_DCB(dcb); 1219 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1220 struct atom_common_table_header *header; 1221 1222 struct atom_data_revision revision; 1223 1224 if (info && DATA_TABLES(firmwareinfo)) { 1225 header = GET_IMAGE(struct atom_common_table_header, 1226 DATA_TABLES(firmwareinfo)); 1227 get_atom_data_table_revision(header, &revision); 1228 switch (revision.major) { 1229 case 3: 1230 switch (revision.minor) { 1231 case 1: 1232 result = get_firmware_info_v3_1(bp, info); 1233 break; 1234 case 2: 1235 case 3: 1236 case 4: 1237 result = get_firmware_info_v3_2(bp, info); 1238 break; 1239 default: 1240 break; 1241 } 1242 break; 1243 default: 1244 break; 1245 } 1246 } 1247 1248 return result; 1249 } 1250 1251 static enum bp_result get_firmware_info_v3_1( 1252 struct bios_parser *bp, 1253 struct dc_firmware_info *info) 1254 { 1255 struct atom_firmware_info_v3_1 *firmware_info; 1256 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1257 1258 if (!info) 1259 return BP_RESULT_BADINPUT; 1260 1261 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1, 1262 DATA_TABLES(firmwareinfo)); 1263 1264 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1265 DATA_TABLES(dce_info)); 1266 1267 if (!firmware_info || !dce_info) 1268 return BP_RESULT_BADBIOSTABLE; 1269 1270 memset(info, 0, sizeof(*info)); 1271 1272 /* Pixel clock pll information. */ 1273 /* We need to convert from 10KHz units into KHz units */ 1274 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1275 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10; 1276 1277 /* 27MHz for Vega10: */ 1278 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1279 1280 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1281 if (info->pll_info.crystal_frequency == 0) 1282 info->pll_info.crystal_frequency = 27000; 1283 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1284 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1285 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1286 1287 /* Get GPU PLL VCO Clock */ 1288 1289 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1290 /* VBIOS gives in 10KHz */ 1291 info->smu_gpu_pll_output_freq = 1292 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1293 } 1294 1295 info->oem_i2c_present = false; 1296 1297 return BP_RESULT_OK; 1298 } 1299 1300 static enum bp_result get_firmware_info_v3_2( 1301 struct bios_parser *bp, 1302 struct dc_firmware_info *info) 1303 { 1304 struct atom_firmware_info_v3_2 *firmware_info; 1305 struct atom_display_controller_info_v4_1 *dce_info = NULL; 1306 struct atom_common_table_header *header; 1307 struct atom_data_revision revision; 1308 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; 1309 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; 1310 1311 if (!info) 1312 return BP_RESULT_BADINPUT; 1313 1314 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, 1315 DATA_TABLES(firmwareinfo)); 1316 1317 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, 1318 DATA_TABLES(dce_info)); 1319 1320 if (!firmware_info || !dce_info) 1321 return BP_RESULT_BADBIOSTABLE; 1322 1323 memset(info, 0, sizeof(*info)); 1324 1325 header = GET_IMAGE(struct atom_common_table_header, 1326 DATA_TABLES(smu_info)); 1327 get_atom_data_table_revision(header, &revision); 1328 1329 if (revision.minor == 2) { 1330 /* Vega12 */ 1331 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, 1332 DATA_TABLES(smu_info)); 1333 1334 if (!smu_info_v3_2) 1335 return BP_RESULT_BADBIOSTABLE; 1336 1337 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; 1338 } else if (revision.minor == 3) { 1339 /* Vega20 */ 1340 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, 1341 DATA_TABLES(smu_info)); 1342 1343 if (!smu_info_v3_3) 1344 return BP_RESULT_BADBIOSTABLE; 1345 1346 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; 1347 } 1348 1349 // We need to convert from 10KHz units into KHz units. 1350 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; 1351 1352 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ 1353 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; 1354 /* Hardcode frequency if BIOS gives no DCE Ref Clk */ 1355 if (info->pll_info.crystal_frequency == 0) { 1356 if (revision.minor == 2) 1357 info->pll_info.crystal_frequency = 27000; 1358 else if (revision.minor == 3) 1359 info->pll_info.crystal_frequency = 100000; 1360 } 1361 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ 1362 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; 1363 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; 1364 1365 /* Get GPU PLL VCO Clock */ 1366 if (bp->cmd_tbl.get_smu_clock_info != NULL) { 1367 if (revision.minor == 2) 1368 info->smu_gpu_pll_output_freq = 1369 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; 1370 else if (revision.minor == 3) 1371 info->smu_gpu_pll_output_freq = 1372 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; 1373 } 1374 1375 if (firmware_info->board_i2c_feature_id == 0x2) { 1376 info->oem_i2c_present = true; 1377 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id; 1378 } else { 1379 info->oem_i2c_present = false; 1380 } 1381 1382 return BP_RESULT_OK; 1383 } 1384 1385 static enum bp_result bios_parser_get_encoder_cap_info( 1386 struct dc_bios *dcb, 1387 struct graphics_object_id object_id, 1388 struct bp_encoder_cap_info *info) 1389 { 1390 struct bios_parser *bp = BP_FROM_DCB(dcb); 1391 struct atom_display_object_path_v2 *object; 1392 struct atom_encoder_caps_record *record = NULL; 1393 1394 if (!info) 1395 return BP_RESULT_BADINPUT; 1396 1397 object = get_bios_object(bp, object_id); 1398 1399 if (!object) 1400 return BP_RESULT_BADINPUT; 1401 1402 record = get_encoder_cap_record(bp, object); 1403 if (!record) 1404 return BP_RESULT_NORECORD; 1405 1406 info->DP_HBR2_CAP = (record->encodercaps & 1407 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0; 1408 info->DP_HBR2_EN = (record->encodercaps & 1409 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0; 1410 info->DP_HBR3_EN = (record->encodercaps & 1411 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0; 1412 info->HDMI_6GB_EN = (record->encodercaps & 1413 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0; 1414 info->DP_IS_USB_C = (record->encodercaps & 1415 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0; 1416 1417 return BP_RESULT_OK; 1418 } 1419 1420 1421 static struct atom_encoder_caps_record *get_encoder_cap_record( 1422 struct bios_parser *bp, 1423 struct atom_display_object_path_v2 *object) 1424 { 1425 struct atom_common_record_header *header; 1426 uint32_t offset; 1427 1428 if (!object) { 1429 BREAK_TO_DEBUGGER(); /* Invalid object */ 1430 return NULL; 1431 } 1432 1433 offset = object->encoder_recordoffset + bp->object_info_tbl_offset; 1434 1435 for (;;) { 1436 header = GET_IMAGE(struct atom_common_record_header, offset); 1437 1438 if (!header) 1439 return NULL; 1440 1441 offset += header->record_size; 1442 1443 if (header->record_type == LAST_RECORD_TYPE || 1444 !header->record_size) 1445 break; 1446 1447 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE) 1448 continue; 1449 1450 if (sizeof(struct atom_encoder_caps_record) <= 1451 header->record_size) 1452 return (struct atom_encoder_caps_record *)header; 1453 } 1454 1455 return NULL; 1456 } 1457 1458 static enum bp_result get_vram_info_v23( 1459 struct bios_parser *bp, 1460 struct dc_vram_info *info) 1461 { 1462 struct atom_vram_info_header_v2_3 *info_v23; 1463 enum bp_result result = BP_RESULT_OK; 1464 1465 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3, 1466 DATA_TABLES(vram_info)); 1467 1468 if (info_v23 == NULL) 1469 return BP_RESULT_BADBIOSTABLE; 1470 1471 info->num_chans = info_v23->vram_module[0].channel_num; 1472 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; 1473 1474 return result; 1475 } 1476 1477 static enum bp_result get_vram_info_v24( 1478 struct bios_parser *bp, 1479 struct dc_vram_info *info) 1480 { 1481 struct atom_vram_info_header_v2_4 *info_v24; 1482 enum bp_result result = BP_RESULT_OK; 1483 1484 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4, 1485 DATA_TABLES(vram_info)); 1486 1487 if (info_v24 == NULL) 1488 return BP_RESULT_BADBIOSTABLE; 1489 1490 info->num_chans = info_v24->vram_module[0].channel_num; 1491 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; 1492 1493 return result; 1494 } 1495 1496 static enum bp_result get_vram_info_v25( 1497 struct bios_parser *bp, 1498 struct dc_vram_info *info) 1499 { 1500 struct atom_vram_info_header_v2_5 *info_v25; 1501 enum bp_result result = BP_RESULT_OK; 1502 1503 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5, 1504 DATA_TABLES(vram_info)); 1505 1506 if (info_v25 == NULL) 1507 return BP_RESULT_BADBIOSTABLE; 1508 1509 info->num_chans = info_v25->vram_module[0].channel_num; 1510 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; 1511 1512 return result; 1513 } 1514 1515 /* 1516 * get_integrated_info_v11 1517 * 1518 * @brief 1519 * Get V8 integrated BIOS information 1520 * 1521 * @param 1522 * bios_parser *bp - [in]BIOS parser handler to get master data table 1523 * integrated_info *info - [out] store and output integrated info 1524 * 1525 * @return 1526 * enum bp_result - BP_RESULT_OK if information is available, 1527 * BP_RESULT_BADBIOSTABLE otherwise. 1528 */ 1529 static enum bp_result get_integrated_info_v11( 1530 struct bios_parser *bp, 1531 struct integrated_info *info) 1532 { 1533 struct atom_integrated_system_info_v1_11 *info_v11; 1534 uint32_t i; 1535 1536 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11, 1537 DATA_TABLES(integratedsysteminfo)); 1538 1539 if (info_v11 == NULL) 1540 return BP_RESULT_BADBIOSTABLE; 1541 1542 info->gpu_cap_info = 1543 le32_to_cpu(info_v11->gpucapinfo); 1544 /* 1545 * system_config: Bit[0] = 0 : PCIE power gating disabled 1546 * = 1 : PCIE power gating enabled 1547 * Bit[1] = 0 : DDR-PLL shut down disabled 1548 * = 1 : DDR-PLL shut down enabled 1549 * Bit[2] = 0 : DDR-PLL power down disabled 1550 * = 1 : DDR-PLL power down enabled 1551 */ 1552 info->system_config = le32_to_cpu(info_v11->system_config); 1553 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo); 1554 info->memory_type = info_v11->memorytype; 1555 info->ma_channel_number = info_v11->umachannelnumber; 1556 info->lvds_ss_percentage = 1557 le16_to_cpu(info_v11->lvds_ss_percentage); 1558 info->dp_ss_control = 1559 le16_to_cpu(info_v11->reserved1); 1560 info->lvds_sspread_rate_in_10hz = 1561 le16_to_cpu(info_v11->lvds_ss_rate_10hz); 1562 info->hdmi_ss_percentage = 1563 le16_to_cpu(info_v11->hdmi_ss_percentage); 1564 info->hdmi_sspread_rate_in_10hz = 1565 le16_to_cpu(info_v11->hdmi_ss_rate_10hz); 1566 info->dvi_ss_percentage = 1567 le16_to_cpu(info_v11->dvi_ss_percentage); 1568 info->dvi_sspread_rate_in_10_hz = 1569 le16_to_cpu(info_v11->dvi_ss_rate_10hz); 1570 info->lvds_misc = info_v11->lvds_misc; 1571 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1572 info->ext_disp_conn_info.gu_id[i] = 1573 info_v11->extdispconninfo.guid[i]; 1574 } 1575 1576 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1577 info->ext_disp_conn_info.path[i].device_connector_id = 1578 object_id_from_bios_object_id( 1579 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid)); 1580 1581 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1582 object_id_from_bios_object_id( 1583 le16_to_cpu( 1584 info_v11->extdispconninfo.path[i].ext_encoder_objid)); 1585 1586 info->ext_disp_conn_info.path[i].device_tag = 1587 le16_to_cpu( 1588 info_v11->extdispconninfo.path[i].device_tag); 1589 info->ext_disp_conn_info.path[i].device_acpi_enum = 1590 le16_to_cpu( 1591 info_v11->extdispconninfo.path[i].device_acpi_enum); 1592 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1593 info_v11->extdispconninfo.path[i].auxddclut_index; 1594 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1595 info_v11->extdispconninfo.path[i].hpdlut_index; 1596 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1597 info_v11->extdispconninfo.path[i].channelmapping; 1598 info->ext_disp_conn_info.path[i].caps = 1599 le16_to_cpu(info_v11->extdispconninfo.path[i].caps); 1600 } 1601 info->ext_disp_conn_info.checksum = 1602 info_v11->extdispconninfo.checksum; 1603 1604 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr; 1605 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum; 1606 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1607 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1608 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1609 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1610 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1611 } 1612 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum; 1613 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1614 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1615 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1616 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1617 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1618 } 1619 1620 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr; 1621 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum; 1622 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1623 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1624 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1625 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1626 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1627 } 1628 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum; 1629 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1630 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1631 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1632 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1633 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1634 } 1635 1636 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr; 1637 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum; 1638 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1639 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1640 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1641 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1642 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1643 } 1644 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum; 1645 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1646 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1647 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1648 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1649 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1650 } 1651 1652 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr; 1653 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum; 1654 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1655 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1656 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1657 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1658 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1659 } 1660 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum; 1661 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1662 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1663 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1664 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1665 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1666 } 1667 1668 1669 /** TODO - review **/ 1670 #if 0 1671 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock) 1672 * 10; 1673 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10; 1674 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 1675 1676 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1677 /* Convert [10KHz] into [KHz] */ 1678 info->disp_clk_voltage[i].max_supported_clk = 1679 le32_to_cpu(info_v11->sDISPCLK_Voltage[i]. 1680 ulMaximumSupportedCLK) * 10; 1681 info->disp_clk_voltage[i].voltage_index = 1682 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex); 1683 } 1684 1685 info->boot_up_req_display_vector = 1686 le32_to_cpu(info_v11->ulBootUpReqDisplayVector); 1687 info->boot_up_nb_voltage = 1688 le16_to_cpu(info_v11->usBootUpNBVoltage); 1689 info->ext_disp_conn_info_offset = 1690 le16_to_cpu(info_v11->usExtDispConnInfoOffset); 1691 info->gmc_restore_reset_time = 1692 le32_to_cpu(info_v11->ulGMCRestoreResetTime); 1693 info->minimum_n_clk = 1694 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]); 1695 for (i = 1; i < 4; ++i) 1696 info->minimum_n_clk = 1697 info->minimum_n_clk < 1698 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ? 1699 info->minimum_n_clk : le32_to_cpu( 1700 info_v11->ulNbpStateNClkFreq[i]); 1701 1702 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk); 1703 info->ddr_dll_power_up_time = 1704 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime); 1705 info->ddr_pll_power_up_time = 1706 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime); 1707 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType); 1708 info->max_lvds_pclk_freq_in_single_link = 1709 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1710 info->max_lvds_pclk_freq_in_single_link = 1711 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink); 1712 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 1713 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 1714 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 1715 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 1716 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 1717 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 1718 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 1719 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 1720 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 1721 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 1722 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 1723 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 1724 info->lvds_off_to_on_delay_in_4ms = 1725 info_v11->ucLVDSOffToOnDelay_in4Ms; 1726 info->lvds_bit_depth_control_val = 1727 le32_to_cpu(info_v11->ulLCDBitDepthControlVal); 1728 1729 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 1730 /* Convert [10KHz] into [KHz] */ 1731 info->avail_s_clk[i].supported_s_clk = 1732 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK) 1733 * 10; 1734 info->avail_s_clk[i].voltage_index = 1735 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex); 1736 info->avail_s_clk[i].voltage_id = 1737 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID); 1738 } 1739 #endif /* TODO*/ 1740 1741 return BP_RESULT_OK; 1742 } 1743 1744 static enum bp_result get_integrated_info_v2_1( 1745 struct bios_parser *bp, 1746 struct integrated_info *info) 1747 { 1748 struct atom_integrated_system_info_v2_1 *info_v2_1; 1749 uint32_t i; 1750 1751 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1, 1752 DATA_TABLES(integratedsysteminfo)); 1753 1754 if (info_v2_1 == NULL) 1755 return BP_RESULT_BADBIOSTABLE; 1756 1757 info->gpu_cap_info = 1758 le32_to_cpu(info_v2_1->gpucapinfo); 1759 /* 1760 * system_config: Bit[0] = 0 : PCIE power gating disabled 1761 * = 1 : PCIE power gating enabled 1762 * Bit[1] = 0 : DDR-PLL shut down disabled 1763 * = 1 : DDR-PLL shut down enabled 1764 * Bit[2] = 0 : DDR-PLL power down disabled 1765 * = 1 : DDR-PLL power down enabled 1766 */ 1767 info->system_config = le32_to_cpu(info_v2_1->system_config); 1768 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo); 1769 info->memory_type = info_v2_1->memorytype; 1770 info->ma_channel_number = info_v2_1->umachannelnumber; 1771 info->dp_ss_control = 1772 le16_to_cpu(info_v2_1->reserved1); 1773 1774 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 1775 info->ext_disp_conn_info.gu_id[i] = 1776 info_v2_1->extdispconninfo.guid[i]; 1777 } 1778 1779 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 1780 info->ext_disp_conn_info.path[i].device_connector_id = 1781 object_id_from_bios_object_id( 1782 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid)); 1783 1784 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 1785 object_id_from_bios_object_id( 1786 le16_to_cpu( 1787 info_v2_1->extdispconninfo.path[i].ext_encoder_objid)); 1788 1789 info->ext_disp_conn_info.path[i].device_tag = 1790 le16_to_cpu( 1791 info_v2_1->extdispconninfo.path[i].device_tag); 1792 info->ext_disp_conn_info.path[i].device_acpi_enum = 1793 le16_to_cpu( 1794 info_v2_1->extdispconninfo.path[i].device_acpi_enum); 1795 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 1796 info_v2_1->extdispconninfo.path[i].auxddclut_index; 1797 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 1798 info_v2_1->extdispconninfo.path[i].hpdlut_index; 1799 info->ext_disp_conn_info.path[i].channel_mapping.raw = 1800 info_v2_1->extdispconninfo.path[i].channelmapping; 1801 info->ext_disp_conn_info.path[i].caps = 1802 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps); 1803 } 1804 1805 info->ext_disp_conn_info.checksum = 1806 info_v2_1->extdispconninfo.checksum; 1807 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr; 1808 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum; 1809 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) { 1810 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index = 1811 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1812 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val = 1813 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1814 } 1815 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum; 1816 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) { 1817 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1818 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1819 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1820 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1821 } 1822 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr; 1823 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum; 1824 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) { 1825 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index = 1826 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1827 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val = 1828 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1829 } 1830 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum; 1831 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) { 1832 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1833 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1834 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1835 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1836 } 1837 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr; 1838 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum; 1839 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) { 1840 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index = 1841 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1842 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val = 1843 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1844 } 1845 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum; 1846 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) { 1847 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1848 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1849 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1850 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1851 } 1852 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr; 1853 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum; 1854 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) { 1855 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index = 1856 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex; 1857 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val = 1858 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal; 1859 } 1860 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum; 1861 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) { 1862 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index = 1863 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex; 1864 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val = 1865 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal; 1866 } 1867 1868 info->edp1_info.edp_backlight_pwm_hz = 1869 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz); 1870 info->edp1_info.edp_ss_percentage = 1871 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage); 1872 info->edp1_info.edp_ss_rate_10hz = 1873 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz); 1874 info->edp1_info.edp_pwr_on_off_delay = 1875 info_v2_1->edp1_info.edp_pwr_on_off_delay; 1876 info->edp1_info.edp_pwr_on_vary_bl_to_blon = 1877 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon; 1878 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff = 1879 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff; 1880 info->edp1_info.edp_panel_bpc = 1881 info_v2_1->edp1_info.edp_panel_bpc; 1882 info->edp1_info.edp_bootup_bl_level = 1883 1884 info->edp2_info.edp_backlight_pwm_hz = 1885 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz); 1886 info->edp2_info.edp_ss_percentage = 1887 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage); 1888 info->edp2_info.edp_ss_rate_10hz = 1889 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz); 1890 info->edp2_info.edp_pwr_on_off_delay = 1891 info_v2_1->edp2_info.edp_pwr_on_off_delay; 1892 info->edp2_info.edp_pwr_on_vary_bl_to_blon = 1893 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon; 1894 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff = 1895 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff; 1896 info->edp2_info.edp_panel_bpc = 1897 info_v2_1->edp2_info.edp_panel_bpc; 1898 info->edp2_info.edp_bootup_bl_level = 1899 info_v2_1->edp2_info.edp_bootup_bl_level; 1900 1901 return BP_RESULT_OK; 1902 } 1903 1904 /* 1905 * construct_integrated_info 1906 * 1907 * @brief 1908 * Get integrated BIOS information based on table revision 1909 * 1910 * @param 1911 * bios_parser *bp - [in]BIOS parser handler to get master data table 1912 * integrated_info *info - [out] store and output integrated info 1913 * 1914 * @return 1915 * enum bp_result - BP_RESULT_OK if information is available, 1916 * BP_RESULT_BADBIOSTABLE otherwise. 1917 */ 1918 static enum bp_result construct_integrated_info( 1919 struct bios_parser *bp, 1920 struct integrated_info *info) 1921 { 1922 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1923 1924 struct atom_common_table_header *header; 1925 struct atom_data_revision revision; 1926 uint32_t i; 1927 uint32_t j; 1928 1929 if (info && DATA_TABLES(integratedsysteminfo)) { 1930 header = GET_IMAGE(struct atom_common_table_header, 1931 DATA_TABLES(integratedsysteminfo)); 1932 1933 get_atom_data_table_revision(header, &revision); 1934 1935 switch (revision.major) { 1936 case 1: 1937 switch (revision.minor) { 1938 case 11: 1939 case 12: 1940 result = get_integrated_info_v11(bp, info); 1941 break; 1942 default: 1943 return result; 1944 } 1945 break; 1946 case 2: 1947 switch (revision.minor) { 1948 case 1: 1949 result = get_integrated_info_v2_1(bp, info); 1950 break; 1951 default: 1952 return result; 1953 } 1954 break; 1955 default: 1956 return result; 1957 } 1958 } 1959 1960 if (result != BP_RESULT_OK) 1961 return result; 1962 1963 /* Sort voltage table from low to high*/ 1964 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 1965 for (j = i; j > 0; --j) { 1966 if (info->disp_clk_voltage[j].max_supported_clk < 1967 info->disp_clk_voltage[j-1].max_supported_clk 1968 ) { 1969 /* swap j and j - 1*/ 1970 swap(info->disp_clk_voltage[j - 1], 1971 info->disp_clk_voltage[j]); 1972 } 1973 } 1974 } 1975 1976 return result; 1977 } 1978 1979 static enum bp_result bios_parser_get_vram_info( 1980 struct dc_bios *dcb, 1981 struct dc_vram_info *info) 1982 { 1983 struct bios_parser *bp = BP_FROM_DCB(dcb); 1984 enum bp_result result = BP_RESULT_BADBIOSTABLE; 1985 struct atom_common_table_header *header; 1986 struct atom_data_revision revision; 1987 1988 if (info && DATA_TABLES(vram_info)) { 1989 header = GET_IMAGE(struct atom_common_table_header, 1990 DATA_TABLES(vram_info)); 1991 1992 get_atom_data_table_revision(header, &revision); 1993 1994 switch (revision.major) { 1995 case 2: 1996 switch (revision.minor) { 1997 case 3: 1998 result = get_vram_info_v23(bp, info); 1999 break; 2000 case 4: 2001 result = get_vram_info_v24(bp, info); 2002 break; 2003 case 5: 2004 result = get_vram_info_v25(bp, info); 2005 break; 2006 default: 2007 break; 2008 } 2009 break; 2010 2011 default: 2012 return result; 2013 } 2014 2015 } 2016 return result; 2017 } 2018 2019 static struct integrated_info *bios_parser_create_integrated_info( 2020 struct dc_bios *dcb) 2021 { 2022 struct bios_parser *bp = BP_FROM_DCB(dcb); 2023 struct integrated_info *info = NULL; 2024 2025 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); 2026 2027 if (info == NULL) { 2028 ASSERT_CRITICAL(0); 2029 return NULL; 2030 } 2031 2032 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2033 return info; 2034 2035 kfree(info); 2036 2037 return NULL; 2038 } 2039 2040 static enum bp_result update_slot_layout_info( 2041 struct dc_bios *dcb, 2042 unsigned int i, 2043 struct slot_layout_info *slot_layout_info) 2044 { 2045 unsigned int record_offset; 2046 unsigned int j; 2047 struct atom_display_object_path_v2 *object; 2048 struct atom_bracket_layout_record *record; 2049 struct atom_common_record_header *record_header; 2050 enum bp_result result; 2051 struct bios_parser *bp; 2052 struct object_info_table *tbl; 2053 struct display_object_info_table_v1_4 *v1_4; 2054 2055 record = NULL; 2056 record_header = NULL; 2057 result = BP_RESULT_NORECORD; 2058 2059 bp = BP_FROM_DCB(dcb); 2060 tbl = &bp->object_info_tbl; 2061 v1_4 = tbl->v1_4; 2062 2063 object = &v1_4->display_path[i]; 2064 record_offset = (unsigned int) 2065 (object->disp_recordoffset) + 2066 (unsigned int)(bp->object_info_tbl_offset); 2067 2068 for (;;) { 2069 2070 record_header = (struct atom_common_record_header *) 2071 GET_IMAGE(struct atom_common_record_header, 2072 record_offset); 2073 if (record_header == NULL) { 2074 result = BP_RESULT_BADBIOSTABLE; 2075 break; 2076 } 2077 2078 /* the end of the list */ 2079 if (record_header->record_type == 0xff || 2080 record_header->record_size == 0) { 2081 break; 2082 } 2083 2084 if (record_header->record_type == 2085 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2086 sizeof(struct atom_bracket_layout_record) 2087 <= record_header->record_size) { 2088 record = (struct atom_bracket_layout_record *) 2089 (record_header); 2090 result = BP_RESULT_OK; 2091 break; 2092 } 2093 2094 record_offset += record_header->record_size; 2095 } 2096 2097 /* return if the record not found */ 2098 if (result != BP_RESULT_OK) 2099 return result; 2100 2101 /* get slot sizes */ 2102 slot_layout_info->length = record->bracketlen; 2103 slot_layout_info->width = record->bracketwidth; 2104 2105 /* get info for each connector in the slot */ 2106 slot_layout_info->num_of_connectors = record->conn_num; 2107 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2108 slot_layout_info->connectors[j].connector_type = 2109 (enum connector_layout_type) 2110 (record->conn_info[j].connector_type); 2111 switch (record->conn_info[j].connector_type) { 2112 case CONNECTOR_TYPE_DVI_D: 2113 slot_layout_info->connectors[j].connector_type = 2114 CONNECTOR_LAYOUT_TYPE_DVI_D; 2115 slot_layout_info->connectors[j].length = 2116 CONNECTOR_SIZE_DVI; 2117 break; 2118 2119 case CONNECTOR_TYPE_HDMI: 2120 slot_layout_info->connectors[j].connector_type = 2121 CONNECTOR_LAYOUT_TYPE_HDMI; 2122 slot_layout_info->connectors[j].length = 2123 CONNECTOR_SIZE_HDMI; 2124 break; 2125 2126 case CONNECTOR_TYPE_DISPLAY_PORT: 2127 slot_layout_info->connectors[j].connector_type = 2128 CONNECTOR_LAYOUT_TYPE_DP; 2129 slot_layout_info->connectors[j].length = 2130 CONNECTOR_SIZE_DP; 2131 break; 2132 2133 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2134 slot_layout_info->connectors[j].connector_type = 2135 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2136 slot_layout_info->connectors[j].length = 2137 CONNECTOR_SIZE_MINI_DP; 2138 break; 2139 2140 default: 2141 slot_layout_info->connectors[j].connector_type = 2142 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2143 slot_layout_info->connectors[j].length = 2144 CONNECTOR_SIZE_UNKNOWN; 2145 } 2146 2147 slot_layout_info->connectors[j].position = 2148 record->conn_info[j].position; 2149 slot_layout_info->connectors[j].connector_id = 2150 object_id_from_bios_object_id( 2151 record->conn_info[j].connectorobjid); 2152 } 2153 return result; 2154 } 2155 2156 2157 static enum bp_result get_bracket_layout_record( 2158 struct dc_bios *dcb, 2159 unsigned int bracket_layout_id, 2160 struct slot_layout_info *slot_layout_info) 2161 { 2162 unsigned int i; 2163 struct bios_parser *bp = BP_FROM_DCB(dcb); 2164 enum bp_result result; 2165 struct object_info_table *tbl; 2166 struct display_object_info_table_v1_4 *v1_4; 2167 2168 if (slot_layout_info == NULL) { 2169 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2170 return BP_RESULT_BADINPUT; 2171 } 2172 tbl = &bp->object_info_tbl; 2173 v1_4 = tbl->v1_4; 2174 2175 result = BP_RESULT_NORECORD; 2176 for (i = 0; i < v1_4->number_of_path; ++i) { 2177 2178 if (bracket_layout_id == 2179 v1_4->display_path[i].display_objid) { 2180 result = update_slot_layout_info(dcb, i, 2181 slot_layout_info); 2182 break; 2183 } 2184 } 2185 return result; 2186 } 2187 2188 static enum bp_result bios_get_board_layout_info( 2189 struct dc_bios *dcb, 2190 struct board_layout_info *board_layout_info) 2191 { 2192 unsigned int i; 2193 enum bp_result record_result; 2194 2195 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2196 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2197 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2198 0, 0 2199 }; 2200 2201 if (board_layout_info == NULL) { 2202 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2203 return BP_RESULT_BADINPUT; 2204 } 2205 2206 board_layout_info->num_of_slots = 0; 2207 2208 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2209 record_result = get_bracket_layout_record(dcb, 2210 slot_index_to_vbios_id[i], 2211 &board_layout_info->slots[i]); 2212 2213 if (record_result == BP_RESULT_NORECORD && i > 0) 2214 break; /* no more slots present in bios */ 2215 else if (record_result != BP_RESULT_OK) 2216 return record_result; /* fail */ 2217 2218 ++board_layout_info->num_of_slots; 2219 } 2220 2221 /* all data is valid */ 2222 board_layout_info->is_number_of_slots_valid = 1; 2223 board_layout_info->is_slots_size_valid = 1; 2224 board_layout_info->is_connector_offsets_valid = 1; 2225 board_layout_info->is_connector_lengths_valid = 1; 2226 2227 return BP_RESULT_OK; 2228 } 2229 2230 2231 static uint16_t bios_parser_pack_data_tables( 2232 struct dc_bios *dcb, 2233 void *dst) 2234 { 2235 #ifdef PACK_BIOS_DATA 2236 struct bios_parser *bp = BP_FROM_DCB(dcb); 2237 struct atom_rom_header_v2_2 *rom_header = NULL; 2238 struct atom_rom_header_v2_2 *packed_rom_header = NULL; 2239 struct atom_common_table_header *data_tbl_header = NULL; 2240 struct atom_master_list_of_data_tables_v2_1 *data_tbl_list = NULL; 2241 struct atom_master_data_table_v2_1 *packed_master_data_tbl = NULL; 2242 struct atom_data_revision tbl_rev = {0}; 2243 uint16_t *rom_header_offset = NULL; 2244 const uint8_t *bios = bp->base.bios; 2245 uint8_t *bios_dst = (uint8_t *)dst; 2246 uint16_t packed_rom_header_offset; 2247 uint16_t packed_masterdatatable_offset; 2248 uint16_t packed_data_tbl_offset; 2249 uint16_t data_tbl_offset; 2250 unsigned int i; 2251 2252 rom_header_offset = 2253 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2254 2255 if (!rom_header_offset) 2256 return 0; 2257 2258 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2259 2260 if (!rom_header) 2261 return 0; 2262 2263 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2264 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2265 return 0; 2266 2267 get_atom_data_table_revision(&bp->master_data_tbl->table_header, &tbl_rev); 2268 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 1)) 2269 return 0; 2270 2271 packed_rom_header_offset = 2272 OFFSET_TO_ATOM_ROM_HEADER_POINTER + sizeof(*rom_header_offset); 2273 2274 packed_masterdatatable_offset = 2275 packed_rom_header_offset + rom_header->table_header.structuresize; 2276 2277 packed_data_tbl_offset = 2278 packed_masterdatatable_offset + 2279 bp->master_data_tbl->table_header.structuresize; 2280 2281 packed_rom_header = 2282 (struct atom_rom_header_v2_2 *)(bios_dst + packed_rom_header_offset); 2283 2284 packed_master_data_tbl = 2285 (struct atom_master_data_table_v2_1 *)(bios_dst + 2286 packed_masterdatatable_offset); 2287 2288 memcpy(bios_dst, bios, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2289 2290 *((uint16_t *)(bios_dst + OFFSET_TO_ATOM_ROM_HEADER_POINTER)) = 2291 packed_rom_header_offset; 2292 2293 memcpy(bios_dst + packed_rom_header_offset, rom_header, 2294 rom_header->table_header.structuresize); 2295 2296 packed_rom_header->masterdatatable_offset = packed_masterdatatable_offset; 2297 2298 memcpy(&packed_master_data_tbl->table_header, 2299 &bp->master_data_tbl->table_header, 2300 sizeof(bp->master_data_tbl->table_header)); 2301 2302 data_tbl_list = &bp->master_data_tbl->listOfdatatables; 2303 2304 /* Each data table offset in data table list is 2 bytes, 2305 * we can use that to iterate through listOfdatatables 2306 * without knowing the name of each member. 2307 */ 2308 for (i = 0; i < sizeof(*data_tbl_list)/sizeof(uint16_t); i++) { 2309 data_tbl_offset = *((uint16_t *)data_tbl_list + i); 2310 2311 if (data_tbl_offset) { 2312 data_tbl_header = 2313 (struct atom_common_table_header *)(bios + data_tbl_offset); 2314 2315 memcpy(bios_dst + packed_data_tbl_offset, data_tbl_header, 2316 data_tbl_header->structuresize); 2317 2318 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 2319 packed_data_tbl_offset; 2320 2321 packed_data_tbl_offset += data_tbl_header->structuresize; 2322 } else { 2323 *((uint16_t *)&packed_master_data_tbl->listOfdatatables + i) = 0; 2324 } 2325 } 2326 return packed_data_tbl_offset; 2327 #endif 2328 // TODO: There is data bytes alignment issue, disable it for now. 2329 return 0; 2330 } 2331 2332 static struct atom_dc_golden_table_v1 *bios_get_golden_table( 2333 struct bios_parser *bp, 2334 uint32_t rev_major, 2335 uint32_t rev_minor, 2336 uint16_t *dc_golden_table_ver) 2337 { 2338 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL; 2339 uint32_t dc_golden_offset = 0; 2340 *dc_golden_table_ver = 0; 2341 2342 if (!DATA_TABLES(dce_info)) 2343 return NULL; 2344 2345 /* ver.4.4 or higher */ 2346 switch (rev_major) { 2347 case 4: 2348 switch (rev_minor) { 2349 case 4: 2350 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4, 2351 DATA_TABLES(dce_info)); 2352 if (!disp_cntl_tbl_4_4) 2353 return NULL; 2354 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset; 2355 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver; 2356 break; 2357 } 2358 break; 2359 } 2360 2361 if (!dc_golden_offset) 2362 return NULL; 2363 2364 if (*dc_golden_table_ver != 1) 2365 return NULL; 2366 2367 return GET_IMAGE(struct atom_dc_golden_table_v1, 2368 dc_golden_offset); 2369 } 2370 2371 static enum bp_result bios_get_atom_dc_golden_table( 2372 struct dc_bios *dcb) 2373 { 2374 struct bios_parser *bp = BP_FROM_DCB(dcb); 2375 enum bp_result result = BP_RESULT_OK; 2376 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL; 2377 struct atom_common_table_header *header; 2378 struct atom_data_revision tbl_revision; 2379 uint16_t dc_golden_table_ver = 0; 2380 2381 header = GET_IMAGE(struct atom_common_table_header, 2382 DATA_TABLES(dce_info)); 2383 if (!header) 2384 return BP_RESULT_UNSUPPORTED; 2385 2386 get_atom_data_table_revision(header, &tbl_revision); 2387 2388 atom_dc_golden_table = bios_get_golden_table(bp, 2389 tbl_revision.major, 2390 tbl_revision.minor, 2391 &dc_golden_table_ver); 2392 2393 if (!atom_dc_golden_table) 2394 return BP_RESULT_UNSUPPORTED; 2395 2396 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver; 2397 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val; 2398 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val; 2399 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val; 2400 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val; 2401 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val; 2402 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val; 2403 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val; 2404 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val; 2405 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val; 2406 2407 return result; 2408 } 2409 2410 2411 static const struct dc_vbios_funcs vbios_funcs = { 2412 .get_connectors_number = bios_parser_get_connectors_number, 2413 2414 .get_connector_id = bios_parser_get_connector_id, 2415 2416 .get_src_obj = bios_parser_get_src_obj, 2417 2418 .get_i2c_info = bios_parser_get_i2c_info, 2419 2420 .get_hpd_info = bios_parser_get_hpd_info, 2421 2422 .get_device_tag = bios_parser_get_device_tag, 2423 2424 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2425 2426 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2427 2428 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2429 2430 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2431 2432 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2433 2434 .is_device_id_supported = bios_parser_is_device_id_supported, 2435 2436 .is_accelerated_mode = bios_parser_is_accelerated_mode, 2437 2438 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2439 2440 2441 /* COMMANDS */ 2442 .encoder_control = bios_parser_encoder_control, 2443 2444 .transmitter_control = bios_parser_transmitter_control, 2445 2446 .enable_crtc = bios_parser_enable_crtc, 2447 2448 .set_pixel_clock = bios_parser_set_pixel_clock, 2449 2450 .set_dce_clock = bios_parser_set_dce_clock, 2451 2452 .program_crtc_timing = bios_parser_program_crtc_timing, 2453 2454 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2455 2456 .bios_parser_destroy = firmware_parser_destroy, 2457 2458 .get_board_layout_info = bios_get_board_layout_info, 2459 .pack_data_tables = bios_parser_pack_data_tables, 2460 2461 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table, 2462 2463 .enable_lvtma_control = bios_parser_enable_lvtma_control, 2464 2465 .get_soc_bb_info = bios_parser_get_soc_bb_info, 2466 }; 2467 2468 static bool bios_parser2_construct( 2469 struct bios_parser *bp, 2470 struct bp_init_data *init, 2471 enum dce_version dce_version) 2472 { 2473 uint16_t *rom_header_offset = NULL; 2474 struct atom_rom_header_v2_2 *rom_header = NULL; 2475 struct display_object_info_table_v1_4 *object_info_tbl; 2476 struct atom_data_revision tbl_rev = {0}; 2477 2478 if (!init) 2479 return false; 2480 2481 if (!init->bios) 2482 return false; 2483 2484 bp->base.funcs = &vbios_funcs; 2485 bp->base.bios = init->bios; 2486 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT; 2487 2488 bp->base.ctx = init->ctx; 2489 2490 bp->base.bios_local_image = NULL; 2491 2492 rom_header_offset = 2493 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER); 2494 2495 if (!rom_header_offset) 2496 return false; 2497 2498 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset); 2499 2500 if (!rom_header) 2501 return false; 2502 2503 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev); 2504 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2)) 2505 return false; 2506 2507 bp->master_data_tbl = 2508 GET_IMAGE(struct atom_master_data_table_v2_1, 2509 rom_header->masterdatatable_offset); 2510 2511 if (!bp->master_data_tbl) 2512 return false; 2513 2514 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo); 2515 2516 if (!bp->object_info_tbl_offset) 2517 return false; 2518 2519 object_info_tbl = 2520 GET_IMAGE(struct display_object_info_table_v1_4, 2521 bp->object_info_tbl_offset); 2522 2523 if (!object_info_tbl) 2524 return false; 2525 2526 get_atom_data_table_revision(&object_info_tbl->table_header, 2527 &bp->object_info_tbl.revision); 2528 2529 if (bp->object_info_tbl.revision.major == 1 2530 && bp->object_info_tbl.revision.minor >= 4) { 2531 struct display_object_info_table_v1_4 *tbl_v1_4; 2532 2533 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4, 2534 bp->object_info_tbl_offset); 2535 if (!tbl_v1_4) 2536 return false; 2537 2538 bp->object_info_tbl.v1_4 = tbl_v1_4; 2539 } else 2540 return false; 2541 2542 dal_firmware_parser_init_cmd_tbl(bp); 2543 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version); 2544 2545 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 2546 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 2547 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info); 2548 2549 return true; 2550 } 2551 2552 struct dc_bios *firmware_parser_create( 2553 struct bp_init_data *init, 2554 enum dce_version dce_version) 2555 { 2556 struct bios_parser *bp = NULL; 2557 2558 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); 2559 if (!bp) 2560 return NULL; 2561 2562 if (bios_parser2_construct(bp, init, dce_version)) 2563 return &bp->base; 2564 2565 kfree(bp); 2566 return NULL; 2567 } 2568 2569 2570