1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #undef TRACE_SYSTEM
27 #define TRACE_SYSTEM amdgpu_dm
28 
29 #if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
30 #define _AMDGPU_DM_TRACE_H_
31 
32 #include <linux/tracepoint.h>
33 #include <drm/drm_connector.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_plane.h>
36 #include <drm/drm_fourcc.h>
37 #include <drm/drm_encoder.h>
38 #include <drm/drm_atomic.h>
39 
40 #include "dc/inc/core_types.h"
41 
42 DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
43 		    TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
44 		    TP_ARGS(count, reg, value),
45 
46 		    TP_STRUCT__entry(
47 				     __field(uint32_t, reg)
48 				     __field(uint32_t, value)
49 		    ),
50 
51 		    TP_fast_assign(
52 				   __entry->reg = reg;
53 				   __entry->value = value;
54 				   *count = *count + 1;
55 		    ),
56 
57 		    TP_printk("reg=0x%08lx, value=0x%08lx",
58 			      (unsigned long)__entry->reg,
59 			      (unsigned long)__entry->value)
60 );
61 
62 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
63 	     TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
64 	     TP_ARGS(count, reg, value));
65 
66 DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
67 	     TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
68 	     TP_ARGS(count, reg, value));
69 
70 TRACE_EVENT(amdgpu_dc_performance,
71 	TP_PROTO(unsigned long read_count, unsigned long write_count,
72 		unsigned long *last_read, unsigned long *last_write,
73 		const char *func, unsigned int line),
74 	TP_ARGS(read_count, write_count, last_read, last_write, func, line),
75 	TP_STRUCT__entry(
76 			__field(uint32_t, reads)
77 			__field(uint32_t, writes)
78 			__field(uint32_t, read_delta)
79 			__field(uint32_t, write_delta)
80 			__string(func, func)
81 			__field(uint32_t, line)
82 			),
83 	TP_fast_assign(
84 			__entry->reads = read_count;
85 			__entry->writes = write_count;
86 			__entry->read_delta = read_count - *last_read;
87 			__entry->write_delta = write_count - *last_write;
88 			__assign_str(func, func);
89 			__entry->line = line;
90 			*last_read = read_count;
91 			*last_write = write_count;
92 			),
93 	TP_printk("%s:%d reads=%08ld (%08ld total), writes=%08ld (%08ld total)",
94 			__get_str(func), __entry->line,
95 			(unsigned long)__entry->read_delta,
96 			(unsigned long)__entry->reads,
97 			(unsigned long)__entry->write_delta,
98 			(unsigned long)__entry->writes)
99 );
100 
101 TRACE_EVENT(amdgpu_dm_connector_atomic_check,
102 	    TP_PROTO(const struct drm_connector_state *state),
103 	    TP_ARGS(state),
104 
105 	    TP_STRUCT__entry(
106 			     __field(uint32_t, conn_id)
107 			     __field(const struct drm_connector_state *, conn_state)
108 			     __field(const struct drm_atomic_state *, state)
109 			     __field(const struct drm_crtc_commit *, commit)
110 			     __field(uint32_t, crtc_id)
111 			     __field(uint32_t, best_encoder_id)
112 			     __field(enum drm_link_status, link_status)
113 			     __field(bool, self_refresh_aware)
114 			     __field(enum hdmi_picture_aspect, picture_aspect_ratio)
115 			     __field(unsigned int, content_type)
116 			     __field(unsigned int, hdcp_content_type)
117 			     __field(unsigned int, content_protection)
118 			     __field(unsigned int, scaling_mode)
119 			     __field(u32, colorspace)
120 			     __field(u8, max_requested_bpc)
121 			     __field(u8, max_bpc)
122 	    ),
123 
124 	    TP_fast_assign(
125 			   __entry->conn_id = state->connector->base.id;
126 			   __entry->conn_state = state;
127 			   __entry->state = state->state;
128 			   __entry->commit = state->commit;
129 			   __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
130 			   __entry->best_encoder_id = state->best_encoder ?
131 						      state->best_encoder->base.id : 0;
132 			   __entry->link_status = state->link_status;
133 			   __entry->self_refresh_aware = state->self_refresh_aware;
134 			   __entry->picture_aspect_ratio = state->picture_aspect_ratio;
135 			   __entry->content_type = state->content_type;
136 			   __entry->hdcp_content_type = state->hdcp_content_type;
137 			   __entry->content_protection = state->content_protection;
138 			   __entry->scaling_mode = state->scaling_mode;
139 			   __entry->colorspace = state->colorspace;
140 			   __entry->max_requested_bpc = state->max_requested_bpc;
141 			   __entry->max_bpc = state->max_bpc;
142 	    ),
143 
144 	    TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "
145 		      "best_encoder_id=%u link_status=%d self_refresh_aware=%d "
146 		      "picture_aspect_ratio=%d content_type=%u "
147 		      "hdcp_content_type=%u content_protection=%u scaling_mode=%u "
148 		      "colorspace=%u max_requested_bpc=%u max_bpc=%u",
149 		      __entry->conn_id, __entry->conn_state, __entry->state,
150 		      __entry->commit, __entry->crtc_id, __entry->best_encoder_id,
151 		      __entry->link_status, __entry->self_refresh_aware,
152 		      __entry->picture_aspect_ratio, __entry->content_type,
153 		      __entry->hdcp_content_type, __entry->content_protection,
154 		      __entry->scaling_mode, __entry->colorspace,
155 		      __entry->max_requested_bpc, __entry->max_bpc)
156 );
157 
158 TRACE_EVENT(amdgpu_dm_crtc_atomic_check,
159 	    TP_PROTO(const struct drm_crtc_state *state),
160 	    TP_ARGS(state),
161 
162 	    TP_STRUCT__entry(
163 			     __field(const struct drm_atomic_state *, state)
164 			     __field(const struct drm_crtc_state *, crtc_state)
165 			     __field(const struct drm_crtc_commit *, commit)
166 			     __field(uint32_t, crtc_id)
167 			     __field(bool, enable)
168 			     __field(bool, active)
169 			     __field(bool, planes_changed)
170 			     __field(bool, mode_changed)
171 			     __field(bool, active_changed)
172 			     __field(bool, connectors_changed)
173 			     __field(bool, zpos_changed)
174 			     __field(bool, color_mgmt_changed)
175 			     __field(bool, no_vblank)
176 			     __field(bool, async_flip)
177 			     __field(bool, vrr_enabled)
178 			     __field(bool, self_refresh_active)
179 			     __field(u32, plane_mask)
180 			     __field(u32, connector_mask)
181 			     __field(u32, encoder_mask)
182 	    ),
183 
184 	    TP_fast_assign(
185 			   __entry->state = state->state;
186 			   __entry->crtc_state = state;
187 			   __entry->crtc_id = state->crtc->base.id;
188 			   __entry->commit = state->commit;
189 			   __entry->enable = state->enable;
190 			   __entry->active = state->active;
191 			   __entry->planes_changed = state->planes_changed;
192 			   __entry->mode_changed = state->mode_changed;
193 			   __entry->active_changed = state->active_changed;
194 			   __entry->connectors_changed = state->connectors_changed;
195 			   __entry->zpos_changed = state->zpos_changed;
196 			   __entry->color_mgmt_changed = state->color_mgmt_changed;
197 			   __entry->no_vblank = state->no_vblank;
198 			   __entry->async_flip = state->async_flip;
199 			   __entry->vrr_enabled = state->vrr_enabled;
200 			   __entry->self_refresh_active = state->self_refresh_active;
201 			   __entry->plane_mask = state->plane_mask;
202 			   __entry->connector_mask = state->connector_mask;
203 			   __entry->encoder_mask = state->encoder_mask;
204 	    ),
205 
206 	    TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("
207 		      "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "
208 		      "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "
209 		      "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "
210 		      "enc=%x)",
211 		      __entry->crtc_id, __entry->crtc_state, __entry->state,
212 		      __entry->commit, __entry->planes_changed,
213 		      __entry->mode_changed, __entry->active_changed,
214 		      __entry->connectors_changed, __entry->zpos_changed,
215 		      __entry->color_mgmt_changed, __entry->enable, __entry->active,
216 		      __entry->async_flip, __entry->vrr_enabled,
217 		      __entry->self_refresh_active, __entry->no_vblank,
218 		      __entry->plane_mask, __entry->connector_mask,
219 		      __entry->encoder_mask)
220 );
221 
222 DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,
223 	    TP_PROTO(const struct drm_plane_state *state),
224 	    TP_ARGS(state),
225 	    TP_STRUCT__entry(
226 			     __field(uint32_t, plane_id)
227 			     __field(enum drm_plane_type, plane_type)
228 			     __field(const struct drm_plane_state *, plane_state)
229 			     __field(const struct drm_atomic_state *, state)
230 			     __field(uint32_t, crtc_id)
231 			     __field(uint32_t, fb_id)
232 			     __field(uint32_t, fb_format)
233 			     __field(uint8_t, fb_planes)
234 			     __field(uint64_t, fb_modifier)
235 			     __field(const struct dma_fence *, fence)
236 			     __field(int32_t, crtc_x)
237 			     __field(int32_t, crtc_y)
238 			     __field(uint32_t, crtc_w)
239 			     __field(uint32_t, crtc_h)
240 			     __field(uint32_t, src_x)
241 			     __field(uint32_t, src_y)
242 			     __field(uint32_t, src_w)
243 			     __field(uint32_t, src_h)
244 			     __field(u32, alpha)
245 			     __field(uint32_t, pixel_blend_mode)
246 			     __field(unsigned int, rotation)
247 			     __field(unsigned int, zpos)
248 			     __field(unsigned int, normalized_zpos)
249 			     __field(enum drm_color_encoding, color_encoding)
250 			     __field(enum drm_color_range, color_range)
251 			     __field(bool, visible)
252 	    ),
253 
254 	    TP_fast_assign(
255 			   __entry->plane_id = state->plane->base.id;
256 			   __entry->plane_type = state->plane->type;
257 			   __entry->plane_state = state;
258 			   __entry->state = state->state;
259 			   __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
260 			   __entry->fb_id = state->fb ? state->fb->base.id : 0;
261 			   __entry->fb_format = state->fb ? state->fb->format->format : 0;
262 			   __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;
263 			   __entry->fb_modifier = state->fb ? state->fb->modifier : 0;
264 			   __entry->fence = state->fence;
265 			   __entry->crtc_x = state->crtc_x;
266 			   __entry->crtc_y = state->crtc_y;
267 			   __entry->crtc_w = state->crtc_w;
268 			   __entry->crtc_h = state->crtc_h;
269 			   __entry->src_x = state->src_x >> 16;
270 			   __entry->src_y = state->src_y >> 16;
271 			   __entry->src_w = state->src_w >> 16;
272 			   __entry->src_h = state->src_h >> 16;
273 			   __entry->alpha = state->alpha;
274 			   __entry->pixel_blend_mode = state->pixel_blend_mode;
275 			   __entry->rotation = state->rotation;
276 			   __entry->zpos = state->zpos;
277 			   __entry->normalized_zpos = state->normalized_zpos;
278 			   __entry->color_encoding = state->color_encoding;
279 			   __entry->color_range = state->color_range;
280 			   __entry->visible = state->visible;
281 	    ),
282 
283 	    TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "
284 		      "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "
285 		      "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "
286 		      "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "
287 		      "pixel_blend_mode=%u rotation=%u zpos=%u "
288 		      "normalized_zpos=%u color_encoding=%d color_range=%d "
289 		      "visible=%d",
290 		      __entry->plane_id, __entry->plane_type, __entry->plane_state,
291 		      __entry->state, __entry->crtc_id, __entry->fb_id,
292 		      (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',
293 		      ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',
294 		      ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',
295 		      ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',
296 		      __entry->fb_planes,
297 		      __entry->fb_modifier, __entry->fence, __entry->crtc_x,
298 		      __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
299 		      __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,
300 		      __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,
301 		      __entry->zpos, __entry->normalized_zpos,
302 		      __entry->color_encoding, __entry->color_range,
303 		      __entry->visible)
304 );
305 
306 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,
307 	     TP_PROTO(const struct drm_plane_state *state),
308 	     TP_ARGS(state));
309 
310 DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,
311 	     TP_PROTO(const struct drm_plane_state *state),
312 	     TP_ARGS(state));
313 
314 TRACE_EVENT(amdgpu_dm_atomic_state_template,
315 	    TP_PROTO(const struct drm_atomic_state *state),
316 	    TP_ARGS(state),
317 
318 	    TP_STRUCT__entry(
319 			     __field(const struct drm_atomic_state *, state)
320 			     __field(bool, allow_modeset)
321 			     __field(bool, legacy_cursor_update)
322 			     __field(bool, async_update)
323 			     __field(bool, duplicated)
324 			     __field(int, num_connector)
325 			     __field(int, num_private_objs)
326 	    ),
327 
328 	    TP_fast_assign(
329 			   __entry->state = state;
330 			   __entry->allow_modeset = state->allow_modeset;
331 			   __entry->legacy_cursor_update = state->legacy_cursor_update;
332 			   __entry->async_update = state->async_update;
333 			   __entry->duplicated = state->duplicated;
334 			   __entry->num_connector = state->num_connector;
335 			   __entry->num_private_objs = state->num_private_objs;
336 	    ),
337 
338 	    TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "
339 		      "async_update=%d duplicated=%d num_connector=%d "
340 		      "num_private_objs=%d",
341 		      __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,
342 		      __entry->async_update, __entry->duplicated, __entry->num_connector,
343 		      __entry->num_private_objs)
344 );
345 
346 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,
347 	     TP_PROTO(const struct drm_atomic_state *state),
348 	     TP_ARGS(state));
349 
350 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,
351 	     TP_PROTO(const struct drm_atomic_state *state),
352 	     TP_ARGS(state));
353 
354 DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,
355 	     TP_PROTO(const struct drm_atomic_state *state),
356 	     TP_ARGS(state));
357 
358 TRACE_EVENT(amdgpu_dm_atomic_check_finish,
359 	    TP_PROTO(const struct drm_atomic_state *state, int res),
360 	    TP_ARGS(state, res),
361 
362 	    TP_STRUCT__entry(
363 			     __field(const struct drm_atomic_state *, state)
364 			     __field(int, res)
365 			     __field(bool, async_update)
366 			     __field(bool, allow_modeset)
367 	    ),
368 
369 	    TP_fast_assign(
370 			   __entry->state = state;
371 			   __entry->res = res;
372 			   __entry->async_update = state->async_update;
373 			   __entry->allow_modeset = state->allow_modeset;
374 	    ),
375 
376 	    TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",
377 		      __entry->state, __entry->res,
378 		      __entry->async_update, __entry->allow_modeset)
379 );
380 
381 TRACE_EVENT(amdgpu_dm_dc_pipe_state,
382 	    TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,
383 		     const struct dc_stream_state *stream,
384 		     const struct plane_resource *plane_res,
385 		     int update_flags),
386 	    TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
387 
388 	    TP_STRUCT__entry(
389 			     __field(int, pipe_idx)
390 			     __field(const void *, stream)
391 			     __field(int, stream_w)
392 			     __field(int, stream_h)
393 			     __field(int, dst_x)
394 			     __field(int, dst_y)
395 			     __field(int, dst_w)
396 			     __field(int, dst_h)
397 			     __field(int, src_x)
398 			     __field(int, src_y)
399 			     __field(int, src_w)
400 			     __field(int, src_h)
401 			     __field(int, clip_x)
402 			     __field(int, clip_y)
403 			     __field(int, clip_w)
404 			     __field(int, clip_h)
405 			     __field(int, recout_x)
406 			     __field(int, recout_y)
407 			     __field(int, recout_w)
408 			     __field(int, recout_h)
409 			     __field(int, viewport_x)
410 			     __field(int, viewport_y)
411 			     __field(int, viewport_w)
412 			     __field(int, viewport_h)
413 			     __field(int, flip_immediate)
414 			     __field(int, surface_pitch)
415 			     __field(int, format)
416 			     __field(int, swizzle)
417 			     __field(unsigned int, update_flags)
418 	),
419 
420 	TP_fast_assign(
421 		       __entry->pipe_idx = pipe_idx;
422 		       __entry->stream = stream;
423 		       __entry->stream_w = stream->timing.h_addressable;
424 		       __entry->stream_h = stream->timing.v_addressable;
425 		       __entry->dst_x = plane_state->dst_rect.x;
426 		       __entry->dst_y = plane_state->dst_rect.y;
427 		       __entry->dst_w = plane_state->dst_rect.width;
428 		       __entry->dst_h = plane_state->dst_rect.height;
429 		       __entry->src_x = plane_state->src_rect.x;
430 		       __entry->src_y = plane_state->src_rect.y;
431 		       __entry->src_w = plane_state->src_rect.width;
432 		       __entry->src_h = plane_state->src_rect.height;
433 		       __entry->clip_x = plane_state->clip_rect.x;
434 		       __entry->clip_y = plane_state->clip_rect.y;
435 		       __entry->clip_w = plane_state->clip_rect.width;
436 		       __entry->clip_h = plane_state->clip_rect.height;
437 		       __entry->recout_x = plane_res->scl_data.recout.x;
438 		       __entry->recout_y = plane_res->scl_data.recout.y;
439 		       __entry->recout_w = plane_res->scl_data.recout.width;
440 		       __entry->recout_h = plane_res->scl_data.recout.height;
441 		       __entry->viewport_x = plane_res->scl_data.viewport.x;
442 		       __entry->viewport_y = plane_res->scl_data.viewport.y;
443 		       __entry->viewport_w = plane_res->scl_data.viewport.width;
444 		       __entry->viewport_h = plane_res->scl_data.viewport.height;
445 		       __entry->flip_immediate = plane_state->flip_immediate;
446 		       __entry->surface_pitch = plane_state->plane_size.surface_pitch;
447 		       __entry->format = plane_state->format;
448 		       __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
449 		       __entry->update_flags = update_flags;
450 	),
451 	TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "
452 		  "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "
453 		  "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "
454 		  "format=%d swizzle=%d update_flags=%x",
455 		  __entry->pipe_idx,
456 		  __entry->stream,
457 		  __entry->stream_w,
458 		  __entry->stream_h,
459 		  __entry->dst_x,
460 		  __entry->dst_y,
461 		  __entry->dst_w,
462 		  __entry->dst_h,
463 		  __entry->src_x,
464 		  __entry->src_y,
465 		  __entry->src_w,
466 		  __entry->src_h,
467 		  __entry->clip_x,
468 		  __entry->clip_y,
469 		  __entry->clip_w,
470 		  __entry->clip_h,
471 		  __entry->recout_x,
472 		  __entry->recout_y,
473 		  __entry->recout_w,
474 		  __entry->recout_h,
475 		  __entry->viewport_x,
476 		  __entry->viewport_y,
477 		  __entry->viewport_w,
478 		  __entry->viewport_h,
479 		  __entry->flip_immediate,
480 		  __entry->surface_pitch,
481 		  __entry->format,
482 		  __entry->swizzle,
483 		  __entry->update_flags
484 	)
485 );
486 
487 TRACE_EVENT(amdgpu_dm_dc_clocks_state,
488 	    TP_PROTO(const struct dc_clocks *clk),
489 	    TP_ARGS(clk),
490 
491 	    TP_STRUCT__entry(
492 			     __field(int, dispclk_khz)
493 			     __field(int, dppclk_khz)
494 			     __field(int, disp_dpp_voltage_level_khz)
495 			     __field(int, dcfclk_khz)
496 			     __field(int, socclk_khz)
497 			     __field(int, dcfclk_deep_sleep_khz)
498 			     __field(int, fclk_khz)
499 			     __field(int, phyclk_khz)
500 			     __field(int, dramclk_khz)
501 			     __field(int, p_state_change_support)
502 			     __field(int, prev_p_state_change_support)
503 			     __field(int, pwr_state)
504 			     __field(int, dtm_level)
505 			     __field(int, max_supported_dppclk_khz)
506 			     __field(int, max_supported_dispclk_khz)
507 			     __field(int, bw_dppclk_khz)
508 			     __field(int, bw_dispclk_khz)
509 	    ),
510 	    TP_fast_assign(
511 			   __entry->dispclk_khz = clk->dispclk_khz;
512 			   __entry->dppclk_khz = clk->dppclk_khz;
513 			   __entry->dcfclk_khz = clk->dcfclk_khz;
514 			   __entry->socclk_khz = clk->socclk_khz;
515 			   __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;
516 			   __entry->fclk_khz = clk->fclk_khz;
517 			   __entry->phyclk_khz = clk->phyclk_khz;
518 			   __entry->dramclk_khz = clk->dramclk_khz;
519 			   __entry->p_state_change_support = clk->p_state_change_support;
520 			   __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
521 			   __entry->pwr_state = clk->pwr_state;
522 			   __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
523 			   __entry->dtm_level = clk->dtm_level;
524 			   __entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;
525 			   __entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;
526 			   __entry->bw_dppclk_khz = clk->bw_dppclk_khz;
527 			   __entry->bw_dispclk_khz = clk->bw_dispclk_khz;
528 	    ),
529 	    TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
530 		      "dcfclk_deep_sleep_khz=%d fclk_khz=%d phyclk_khz=%d "
531 		      "dramclk_khz=%d p_state_change_support=%d "
532 		      "prev_p_state_change_support=%d pwr_state=%d prev_p_state_change_support=%d "
533 		      "dtm_level=%d max_supported_dppclk_khz=%d max_supported_dispclk_khz=%d "
534 		      "bw_dppclk_khz=%d bw_dispclk_khz=%d ",
535 		      __entry->dispclk_khz,
536 		      __entry->dppclk_khz,
537 		      __entry->disp_dpp_voltage_level_khz,
538 		      __entry->dcfclk_khz,
539 		      __entry->socclk_khz,
540 		      __entry->dcfclk_deep_sleep_khz,
541 		      __entry->fclk_khz,
542 		      __entry->phyclk_khz,
543 		      __entry->dramclk_khz,
544 		      __entry->p_state_change_support,
545 		      __entry->prev_p_state_change_support,
546 		      __entry->pwr_state,
547 		      __entry->prev_p_state_change_support,
548 		      __entry->dtm_level,
549 		      __entry->max_supported_dppclk_khz,
550 		      __entry->max_supported_dispclk_khz,
551 		      __entry->bw_dppclk_khz,
552 		      __entry->bw_dispclk_khz
553 	    )
554 );
555 
556 TRACE_EVENT(amdgpu_dm_dce_clocks_state,
557 	    TP_PROTO(const struct dce_bw_output *clk),
558 	    TP_ARGS(clk),
559 
560 	    TP_STRUCT__entry(
561 			     __field(bool, cpuc_state_change_enable)
562 			     __field(bool, cpup_state_change_enable)
563 			     __field(bool, stutter_mode_enable)
564 			     __field(bool, nbp_state_change_enable)
565 			     __field(bool, all_displays_in_sync)
566 			     __field(int, sclk_khz)
567 			     __field(int, sclk_deep_sleep_khz)
568 			     __field(int, yclk_khz)
569 			     __field(int, dispclk_khz)
570 			     __field(int, blackout_recovery_time_us)
571 	    ),
572 	    TP_fast_assign(
573 			   __entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;
574 			   __entry->cpup_state_change_enable = clk->cpup_state_change_enable;
575 			   __entry->stutter_mode_enable = clk->stutter_mode_enable;
576 			   __entry->nbp_state_change_enable = clk->nbp_state_change_enable;
577 			   __entry->all_displays_in_sync = clk->all_displays_in_sync;
578 			   __entry->sclk_khz = clk->sclk_khz;
579 			   __entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;
580 			   __entry->yclk_khz = clk->yclk_khz;
581 			   __entry->dispclk_khz = clk->dispclk_khz;
582 			   __entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;
583 	    ),
584 	    TP_printk("cpuc_state_change_enable=%d cpup_state_change_enable=%d stutter_mode_enable=%d "
585 		      "nbp_state_change_enable=%d all_displays_in_sync=%d sclk_khz=%d sclk_deep_sleep_khz=%d "
586 		      "yclk_khz=%d dispclk_khz=%d blackout_recovery_time_us=%d",
587 		      __entry->cpuc_state_change_enable,
588 		      __entry->cpup_state_change_enable,
589 		      __entry->stutter_mode_enable,
590 		      __entry->nbp_state_change_enable,
591 		      __entry->all_displays_in_sync,
592 		      __entry->sclk_khz,
593 		      __entry->sclk_deep_sleep_khz,
594 		      __entry->yclk_khz,
595 		      __entry->dispclk_khz,
596 		      __entry->blackout_recovery_time_us
597 	    )
598 );
599 
600 TRACE_EVENT(amdgpu_dmub_trace_high_irq,
601 	TP_PROTO(uint32_t trace_code, uint32_t tick_count, uint32_t param0,
602 		 uint32_t param1),
603 	TP_ARGS(trace_code, tick_count, param0, param1),
604 	TP_STRUCT__entry(
605 		__field(uint32_t, trace_code)
606 		__field(uint32_t, tick_count)
607 		__field(uint32_t, param0)
608 		__field(uint32_t, param1)
609 		),
610 	TP_fast_assign(
611 		__entry->trace_code = trace_code;
612 		__entry->tick_count = tick_count;
613 		__entry->param0 = param0;
614 		__entry->param1 = param1;
615 	),
616 	TP_printk("trace_code=%u tick_count=%u param0=%u param1=%u",
617 		  __entry->trace_code, __entry->tick_count,
618 		  __entry->param0, __entry->param1)
619 );
620 
621 TRACE_EVENT(amdgpu_refresh_rate_track,
622 	TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz),
623 	TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz),
624 	TP_STRUCT__entry(
625 		__field(int, crtc_index)
626 		__field(ktime_t, refresh_rate_ns)
627 		__field(uint32_t, refresh_rate_hz)
628 		),
629 	TP_fast_assign(
630 		__entry->crtc_index = crtc_index;
631 		__entry->refresh_rate_ns = refresh_rate_ns;
632 		__entry->refresh_rate_hz = refresh_rate_hz;
633 	),
634 	TP_printk("crtc_index=%d refresh_rate=%dHz (%lld)",
635 		  __entry->crtc_index,
636 		  __entry->refresh_rate_hz,
637 		  __entry->refresh_rate_ns)
638 );
639 
640 TRACE_EVENT(dcn_fpu,
641 	    TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth),
642 	    TP_ARGS(begin, function, line, recursion_depth),
643 
644 	    TP_STRUCT__entry(
645 			     __field(bool, begin)
646 			     __field(const char *, function)
647 			     __field(int, line)
648 			     __field(int, recursion_depth)
649 	    ),
650 	    TP_fast_assign(
651 			   __entry->begin = begin;
652 			   __entry->function = function;
653 			   __entry->line = line;
654 			   __entry->recursion_depth = recursion_depth;
655 	    ),
656 	    TP_printk("%s: recursion_depth: %d: %s()+%d:",
657 		      __entry->begin ? "begin" : "end",
658 		      __entry->recursion_depth,
659 		      __entry->function,
660 		      __entry->line
661 	    )
662 );
663 
664 #endif /* _AMDGPU_DM_TRACE_H_ */
665 
666 #undef TRACE_INCLUDE_PATH
667 #define TRACE_INCLUDE_PATH .
668 #define TRACE_INCLUDE_FILE amdgpu_dm_trace
669 #include <trace/define_trace.h>
670