1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/amdgpu_drm.h> 32 #include "dm_services.h" 33 #include "amdgpu.h" 34 #include "amdgpu_dm.h" 35 #include "amdgpu_dm_irq.h" 36 #include "amdgpu_pm.h" 37 38 unsigned long long dm_get_timestamp(struct dc_context *ctx) 39 { 40 /* TODO: return actual timestamp */ 41 return 0; 42 } 43 44 bool dm_write_persistent_data(struct dc_context *ctx, 45 const struct dc_sink *sink, 46 const char *module_name, 47 const char *key_name, 48 void *params, 49 unsigned int size, 50 struct persistent_data_flag *flag) 51 { 52 /*TODO implement*/ 53 return false; 54 } 55 56 bool dm_read_persistent_data(struct dc_context *ctx, 57 const struct dc_sink *sink, 58 const char *module_name, 59 const char *key_name, 60 void *params, 61 unsigned int size, 62 struct persistent_data_flag *flag) 63 { 64 /*TODO implement*/ 65 return false; 66 } 67 68 /**** power component interfaces ****/ 69 70 bool dm_pp_pre_dce_clock_change( 71 struct dc_context *ctx, 72 struct dm_pp_gpu_clock_range *requested_state, 73 struct dm_pp_gpu_clock_range *actual_state) 74 { 75 /*TODO*/ 76 return false; 77 } 78 79 bool dm_pp_apply_display_requirements( 80 const struct dc_context *ctx, 81 const struct dm_pp_display_configuration *pp_display_cfg) 82 { 83 struct amdgpu_device *adev = ctx->driver_context; 84 85 if (adev->pm.dpm_enabled) { 86 87 memset(&adev->pm.pm_display_cfg, 0, 88 sizeof(adev->pm.pm_display_cfg)); 89 90 adev->pm.pm_display_cfg.cpu_cc6_disable = 91 pp_display_cfg->cpu_cc6_disable; 92 93 adev->pm.pm_display_cfg.cpu_pstate_disable = 94 pp_display_cfg->cpu_pstate_disable; 95 96 adev->pm.pm_display_cfg.cpu_pstate_separation_time = 97 pp_display_cfg->cpu_pstate_separation_time; 98 99 adev->pm.pm_display_cfg.nb_pstate_switch_disable = 100 pp_display_cfg->nb_pstate_switch_disable; 101 102 adev->pm.pm_display_cfg.num_display = 103 pp_display_cfg->display_count; 104 adev->pm.pm_display_cfg.num_path_including_non_display = 105 pp_display_cfg->display_count; 106 107 adev->pm.pm_display_cfg.min_core_set_clock = 108 pp_display_cfg->min_engine_clock_khz/10; 109 adev->pm.pm_display_cfg.min_core_set_clock_in_sr = 110 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 111 adev->pm.pm_display_cfg.min_mem_set_clock = 112 pp_display_cfg->min_memory_clock_khz/10; 113 114 adev->pm.pm_display_cfg.multi_monitor_in_sync = 115 pp_display_cfg->all_displays_in_sync; 116 adev->pm.pm_display_cfg.min_vblank_time = 117 pp_display_cfg->avail_mclk_switch_time_us; 118 119 adev->pm.pm_display_cfg.display_clk = 120 pp_display_cfg->disp_clk_khz/10; 121 122 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency = 123 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; 124 125 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; 126 adev->pm.pm_display_cfg.line_time_in_us = 127 pp_display_cfg->line_time_in_us; 128 129 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; 130 adev->pm.pm_display_cfg.crossfire_display_index = -1; 131 adev->pm.pm_display_cfg.min_bus_bandwidth = 0; 132 133 /* TODO: complete implementation of 134 * pp_display_configuration_change(). 135 * Follow example of: 136 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c 137 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ 138 if (adev->powerplay.pp_funcs->display_configuration_change) 139 adev->powerplay.pp_funcs->display_configuration_change( 140 adev->powerplay.pp_handle, 141 &adev->pm.pm_display_cfg); 142 143 /* TODO: replace by a separate call to 'apply display cfg'? */ 144 amdgpu_pm_compute_clocks(adev); 145 } 146 147 return true; 148 } 149 150 bool dc_service_get_system_clocks_range( 151 const struct dc_context *ctx, 152 struct dm_pp_gpu_clock_range *sys_clks) 153 { 154 struct amdgpu_device *adev = ctx->driver_context; 155 156 /* Default values, in case PPLib is not compiled-in. */ 157 sys_clks->mclk.max_khz = 800000; 158 sys_clks->mclk.min_khz = 800000; 159 160 sys_clks->sclk.max_khz = 600000; 161 sys_clks->sclk.min_khz = 300000; 162 163 if (adev->pm.dpm_enabled) { 164 sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false); 165 sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true); 166 167 sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false); 168 sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true); 169 } 170 171 return true; 172 } 173 174 static void get_default_clock_levels( 175 enum dm_pp_clock_type clk_type, 176 struct dm_pp_clock_levels *clks) 177 { 178 uint32_t disp_clks_in_khz[6] = { 179 300000, 400000, 496560, 626090, 685720, 757900 }; 180 uint32_t sclks_in_khz[6] = { 181 300000, 360000, 423530, 514290, 626090, 720000 }; 182 uint32_t mclks_in_khz[2] = { 333000, 800000 }; 183 184 switch (clk_type) { 185 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 186 clks->num_levels = 6; 187 memmove(clks->clocks_in_khz, disp_clks_in_khz, 188 sizeof(disp_clks_in_khz)); 189 break; 190 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 191 clks->num_levels = 6; 192 memmove(clks->clocks_in_khz, sclks_in_khz, 193 sizeof(sclks_in_khz)); 194 break; 195 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 196 clks->num_levels = 2; 197 memmove(clks->clocks_in_khz, mclks_in_khz, 198 sizeof(mclks_in_khz)); 199 break; 200 default: 201 clks->num_levels = 0; 202 break; 203 } 204 } 205 206 static enum amd_pp_clock_type dc_to_pp_clock_type( 207 enum dm_pp_clock_type dm_pp_clk_type) 208 { 209 enum amd_pp_clock_type amd_pp_clk_type = 0; 210 211 switch (dm_pp_clk_type) { 212 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 213 amd_pp_clk_type = amd_pp_disp_clock; 214 break; 215 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 216 amd_pp_clk_type = amd_pp_sys_clock; 217 break; 218 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 219 amd_pp_clk_type = amd_pp_mem_clock; 220 break; 221 default: 222 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 223 dm_pp_clk_type); 224 break; 225 } 226 227 return amd_pp_clk_type; 228 } 229 230 static void pp_to_dc_clock_levels( 231 const struct amd_pp_clocks *pp_clks, 232 struct dm_pp_clock_levels *dc_clks, 233 enum dm_pp_clock_type dc_clk_type) 234 { 235 uint32_t i; 236 237 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { 238 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 239 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 240 pp_clks->count, 241 DM_PP_MAX_CLOCK_LEVELS); 242 243 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 244 } else 245 dc_clks->num_levels = pp_clks->count; 246 247 DRM_INFO("DM_PPLIB: values for %s clock\n", 248 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 249 250 for (i = 0; i < dc_clks->num_levels; i++) { 251 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 252 /* translate 10kHz to kHz */ 253 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10; 254 } 255 } 256 257 bool dm_pp_get_clock_levels_by_type( 258 const struct dc_context *ctx, 259 enum dm_pp_clock_type clk_type, 260 struct dm_pp_clock_levels *dc_clks) 261 { 262 struct amdgpu_device *adev = ctx->driver_context; 263 void *pp_handle = adev->powerplay.pp_handle; 264 struct amd_pp_clocks pp_clks = { 0 }; 265 struct amd_pp_simple_clock_info validation_clks = { 0 }; 266 uint32_t i; 267 268 if (adev->powerplay.pp_funcs->get_clock_by_type) { 269 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, 270 dc_to_pp_clock_type(clk_type), &pp_clks)) { 271 /* Error in pplib. Provide default values. */ 272 get_default_clock_levels(clk_type, dc_clks); 273 return true; 274 } 275 } 276 277 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); 278 279 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { 280 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( 281 pp_handle, &validation_clks)) { 282 /* Error in pplib. Provide default values. */ 283 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); 284 validation_clks.engine_max_clock = 72000; 285 validation_clks.memory_max_clock = 80000; 286 validation_clks.level = 0; 287 } 288 } 289 290 DRM_INFO("DM_PPLIB: Validation clocks:\n"); 291 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n", 292 validation_clks.engine_max_clock); 293 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n", 294 validation_clks.memory_max_clock); 295 DRM_INFO("DM_PPLIB: level : %d\n", 296 validation_clks.level); 297 298 /* Translate 10 kHz to kHz. */ 299 validation_clks.engine_max_clock *= 10; 300 validation_clks.memory_max_clock *= 10; 301 302 /* Determine the highest non-boosted level from the Validation Clocks */ 303 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { 304 for (i = 0; i < dc_clks->num_levels; i++) { 305 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { 306 /* This clock is higher the validation clock. 307 * Than means the previous one is the highest 308 * non-boosted one. */ 309 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", 310 dc_clks->num_levels, i); 311 dc_clks->num_levels = i > 0 ? i : 1; 312 break; 313 } 314 } 315 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { 316 for (i = 0; i < dc_clks->num_levels; i++) { 317 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) { 318 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n", 319 dc_clks->num_levels, i); 320 dc_clks->num_levels = i > 0 ? i : 1; 321 break; 322 } 323 } 324 } 325 326 return true; 327 } 328 329 bool dm_pp_get_clock_levels_by_type_with_latency( 330 const struct dc_context *ctx, 331 enum dm_pp_clock_type clk_type, 332 struct dm_pp_clock_levels_with_latency *clk_level_info) 333 { 334 /* TODO: to be implemented */ 335 return false; 336 } 337 338 bool dm_pp_get_clock_levels_by_type_with_voltage( 339 const struct dc_context *ctx, 340 enum dm_pp_clock_type clk_type, 341 struct dm_pp_clock_levels_with_voltage *clk_level_info) 342 { 343 /* TODO: to be implemented */ 344 return false; 345 } 346 347 bool dm_pp_notify_wm_clock_changes( 348 const struct dc_context *ctx, 349 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) 350 { 351 /* TODO: to be implemented */ 352 return false; 353 } 354 355 bool dm_pp_apply_power_level_change_request( 356 const struct dc_context *ctx, 357 struct dm_pp_power_level_change_request *level_change_req) 358 { 359 /* TODO: to be implemented */ 360 return false; 361 } 362 363 bool dm_pp_apply_clock_for_voltage_request( 364 const struct dc_context *ctx, 365 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) 366 { 367 /* TODO: to be implemented */ 368 return false; 369 } 370 371 bool dm_pp_get_static_clocks( 372 const struct dc_context *ctx, 373 struct dm_pp_static_clock_info *static_clk_info) 374 { 375 /* TODO: to be implemented */ 376 return false; 377 } 378 379 void dm_pp_get_funcs_rv( 380 struct dc_context *ctx, 381 struct pp_smu_funcs_rv *funcs) 382 {} 383 384 /**** end of power component interfaces ****/ 385