1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/amdgpu_drm.h> 32 #include "dm_services.h" 33 #include "amdgpu.h" 34 #include "amdgpu_dm.h" 35 #include "amdgpu_dm_irq.h" 36 #include "amdgpu_pm.h" 37 38 unsigned long long dm_get_timestamp(struct dc_context *ctx) 39 { 40 /* TODO: return actual timestamp */ 41 return 0; 42 } 43 44 void dm_perf_trace_timestamp(const char *func_name, unsigned int line) 45 { 46 } 47 48 bool dm_write_persistent_data(struct dc_context *ctx, 49 const struct dc_sink *sink, 50 const char *module_name, 51 const char *key_name, 52 void *params, 53 unsigned int size, 54 struct persistent_data_flag *flag) 55 { 56 /*TODO implement*/ 57 return false; 58 } 59 60 bool dm_read_persistent_data(struct dc_context *ctx, 61 const struct dc_sink *sink, 62 const char *module_name, 63 const char *key_name, 64 void *params, 65 unsigned int size, 66 struct persistent_data_flag *flag) 67 { 68 /*TODO implement*/ 69 return false; 70 } 71 72 /**** power component interfaces ****/ 73 74 bool dm_pp_pre_dce_clock_change( 75 struct dc_context *ctx, 76 struct dm_pp_gpu_clock_range *requested_state, 77 struct dm_pp_gpu_clock_range *actual_state) 78 { 79 /*TODO*/ 80 return false; 81 } 82 83 bool dm_pp_apply_display_requirements( 84 const struct dc_context *ctx, 85 const struct dm_pp_display_configuration *pp_display_cfg) 86 { 87 struct amdgpu_device *adev = ctx->driver_context; 88 89 if (adev->pm.dpm_enabled) { 90 91 memset(&adev->pm.pm_display_cfg, 0, 92 sizeof(adev->pm.pm_display_cfg)); 93 94 adev->pm.pm_display_cfg.cpu_cc6_disable = 95 pp_display_cfg->cpu_cc6_disable; 96 97 adev->pm.pm_display_cfg.cpu_pstate_disable = 98 pp_display_cfg->cpu_pstate_disable; 99 100 adev->pm.pm_display_cfg.cpu_pstate_separation_time = 101 pp_display_cfg->cpu_pstate_separation_time; 102 103 adev->pm.pm_display_cfg.nb_pstate_switch_disable = 104 pp_display_cfg->nb_pstate_switch_disable; 105 106 adev->pm.pm_display_cfg.num_display = 107 pp_display_cfg->display_count; 108 adev->pm.pm_display_cfg.num_path_including_non_display = 109 pp_display_cfg->display_count; 110 111 adev->pm.pm_display_cfg.min_core_set_clock = 112 pp_display_cfg->min_engine_clock_khz/10; 113 adev->pm.pm_display_cfg.min_core_set_clock_in_sr = 114 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 115 adev->pm.pm_display_cfg.min_mem_set_clock = 116 pp_display_cfg->min_memory_clock_khz/10; 117 118 adev->pm.pm_display_cfg.multi_monitor_in_sync = 119 pp_display_cfg->all_displays_in_sync; 120 adev->pm.pm_display_cfg.min_vblank_time = 121 pp_display_cfg->avail_mclk_switch_time_us; 122 123 adev->pm.pm_display_cfg.display_clk = 124 pp_display_cfg->disp_clk_khz/10; 125 126 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency = 127 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; 128 129 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; 130 adev->pm.pm_display_cfg.line_time_in_us = 131 pp_display_cfg->line_time_in_us; 132 133 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; 134 adev->pm.pm_display_cfg.crossfire_display_index = -1; 135 adev->pm.pm_display_cfg.min_bus_bandwidth = 0; 136 137 /* TODO: complete implementation of 138 * pp_display_configuration_change(). 139 * Follow example of: 140 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c 141 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ 142 if (adev->powerplay.pp_funcs->display_configuration_change) 143 adev->powerplay.pp_funcs->display_configuration_change( 144 adev->powerplay.pp_handle, 145 &adev->pm.pm_display_cfg); 146 147 /* TODO: replace by a separate call to 'apply display cfg'? */ 148 amdgpu_pm_compute_clocks(adev); 149 } 150 151 return true; 152 } 153 154 bool dc_service_get_system_clocks_range( 155 const struct dc_context *ctx, 156 struct dm_pp_gpu_clock_range *sys_clks) 157 { 158 struct amdgpu_device *adev = ctx->driver_context; 159 160 /* Default values, in case PPLib is not compiled-in. */ 161 sys_clks->mclk.max_khz = 800000; 162 sys_clks->mclk.min_khz = 800000; 163 164 sys_clks->sclk.max_khz = 600000; 165 sys_clks->sclk.min_khz = 300000; 166 167 if (adev->pm.dpm_enabled) { 168 sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false); 169 sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true); 170 171 sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false); 172 sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true); 173 } 174 175 return true; 176 } 177 178 static void get_default_clock_levels( 179 enum dm_pp_clock_type clk_type, 180 struct dm_pp_clock_levels *clks) 181 { 182 uint32_t disp_clks_in_khz[6] = { 183 300000, 400000, 496560, 626090, 685720, 757900 }; 184 uint32_t sclks_in_khz[6] = { 185 300000, 360000, 423530, 514290, 626090, 720000 }; 186 uint32_t mclks_in_khz[2] = { 333000, 800000 }; 187 188 switch (clk_type) { 189 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 190 clks->num_levels = 6; 191 memmove(clks->clocks_in_khz, disp_clks_in_khz, 192 sizeof(disp_clks_in_khz)); 193 break; 194 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 195 clks->num_levels = 6; 196 memmove(clks->clocks_in_khz, sclks_in_khz, 197 sizeof(sclks_in_khz)); 198 break; 199 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 200 clks->num_levels = 2; 201 memmove(clks->clocks_in_khz, mclks_in_khz, 202 sizeof(mclks_in_khz)); 203 break; 204 default: 205 clks->num_levels = 0; 206 break; 207 } 208 } 209 210 static enum amd_pp_clock_type dc_to_pp_clock_type( 211 enum dm_pp_clock_type dm_pp_clk_type) 212 { 213 enum amd_pp_clock_type amd_pp_clk_type = 0; 214 215 switch (dm_pp_clk_type) { 216 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 217 amd_pp_clk_type = amd_pp_disp_clock; 218 break; 219 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 220 amd_pp_clk_type = amd_pp_sys_clock; 221 break; 222 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 223 amd_pp_clk_type = amd_pp_mem_clock; 224 break; 225 default: 226 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 227 dm_pp_clk_type); 228 break; 229 } 230 231 return amd_pp_clk_type; 232 } 233 234 static void pp_to_dc_clock_levels( 235 const struct amd_pp_clocks *pp_clks, 236 struct dm_pp_clock_levels *dc_clks, 237 enum dm_pp_clock_type dc_clk_type) 238 { 239 uint32_t i; 240 241 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { 242 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 243 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 244 pp_clks->count, 245 DM_PP_MAX_CLOCK_LEVELS); 246 247 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 248 } else 249 dc_clks->num_levels = pp_clks->count; 250 251 DRM_INFO("DM_PPLIB: values for %s clock\n", 252 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 253 254 for (i = 0; i < dc_clks->num_levels; i++) { 255 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 256 /* translate 10kHz to kHz */ 257 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10; 258 } 259 } 260 261 bool dm_pp_get_clock_levels_by_type( 262 const struct dc_context *ctx, 263 enum dm_pp_clock_type clk_type, 264 struct dm_pp_clock_levels *dc_clks) 265 { 266 struct amdgpu_device *adev = ctx->driver_context; 267 void *pp_handle = adev->powerplay.pp_handle; 268 struct amd_pp_clocks pp_clks = { 0 }; 269 struct amd_pp_simple_clock_info validation_clks = { 0 }; 270 uint32_t i; 271 272 if (adev->powerplay.pp_funcs->get_clock_by_type) { 273 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, 274 dc_to_pp_clock_type(clk_type), &pp_clks)) { 275 /* Error in pplib. Provide default values. */ 276 get_default_clock_levels(clk_type, dc_clks); 277 return true; 278 } 279 } 280 281 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); 282 283 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { 284 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( 285 pp_handle, &validation_clks)) { 286 /* Error in pplib. Provide default values. */ 287 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); 288 validation_clks.engine_max_clock = 72000; 289 validation_clks.memory_max_clock = 80000; 290 validation_clks.level = 0; 291 } 292 } 293 294 DRM_INFO("DM_PPLIB: Validation clocks:\n"); 295 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n", 296 validation_clks.engine_max_clock); 297 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n", 298 validation_clks.memory_max_clock); 299 DRM_INFO("DM_PPLIB: level : %d\n", 300 validation_clks.level); 301 302 /* Translate 10 kHz to kHz. */ 303 validation_clks.engine_max_clock *= 10; 304 validation_clks.memory_max_clock *= 10; 305 306 /* Determine the highest non-boosted level from the Validation Clocks */ 307 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { 308 for (i = 0; i < dc_clks->num_levels; i++) { 309 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { 310 /* This clock is higher the validation clock. 311 * Than means the previous one is the highest 312 * non-boosted one. */ 313 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", 314 dc_clks->num_levels, i); 315 dc_clks->num_levels = i > 0 ? i : 1; 316 break; 317 } 318 } 319 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { 320 for (i = 0; i < dc_clks->num_levels; i++) { 321 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) { 322 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n", 323 dc_clks->num_levels, i); 324 dc_clks->num_levels = i > 0 ? i : 1; 325 break; 326 } 327 } 328 } 329 330 return true; 331 } 332 333 bool dm_pp_get_clock_levels_by_type_with_latency( 334 const struct dc_context *ctx, 335 enum dm_pp_clock_type clk_type, 336 struct dm_pp_clock_levels_with_latency *clk_level_info) 337 { 338 /* TODO: to be implemented */ 339 return false; 340 } 341 342 bool dm_pp_get_clock_levels_by_type_with_voltage( 343 const struct dc_context *ctx, 344 enum dm_pp_clock_type clk_type, 345 struct dm_pp_clock_levels_with_voltage *clk_level_info) 346 { 347 /* TODO: to be implemented */ 348 return false; 349 } 350 351 bool dm_pp_notify_wm_clock_changes( 352 const struct dc_context *ctx, 353 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) 354 { 355 /* TODO: to be implemented */ 356 return false; 357 } 358 359 bool dm_pp_apply_power_level_change_request( 360 const struct dc_context *ctx, 361 struct dm_pp_power_level_change_request *level_change_req) 362 { 363 /* TODO: to be implemented */ 364 return false; 365 } 366 367 bool dm_pp_apply_clock_for_voltage_request( 368 const struct dc_context *ctx, 369 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) 370 { 371 /* TODO: to be implemented */ 372 return false; 373 } 374 375 bool dm_pp_get_static_clocks( 376 const struct dc_context *ctx, 377 struct dm_pp_static_clock_info *static_clk_info) 378 { 379 /* TODO: to be implemented */ 380 return false; 381 } 382 383 void dm_pp_get_funcs_rv( 384 struct dc_context *ctx, 385 struct pp_smu_funcs_rv *funcs) 386 {} 387 388 /**** end of power component interfaces ****/ 389