1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/amdgpu_drm.h> 32 #include "dm_services.h" 33 #include "amdgpu.h" 34 #include "amdgpu_dm.h" 35 #include "amdgpu_dm_irq.h" 36 #include "amdgpu_pm.h" 37 38 unsigned long long dm_get_timestamp(struct dc_context *ctx) 39 { 40 struct timespec64 time; 41 42 getrawmonotonic64(&time); 43 return timespec64_to_ns(&time); 44 } 45 46 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx, 47 unsigned long long current_time_stamp, 48 unsigned long long last_time_stamp) 49 { 50 return current_time_stamp - last_time_stamp; 51 } 52 53 void dm_perf_trace_timestamp(const char *func_name, unsigned int line) 54 { 55 } 56 57 bool dm_write_persistent_data(struct dc_context *ctx, 58 const struct dc_sink *sink, 59 const char *module_name, 60 const char *key_name, 61 void *params, 62 unsigned int size, 63 struct persistent_data_flag *flag) 64 { 65 /*TODO implement*/ 66 return false; 67 } 68 69 bool dm_read_persistent_data(struct dc_context *ctx, 70 const struct dc_sink *sink, 71 const char *module_name, 72 const char *key_name, 73 void *params, 74 unsigned int size, 75 struct persistent_data_flag *flag) 76 { 77 /*TODO implement*/ 78 return false; 79 } 80 81 /**** power component interfaces ****/ 82 83 bool dm_pp_apply_display_requirements( 84 const struct dc_context *ctx, 85 const struct dm_pp_display_configuration *pp_display_cfg) 86 { 87 struct amdgpu_device *adev = ctx->driver_context; 88 89 if (adev->pm.dpm_enabled) { 90 91 memset(&adev->pm.pm_display_cfg, 0, 92 sizeof(adev->pm.pm_display_cfg)); 93 94 adev->pm.pm_display_cfg.cpu_cc6_disable = 95 pp_display_cfg->cpu_cc6_disable; 96 97 adev->pm.pm_display_cfg.cpu_pstate_disable = 98 pp_display_cfg->cpu_pstate_disable; 99 100 adev->pm.pm_display_cfg.cpu_pstate_separation_time = 101 pp_display_cfg->cpu_pstate_separation_time; 102 103 adev->pm.pm_display_cfg.nb_pstate_switch_disable = 104 pp_display_cfg->nb_pstate_switch_disable; 105 106 adev->pm.pm_display_cfg.num_display = 107 pp_display_cfg->display_count; 108 adev->pm.pm_display_cfg.num_path_including_non_display = 109 pp_display_cfg->display_count; 110 111 adev->pm.pm_display_cfg.min_core_set_clock = 112 pp_display_cfg->min_engine_clock_khz/10; 113 adev->pm.pm_display_cfg.min_core_set_clock_in_sr = 114 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 115 adev->pm.pm_display_cfg.min_mem_set_clock = 116 pp_display_cfg->min_memory_clock_khz/10; 117 118 adev->pm.pm_display_cfg.multi_monitor_in_sync = 119 pp_display_cfg->all_displays_in_sync; 120 adev->pm.pm_display_cfg.min_vblank_time = 121 pp_display_cfg->avail_mclk_switch_time_us; 122 123 adev->pm.pm_display_cfg.display_clk = 124 pp_display_cfg->disp_clk_khz/10; 125 126 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency = 127 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; 128 129 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; 130 adev->pm.pm_display_cfg.line_time_in_us = 131 pp_display_cfg->line_time_in_us; 132 133 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; 134 adev->pm.pm_display_cfg.crossfire_display_index = -1; 135 adev->pm.pm_display_cfg.min_bus_bandwidth = 0; 136 137 /* TODO: complete implementation of 138 * pp_display_configuration_change(). 139 * Follow example of: 140 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c 141 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ 142 if (adev->powerplay.pp_funcs->display_configuration_change) 143 adev->powerplay.pp_funcs->display_configuration_change( 144 adev->powerplay.pp_handle, 145 &adev->pm.pm_display_cfg); 146 147 /* TODO: replace by a separate call to 'apply display cfg'? */ 148 amdgpu_pm_compute_clocks(adev); 149 } 150 151 return true; 152 } 153 154 static void get_default_clock_levels( 155 enum dm_pp_clock_type clk_type, 156 struct dm_pp_clock_levels *clks) 157 { 158 uint32_t disp_clks_in_khz[6] = { 159 300000, 400000, 496560, 626090, 685720, 757900 }; 160 uint32_t sclks_in_khz[6] = { 161 300000, 360000, 423530, 514290, 626090, 720000 }; 162 uint32_t mclks_in_khz[2] = { 333000, 800000 }; 163 164 switch (clk_type) { 165 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 166 clks->num_levels = 6; 167 memmove(clks->clocks_in_khz, disp_clks_in_khz, 168 sizeof(disp_clks_in_khz)); 169 break; 170 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 171 clks->num_levels = 6; 172 memmove(clks->clocks_in_khz, sclks_in_khz, 173 sizeof(sclks_in_khz)); 174 break; 175 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 176 clks->num_levels = 2; 177 memmove(clks->clocks_in_khz, mclks_in_khz, 178 sizeof(mclks_in_khz)); 179 break; 180 default: 181 clks->num_levels = 0; 182 break; 183 } 184 } 185 186 static enum amd_pp_clock_type dc_to_pp_clock_type( 187 enum dm_pp_clock_type dm_pp_clk_type) 188 { 189 enum amd_pp_clock_type amd_pp_clk_type = 0; 190 191 switch (dm_pp_clk_type) { 192 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 193 amd_pp_clk_type = amd_pp_disp_clock; 194 break; 195 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 196 amd_pp_clk_type = amd_pp_sys_clock; 197 break; 198 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 199 amd_pp_clk_type = amd_pp_mem_clock; 200 break; 201 default: 202 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 203 dm_pp_clk_type); 204 break; 205 } 206 207 return amd_pp_clk_type; 208 } 209 210 static void pp_to_dc_clock_levels( 211 const struct amd_pp_clocks *pp_clks, 212 struct dm_pp_clock_levels *dc_clks, 213 enum dm_pp_clock_type dc_clk_type) 214 { 215 uint32_t i; 216 217 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { 218 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 219 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 220 pp_clks->count, 221 DM_PP_MAX_CLOCK_LEVELS); 222 223 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 224 } else 225 dc_clks->num_levels = pp_clks->count; 226 227 DRM_INFO("DM_PPLIB: values for %s clock\n", 228 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 229 230 for (i = 0; i < dc_clks->num_levels; i++) { 231 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 232 /* translate 10kHz to kHz */ 233 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10; 234 } 235 } 236 237 static void pp_to_dc_clock_levels_with_latency( 238 const struct pp_clock_levels_with_latency *pp_clks, 239 struct dm_pp_clock_levels_with_latency *clk_level_info, 240 enum dm_pp_clock_type dc_clk_type) 241 { 242 uint32_t i; 243 244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 245 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 246 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 247 pp_clks->num_levels, 248 DM_PP_MAX_CLOCK_LEVELS); 249 250 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; 251 } else 252 clk_level_info->num_levels = pp_clks->num_levels; 253 254 DRM_DEBUG("DM_PPLIB: values for %s clock\n", 255 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 256 257 for (i = 0; i < clk_level_info->num_levels; i++) { 258 DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); 259 /* translate 10kHz to kHz */ 260 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; 261 clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; 262 } 263 } 264 265 bool dm_pp_get_clock_levels_by_type( 266 const struct dc_context *ctx, 267 enum dm_pp_clock_type clk_type, 268 struct dm_pp_clock_levels *dc_clks) 269 { 270 struct amdgpu_device *adev = ctx->driver_context; 271 void *pp_handle = adev->powerplay.pp_handle; 272 struct amd_pp_clocks pp_clks = { 0 }; 273 struct amd_pp_simple_clock_info validation_clks = { 0 }; 274 uint32_t i; 275 276 if (adev->powerplay.pp_funcs->get_clock_by_type) { 277 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, 278 dc_to_pp_clock_type(clk_type), &pp_clks)) { 279 /* Error in pplib. Provide default values. */ 280 get_default_clock_levels(clk_type, dc_clks); 281 return true; 282 } 283 } 284 285 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); 286 287 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { 288 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( 289 pp_handle, &validation_clks)) { 290 /* Error in pplib. Provide default values. */ 291 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); 292 validation_clks.engine_max_clock = 72000; 293 validation_clks.memory_max_clock = 80000; 294 validation_clks.level = 0; 295 } 296 } 297 298 DRM_INFO("DM_PPLIB: Validation clocks:\n"); 299 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n", 300 validation_clks.engine_max_clock); 301 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n", 302 validation_clks.memory_max_clock); 303 DRM_INFO("DM_PPLIB: level : %d\n", 304 validation_clks.level); 305 306 /* Translate 10 kHz to kHz. */ 307 validation_clks.engine_max_clock *= 10; 308 validation_clks.memory_max_clock *= 10; 309 310 /* Determine the highest non-boosted level from the Validation Clocks */ 311 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { 312 for (i = 0; i < dc_clks->num_levels; i++) { 313 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { 314 /* This clock is higher the validation clock. 315 * Than means the previous one is the highest 316 * non-boosted one. */ 317 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", 318 dc_clks->num_levels, i); 319 dc_clks->num_levels = i > 0 ? i : 1; 320 break; 321 } 322 } 323 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { 324 for (i = 0; i < dc_clks->num_levels; i++) { 325 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) { 326 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n", 327 dc_clks->num_levels, i); 328 dc_clks->num_levels = i > 0 ? i : 1; 329 break; 330 } 331 } 332 } 333 334 return true; 335 } 336 337 bool dm_pp_get_clock_levels_by_type_with_latency( 338 const struct dc_context *ctx, 339 enum dm_pp_clock_type clk_type, 340 struct dm_pp_clock_levels_with_latency *clk_level_info) 341 { 342 struct amdgpu_device *adev = ctx->driver_context; 343 void *pp_handle = adev->powerplay.pp_handle; 344 struct pp_clock_levels_with_latency pp_clks = { 0 }; 345 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 346 347 if (!pp_funcs->get_clock_by_type_with_latency) 348 return false; 349 350 if (pp_funcs->get_clock_by_type_with_latency(pp_handle, 351 dc_to_pp_clock_type(clk_type), 352 &pp_clks)) 353 return false; 354 355 pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); 356 357 return true; 358 } 359 360 bool dm_pp_get_clock_levels_by_type_with_voltage( 361 const struct dc_context *ctx, 362 enum dm_pp_clock_type clk_type, 363 struct dm_pp_clock_levels_with_voltage *clk_level_info) 364 { 365 /* TODO: to be implemented */ 366 return false; 367 } 368 369 bool dm_pp_notify_wm_clock_changes( 370 const struct dc_context *ctx, 371 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) 372 { 373 /* TODO: to be implemented */ 374 return false; 375 } 376 377 bool dm_pp_apply_power_level_change_request( 378 const struct dc_context *ctx, 379 struct dm_pp_power_level_change_request *level_change_req) 380 { 381 /* TODO: to be implemented */ 382 return false; 383 } 384 385 bool dm_pp_apply_clock_for_voltage_request( 386 const struct dc_context *ctx, 387 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) 388 { 389 /* TODO: to be implemented */ 390 return false; 391 } 392 393 bool dm_pp_get_static_clocks( 394 const struct dc_context *ctx, 395 struct dm_pp_static_clock_info *static_clk_info) 396 { 397 /* TODO: to be implemented */ 398 return false; 399 } 400 401 void dm_pp_get_funcs_rv( 402 struct dc_context *ctx, 403 struct pp_smu_funcs_rv *funcs) 404 {} 405 406 /**** end of power component interfaces ****/ 407