1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 29 #include <drm/drmP.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/amdgpu_drm.h> 32 #include "dm_services.h" 33 #include "amdgpu.h" 34 #include "amdgpu_dm.h" 35 #include "amdgpu_dm_irq.h" 36 #include "amdgpu_pm.h" 37 #include "dm_pp_smu.h" 38 #include "../../powerplay/inc/hwmgr.h" 39 #include "../../powerplay/hwmgr/smu10_hwmgr.h" 40 41 42 43 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx, 44 unsigned long long current_time_stamp, 45 unsigned long long last_time_stamp) 46 { 47 return current_time_stamp - last_time_stamp; 48 } 49 50 void dm_perf_trace_timestamp(const char *func_name, unsigned int line) 51 { 52 } 53 54 bool dm_write_persistent_data(struct dc_context *ctx, 55 const struct dc_sink *sink, 56 const char *module_name, 57 const char *key_name, 58 void *params, 59 unsigned int size, 60 struct persistent_data_flag *flag) 61 { 62 /*TODO implement*/ 63 return false; 64 } 65 66 bool dm_read_persistent_data(struct dc_context *ctx, 67 const struct dc_sink *sink, 68 const char *module_name, 69 const char *key_name, 70 void *params, 71 unsigned int size, 72 struct persistent_data_flag *flag) 73 { 74 /*TODO implement*/ 75 return false; 76 } 77 78 /**** power component interfaces ****/ 79 80 bool dm_pp_apply_display_requirements( 81 const struct dc_context *ctx, 82 const struct dm_pp_display_configuration *pp_display_cfg) 83 { 84 struct amdgpu_device *adev = ctx->driver_context; 85 86 if (adev->pm.dpm_enabled) { 87 88 memset(&adev->pm.pm_display_cfg, 0, 89 sizeof(adev->pm.pm_display_cfg)); 90 91 adev->pm.pm_display_cfg.cpu_cc6_disable = 92 pp_display_cfg->cpu_cc6_disable; 93 94 adev->pm.pm_display_cfg.cpu_pstate_disable = 95 pp_display_cfg->cpu_pstate_disable; 96 97 adev->pm.pm_display_cfg.cpu_pstate_separation_time = 98 pp_display_cfg->cpu_pstate_separation_time; 99 100 adev->pm.pm_display_cfg.nb_pstate_switch_disable = 101 pp_display_cfg->nb_pstate_switch_disable; 102 103 adev->pm.pm_display_cfg.num_display = 104 pp_display_cfg->display_count; 105 adev->pm.pm_display_cfg.num_path_including_non_display = 106 pp_display_cfg->display_count; 107 108 adev->pm.pm_display_cfg.min_core_set_clock = 109 pp_display_cfg->min_engine_clock_khz/10; 110 adev->pm.pm_display_cfg.min_core_set_clock_in_sr = 111 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 112 adev->pm.pm_display_cfg.min_mem_set_clock = 113 pp_display_cfg->min_memory_clock_khz/10; 114 115 adev->pm.pm_display_cfg.multi_monitor_in_sync = 116 pp_display_cfg->all_displays_in_sync; 117 adev->pm.pm_display_cfg.min_vblank_time = 118 pp_display_cfg->avail_mclk_switch_time_us; 119 120 adev->pm.pm_display_cfg.display_clk = 121 pp_display_cfg->disp_clk_khz/10; 122 123 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency = 124 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; 125 126 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; 127 adev->pm.pm_display_cfg.line_time_in_us = 128 pp_display_cfg->line_time_in_us; 129 130 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; 131 adev->pm.pm_display_cfg.crossfire_display_index = -1; 132 adev->pm.pm_display_cfg.min_bus_bandwidth = 0; 133 134 /* TODO: complete implementation of 135 * pp_display_configuration_change(). 136 * Follow example of: 137 * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c 138 * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ 139 if (adev->powerplay.pp_funcs->display_configuration_change) 140 adev->powerplay.pp_funcs->display_configuration_change( 141 adev->powerplay.pp_handle, 142 &adev->pm.pm_display_cfg); 143 144 /* TODO: replace by a separate call to 'apply display cfg'? */ 145 amdgpu_pm_compute_clocks(adev); 146 } 147 148 return true; 149 } 150 151 static void get_default_clock_levels( 152 enum dm_pp_clock_type clk_type, 153 struct dm_pp_clock_levels *clks) 154 { 155 uint32_t disp_clks_in_khz[6] = { 156 300000, 400000, 496560, 626090, 685720, 757900 }; 157 uint32_t sclks_in_khz[6] = { 158 300000, 360000, 423530, 514290, 626090, 720000 }; 159 uint32_t mclks_in_khz[2] = { 333000, 800000 }; 160 161 switch (clk_type) { 162 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 163 clks->num_levels = 6; 164 memmove(clks->clocks_in_khz, disp_clks_in_khz, 165 sizeof(disp_clks_in_khz)); 166 break; 167 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 168 clks->num_levels = 6; 169 memmove(clks->clocks_in_khz, sclks_in_khz, 170 sizeof(sclks_in_khz)); 171 break; 172 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 173 clks->num_levels = 2; 174 memmove(clks->clocks_in_khz, mclks_in_khz, 175 sizeof(mclks_in_khz)); 176 break; 177 default: 178 clks->num_levels = 0; 179 break; 180 } 181 } 182 183 static enum amd_pp_clock_type dc_to_pp_clock_type( 184 enum dm_pp_clock_type dm_pp_clk_type) 185 { 186 enum amd_pp_clock_type amd_pp_clk_type = 0; 187 188 switch (dm_pp_clk_type) { 189 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 190 amd_pp_clk_type = amd_pp_disp_clock; 191 break; 192 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 193 amd_pp_clk_type = amd_pp_sys_clock; 194 break; 195 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 196 amd_pp_clk_type = amd_pp_mem_clock; 197 break; 198 default: 199 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 200 dm_pp_clk_type); 201 break; 202 } 203 204 return amd_pp_clk_type; 205 } 206 207 static void pp_to_dc_clock_levels( 208 const struct amd_pp_clocks *pp_clks, 209 struct dm_pp_clock_levels *dc_clks, 210 enum dm_pp_clock_type dc_clk_type) 211 { 212 uint32_t i; 213 214 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { 215 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 216 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 217 pp_clks->count, 218 DM_PP_MAX_CLOCK_LEVELS); 219 220 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 221 } else 222 dc_clks->num_levels = pp_clks->count; 223 224 DRM_INFO("DM_PPLIB: values for %s clock\n", 225 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 226 227 for (i = 0; i < dc_clks->num_levels; i++) { 228 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 229 /* translate 10kHz to kHz */ 230 dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10; 231 } 232 } 233 234 static void pp_to_dc_clock_levels_with_latency( 235 const struct pp_clock_levels_with_latency *pp_clks, 236 struct dm_pp_clock_levels_with_latency *clk_level_info, 237 enum dm_pp_clock_type dc_clk_type) 238 { 239 uint32_t i; 240 241 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 242 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 243 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 244 pp_clks->num_levels, 245 DM_PP_MAX_CLOCK_LEVELS); 246 247 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; 248 } else 249 clk_level_info->num_levels = pp_clks->num_levels; 250 251 DRM_DEBUG("DM_PPLIB: values for %s clock\n", 252 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 253 254 for (i = 0; i < clk_level_info->num_levels; i++) { 255 DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); 256 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; 257 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us; 258 } 259 } 260 261 static void pp_to_dc_clock_levels_with_voltage( 262 const struct pp_clock_levels_with_voltage *pp_clks, 263 struct dm_pp_clock_levels_with_voltage *clk_level_info, 264 enum dm_pp_clock_type dc_clk_type) 265 { 266 uint32_t i; 267 268 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 269 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 270 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 271 pp_clks->num_levels, 272 DM_PP_MAX_CLOCK_LEVELS); 273 274 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; 275 } else 276 clk_level_info->num_levels = pp_clks->num_levels; 277 278 DRM_INFO("DM_PPLIB: values for %s clock\n", 279 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 280 281 for (i = 0; i < clk_level_info->num_levels; i++) { 282 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); 283 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; 284 clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv; 285 } 286 } 287 288 289 bool dm_pp_get_clock_levels_by_type( 290 const struct dc_context *ctx, 291 enum dm_pp_clock_type clk_type, 292 struct dm_pp_clock_levels *dc_clks) 293 { 294 struct amdgpu_device *adev = ctx->driver_context; 295 void *pp_handle = adev->powerplay.pp_handle; 296 struct amd_pp_clocks pp_clks = { 0 }; 297 struct amd_pp_simple_clock_info validation_clks = { 0 }; 298 uint32_t i; 299 300 if (adev->powerplay.pp_funcs->get_clock_by_type) { 301 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, 302 dc_to_pp_clock_type(clk_type), &pp_clks)) { 303 /* Error in pplib. Provide default values. */ 304 get_default_clock_levels(clk_type, dc_clks); 305 return true; 306 } 307 } 308 309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); 310 311 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { 312 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( 313 pp_handle, &validation_clks)) { 314 /* Error in pplib. Provide default values. */ 315 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); 316 validation_clks.engine_max_clock = 72000; 317 validation_clks.memory_max_clock = 80000; 318 validation_clks.level = 0; 319 } 320 } 321 322 DRM_INFO("DM_PPLIB: Validation clocks:\n"); 323 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n", 324 validation_clks.engine_max_clock); 325 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n", 326 validation_clks.memory_max_clock); 327 DRM_INFO("DM_PPLIB: level : %d\n", 328 validation_clks.level); 329 330 /* Translate 10 kHz to kHz. */ 331 validation_clks.engine_max_clock *= 10; 332 validation_clks.memory_max_clock *= 10; 333 334 /* Determine the highest non-boosted level from the Validation Clocks */ 335 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { 336 for (i = 0; i < dc_clks->num_levels; i++) { 337 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { 338 /* This clock is higher the validation clock. 339 * Than means the previous one is the highest 340 * non-boosted one. */ 341 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", 342 dc_clks->num_levels, i); 343 dc_clks->num_levels = i > 0 ? i : 1; 344 break; 345 } 346 } 347 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { 348 for (i = 0; i < dc_clks->num_levels; i++) { 349 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) { 350 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n", 351 dc_clks->num_levels, i); 352 dc_clks->num_levels = i > 0 ? i : 1; 353 break; 354 } 355 } 356 } 357 358 return true; 359 } 360 361 bool dm_pp_get_clock_levels_by_type_with_latency( 362 const struct dc_context *ctx, 363 enum dm_pp_clock_type clk_type, 364 struct dm_pp_clock_levels_with_latency *clk_level_info) 365 { 366 struct amdgpu_device *adev = ctx->driver_context; 367 void *pp_handle = adev->powerplay.pp_handle; 368 struct pp_clock_levels_with_latency pp_clks = { 0 }; 369 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 370 371 if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency) 372 return false; 373 374 if (pp_funcs->get_clock_by_type_with_latency(pp_handle, 375 dc_to_pp_clock_type(clk_type), 376 &pp_clks)) 377 return false; 378 379 pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); 380 381 return true; 382 } 383 384 bool dm_pp_get_clock_levels_by_type_with_voltage( 385 const struct dc_context *ctx, 386 enum dm_pp_clock_type clk_type, 387 struct dm_pp_clock_levels_with_voltage *clk_level_info) 388 { 389 struct amdgpu_device *adev = ctx->driver_context; 390 void *pp_handle = adev->powerplay.pp_handle; 391 struct pp_clock_levels_with_voltage pp_clk_info = {0}; 392 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 393 394 if (pp_funcs->get_clock_by_type_with_voltage(pp_handle, 395 dc_to_pp_clock_type(clk_type), 396 &pp_clk_info)) 397 return false; 398 399 pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type); 400 401 return true; 402 } 403 404 bool dm_pp_notify_wm_clock_changes( 405 const struct dc_context *ctx, 406 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) 407 { 408 /* TODO: to be implemented */ 409 return false; 410 } 411 412 bool dm_pp_apply_power_level_change_request( 413 const struct dc_context *ctx, 414 struct dm_pp_power_level_change_request *level_change_req) 415 { 416 /* TODO: to be implemented */ 417 return false; 418 } 419 420 bool dm_pp_apply_clock_for_voltage_request( 421 const struct dc_context *ctx, 422 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) 423 { 424 struct amdgpu_device *adev = ctx->driver_context; 425 struct pp_display_clock_request pp_clock_request = {0}; 426 int ret = 0; 427 switch (clock_for_voltage_req->clk_type) { 428 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 429 pp_clock_request.clock_type = amd_pp_disp_clock; 430 break; 431 432 case DM_PP_CLOCK_TYPE_DCEFCLK: 433 pp_clock_request.clock_type = amd_pp_dcef_clock; 434 break; 435 436 case DM_PP_CLOCK_TYPE_PIXELCLK: 437 pp_clock_request.clock_type = amd_pp_pixel_clock; 438 break; 439 440 default: 441 return false; 442 } 443 444 pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz; 445 446 if (adev->powerplay.pp_funcs->display_clock_voltage_request) 447 ret = adev->powerplay.pp_funcs->display_clock_voltage_request( 448 adev->powerplay.pp_handle, 449 &pp_clock_request); 450 if (ret) 451 return false; 452 return true; 453 } 454 455 bool dm_pp_get_static_clocks( 456 const struct dc_context *ctx, 457 struct dm_pp_static_clock_info *static_clk_info) 458 { 459 struct amdgpu_device *adev = ctx->driver_context; 460 struct amd_pp_clock_info pp_clk_info = {0}; 461 int ret = 0; 462 463 if (adev->powerplay.pp_funcs->get_current_clocks) 464 ret = adev->powerplay.pp_funcs->get_current_clocks( 465 adev->powerplay.pp_handle, 466 &pp_clk_info); 467 if (ret) 468 return false; 469 470 static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state; 471 static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock; 472 static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock; 473 474 return true; 475 } 476 477 void pp_rv_set_display_requirement(struct pp_smu *pp, 478 struct pp_smu_display_requirement_rv *req) 479 { 480 struct amdgpu_device *adev = pp->ctx->driver_context; 481 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 482 int ret = 0; 483 if (hwmgr->hwmgr_func->set_deep_sleep_dcefclk) 484 ret = hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, req->hard_min_dcefclk_khz/10); 485 if (hwmgr->hwmgr_func->set_active_display_count) 486 ret = hwmgr->hwmgr_func->set_active_display_count(hwmgr, req->display_count); 487 488 //store_cc6 is not yet implemented in SMU level 489 } 490 491 void pp_rv_set_wm_ranges(struct pp_smu *pp, 492 struct pp_smu_wm_range_sets *ranges) 493 { 494 struct amdgpu_device *adev = pp->ctx->driver_context; 495 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 496 struct pp_wm_sets_with_clock_ranges_soc15 ranges_soc15 = {0}; 497 int i = 0; 498 499 if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges || 500 !pp || !ranges) 501 return; 502 503 //not entirely sure if thats a correct assignment 504 ranges_soc15.num_wm_sets_dmif = ranges->num_reader_wm_sets; 505 ranges_soc15.num_wm_sets_mcif = ranges->num_writer_wm_sets; 506 507 for (i = 0; i < ranges_soc15.num_wm_sets_dmif; i++) { 508 if (ranges->reader_wm_sets[i].wm_inst > 3) 509 ranges_soc15.wm_sets_dmif[i].wm_set_id = DC_WM_SET_A; 510 else 511 ranges_soc15.wm_sets_dmif[i].wm_set_id = 512 ranges->reader_wm_sets[i].wm_inst; 513 ranges_soc15.wm_sets_dmif[i].wm_max_dcefclk_in_khz = 514 ranges->reader_wm_sets[i].max_drain_clk_khz; 515 ranges_soc15.wm_sets_dmif[i].wm_min_dcefclk_in_khz = 516 ranges->reader_wm_sets[i].min_drain_clk_khz; 517 ranges_soc15.wm_sets_dmif[i].wm_max_memclk_in_khz = 518 ranges->reader_wm_sets[i].max_fill_clk_khz; 519 ranges_soc15.wm_sets_dmif[i].wm_min_memclk_in_khz = 520 ranges->reader_wm_sets[i].min_fill_clk_khz; 521 } 522 523 for (i = 0; i < ranges_soc15.num_wm_sets_mcif; i++) { 524 if (ranges->writer_wm_sets[i].wm_inst > 3) 525 ranges_soc15.wm_sets_dmif[i].wm_set_id = DC_WM_SET_A; 526 else 527 ranges_soc15.wm_sets_mcif[i].wm_set_id = 528 ranges->writer_wm_sets[i].wm_inst; 529 ranges_soc15.wm_sets_mcif[i].wm_max_socclk_in_khz = 530 ranges->writer_wm_sets[i].max_fill_clk_khz; 531 ranges_soc15.wm_sets_mcif[i].wm_min_socclk_in_khz = 532 ranges->writer_wm_sets[i].min_fill_clk_khz; 533 ranges_soc15.wm_sets_mcif[i].wm_max_memclk_in_khz = 534 ranges->writer_wm_sets[i].max_fill_clk_khz; 535 ranges_soc15.wm_sets_mcif[i].wm_min_memclk_in_khz = 536 ranges->writer_wm_sets[i].min_fill_clk_khz; 537 } 538 539 hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr, &ranges_soc15); 540 541 } 542 543 void pp_rv_set_pme_wa_enable(struct pp_smu *pp) 544 { 545 struct amdgpu_device *adev = pp->ctx->driver_context; 546 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 547 548 if (hwmgr->hwmgr_func->smus_notify_pwe) 549 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); 550 } 551 552 void dm_pp_get_funcs_rv( 553 struct dc_context *ctx, 554 struct pp_smu_funcs_rv *funcs) 555 { 556 funcs->pp_smu.ctx = ctx; 557 funcs->set_display_requirement = pp_rv_set_display_requirement; 558 funcs->set_wm_ranges = pp_rv_set_wm_ranges; 559 funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable; 560 } 561 562 563 /**** end of power component interfaces ****/ 564