1f4594cd1SRoman Li /*
2f4594cd1SRoman Li  * Copyright 2021 Advanced Micro Devices, Inc.
3f4594cd1SRoman Li  *
4f4594cd1SRoman Li  * Permission is hereby granted, free of charge, to any person obtaining a
5f4594cd1SRoman Li  * copy of this software and associated documentation files (the "Software"),
6f4594cd1SRoman Li  * to deal in the Software without restriction, including without limitation
7f4594cd1SRoman Li  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f4594cd1SRoman Li  * and/or sell copies of the Software, and to permit persons to whom the
9f4594cd1SRoman Li  * Software is furnished to do so, subject to the following conditions:
10f4594cd1SRoman Li  *
11f4594cd1SRoman Li  * The above copyright notice and this permission notice shall be included in
12f4594cd1SRoman Li  * all copies or substantial portions of the Software.
13f4594cd1SRoman Li  *
14f4594cd1SRoman Li  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f4594cd1SRoman Li  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f4594cd1SRoman Li  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17f4594cd1SRoman Li  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f4594cd1SRoman Li  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f4594cd1SRoman Li  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f4594cd1SRoman Li  * OTHER DEALINGS IN THE SOFTWARE.
21f4594cd1SRoman Li  *
22f4594cd1SRoman Li  * Authors: AMD
23f4594cd1SRoman Li  *
24f4594cd1SRoman Li  */
25f4594cd1SRoman Li 
26f4594cd1SRoman Li #ifndef AMDGPU_DM_AMDGPU_DM_PSR_H_
27f4594cd1SRoman Li #define AMDGPU_DM_AMDGPU_DM_PSR_H_
28f4594cd1SRoman Li 
29f4594cd1SRoman Li #include "amdgpu.h"
30f4594cd1SRoman Li 
31*1a365683SRoman Li /* the number of pageflips before enabling psr */
32*1a365683SRoman Li #define AMDGPU_DM_PSR_ENTRY_DELAY 5
33*1a365683SRoman Li 
34f4594cd1SRoman Li void amdgpu_dm_set_psr_caps(struct dc_link *link);
35f4594cd1SRoman Li bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
36f4594cd1SRoman Li bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
37f4594cd1SRoman Li bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
38f4594cd1SRoman Li bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
39f4594cd1SRoman Li 
40f4594cd1SRoman Li #endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */
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