1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_psr.h" 27 #include "dc.h" 28 #include "dm_helpers.h" 29 #include "amdgpu_dm.h" 30 #include "modules/power/power_helpers.h" 31 32 #ifdef CONFIG_DRM_AMD_DC_DCN 33 static bool link_supports_psrsu(struct dc_link *link) 34 { 35 struct dc *dc = link->ctx->dc; 36 37 if (!dc->caps.dmcub_support) 38 return false; 39 40 if (dc->ctx->dce_version < DCN_VERSION_3_1) 41 return false; 42 43 if (!is_psr_su_specific_panel(link)) 44 return false; 45 46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || 47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) 48 return false; 49 50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && 51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) 52 return false; 53 54 return true; 55 } 56 #endif 57 58 /* 59 * amdgpu_dm_set_psr_caps() - set link psr capabilities 60 * @link: link 61 * 62 */ 63 void amdgpu_dm_set_psr_caps(struct dc_link *link) 64 { 65 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 66 return; 67 68 if (link->type == dc_connection_none) 69 return; 70 71 if (link->dpcd_caps.psr_info.psr_version == 0) { 72 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 73 link->psr_settings.psr_feature_enabled = false; 74 75 } else { 76 #ifdef CONFIG_DRM_AMD_DC_DCN 77 if (link_supports_psrsu(link)) 78 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; 79 else 80 #endif 81 link->psr_settings.psr_version = DC_PSR_VERSION_1; 82 83 link->psr_settings.psr_feature_enabled = true; 84 } 85 86 DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d\n", 87 link->psr_settings.psr_feature_enabled, 88 link->psr_settings.psr_version, 89 link->dpcd_caps.psr_info.psr_version); 90 91 } 92 93 /* 94 * amdgpu_dm_link_setup_psr() - configure psr link 95 * @stream: stream state 96 * 97 * Return: true if success 98 */ 99 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 100 { 101 struct dc_link *link = NULL; 102 struct psr_config psr_config = {0}; 103 struct psr_context psr_context = {0}; 104 bool ret = false; 105 106 if (stream == NULL) 107 return false; 108 109 link = stream->link; 110 111 if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { 112 psr_config.psr_version = link->psr_settings.psr_version; 113 psr_config.psr_frame_capture_indication_req = 0; 114 psr_config.psr_rfb_setup_time = 0x37; 115 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 116 psr_config.allow_smu_optimizations = 0x0; 117 118 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 119 120 } 121 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); 122 123 return ret; 124 } 125 126 /* 127 * amdgpu_dm_psr_enable() - enable psr f/w 128 * @stream: stream state 129 * 130 * Return: true if success 131 */ 132 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 133 { 134 struct dc_link *link = stream->link; 135 unsigned int vsync_rate_hz = 0; 136 struct dc_static_screen_params params = {0}; 137 /* Calculate number of static frames before generating interrupt to 138 * enter PSR. 139 */ 140 // Init fail safe of 2 frames static 141 unsigned int num_frames_static = 2; 142 unsigned int power_opt = 0; 143 bool psr_enable = true; 144 145 DRM_DEBUG_DRIVER("Enabling psr...\n"); 146 147 vsync_rate_hz = div64_u64(div64_u64(( 148 stream->timing.pix_clk_100hz * 100), 149 stream->timing.v_total), 150 stream->timing.h_total); 151 152 /* Round up 153 * Calculate number of frames such that at least 30 ms of time has 154 * passed. 155 */ 156 if (vsync_rate_hz != 0) { 157 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 158 num_frames_static = (30000 / frame_time_microsec) + 1; 159 } 160 161 params.triggers.cursor_update = true; 162 params.triggers.overlay_update = true; 163 params.triggers.surface_update = true; 164 params.num_frames = num_frames_static; 165 166 dc_stream_set_static_screen_params(link->ctx->dc, 167 &stream, 1, 168 ¶ms); 169 170 power_opt |= psr_power_opt_z10_static_screen; 171 172 return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); 173 } 174 175 /* 176 * amdgpu_dm_psr_disable() - disable psr f/w 177 * @stream: stream state 178 * 179 * Return: true if success 180 */ 181 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 182 { 183 unsigned int power_opt = 0; 184 bool psr_enable = false; 185 186 DRM_DEBUG_DRIVER("Disabling psr...\n"); 187 188 return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt); 189 } 190 191 /* 192 * amdgpu_dm_psr_disable() - disable psr f/w 193 * if psr is enabled on any stream 194 * 195 * Return: true if success 196 */ 197 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 198 { 199 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 200 return dc_set_psr_allow_active(dm->dc, false); 201 } 202 203