1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_psr.h" 27 #include "dc.h" 28 #include "dm_helpers.h" 29 30 /* 31 * amdgpu_dm_set_psr_caps() - set link psr capabilities 32 * @link: link 33 * 34 */ 35 void amdgpu_dm_set_psr_caps(struct dc_link *link) 36 { 37 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; 38 39 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 40 return; 41 if (link->type == dc_connection_none) 42 return; 43 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, 44 dpcd_data, sizeof(dpcd_data))) { 45 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; 46 47 if (dpcd_data[0] == 0) { 48 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 49 link->psr_settings.psr_feature_enabled = false; 50 } else { 51 link->psr_settings.psr_version = DC_PSR_VERSION_1; 52 link->psr_settings.psr_feature_enabled = true; 53 } 54 55 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled); 56 } 57 } 58 59 /* 60 * amdgpu_dm_link_setup_psr() - configure psr link 61 * @stream: stream state 62 * 63 * Return: true if success 64 */ 65 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 66 { 67 struct dc_link *link = NULL; 68 struct psr_config psr_config = {0}; 69 struct psr_context psr_context = {0}; 70 bool ret = false; 71 72 if (stream == NULL) 73 return false; 74 75 link = stream->link; 76 77 psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version; 78 79 if (psr_config.psr_version > 0) { 80 psr_config.psr_exit_link_training_required = 0x1; 81 psr_config.psr_frame_capture_indication_req = 0; 82 psr_config.psr_rfb_setup_time = 0x37; 83 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 84 psr_config.allow_smu_optimizations = 0x0; 85 86 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 87 88 } 89 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); 90 91 return ret; 92 } 93 94 /* 95 * amdgpu_dm_psr_enable() - enable psr f/w 96 * @stream: stream state 97 * 98 * Return: true if success 99 */ 100 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 101 { 102 struct dc_link *link = stream->link; 103 unsigned int vsync_rate_hz = 0; 104 struct dc_static_screen_params params = {0}; 105 /* Calculate number of static frames before generating interrupt to 106 * enter PSR. 107 */ 108 // Init fail safe of 2 frames static 109 unsigned int num_frames_static = 2; 110 111 DRM_DEBUG_DRIVER("Enabling psr...\n"); 112 113 vsync_rate_hz = div64_u64(div64_u64(( 114 stream->timing.pix_clk_100hz * 100), 115 stream->timing.v_total), 116 stream->timing.h_total); 117 118 /* Round up 119 * Calculate number of frames such that at least 30 ms of time has 120 * passed. 121 */ 122 if (vsync_rate_hz != 0) { 123 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 124 num_frames_static = (30000 / frame_time_microsec) + 1; 125 } 126 127 params.triggers.cursor_update = true; 128 params.triggers.overlay_update = true; 129 params.triggers.surface_update = true; 130 params.num_frames = num_frames_static; 131 132 dc_stream_set_static_screen_params(link->ctx->dc, 133 &stream, 1, 134 ¶ms); 135 136 return dc_link_set_psr_allow_active(link, true, false, false); 137 } 138 139 /* 140 * amdgpu_dm_psr_disable() - disable psr f/w 141 * @stream: stream state 142 * 143 * Return: true if success 144 */ 145 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 146 { 147 148 DRM_DEBUG_DRIVER("Disabling psr...\n"); 149 150 return dc_link_set_psr_allow_active(stream->link, false, true, false); 151 } 152 153 /* 154 * amdgpu_dm_psr_disable() - disable psr f/w 155 * if psr is enabled on any stream 156 * 157 * Return: true if success 158 */ 159 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 160 { 161 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 162 return dc_set_psr_allow_active(dm->dc, false); 163 } 164 165