1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_psr.h" 27 #include "dc.h" 28 #include "dm_helpers.h" 29 30 /* 31 * amdgpu_dm_set_psr_caps() - set link psr capabilities 32 * @link: link 33 * 34 */ 35 void amdgpu_dm_set_psr_caps(struct dc_link *link) 36 { 37 uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE]; 38 39 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { 40 link->psr_settings.psr_feature_enabled = false; 41 return; 42 } 43 if (link->type == dc_connection_none) { 44 link->psr_settings.psr_feature_enabled = false; 45 return; 46 } 47 if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT, 48 dpcd_data, sizeof(dpcd_data))) { 49 link->dpcd_caps.psr_caps.psr_version = dpcd_data[0]; 50 51 if (dpcd_data[0] == 0) { 52 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 53 link->psr_settings.psr_feature_enabled = false; 54 } else { 55 link->psr_settings.psr_version = DC_PSR_VERSION_1; 56 link->psr_settings.psr_feature_enabled = true; 57 } 58 59 DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled); 60 } 61 } 62 63 /* 64 * amdgpu_dm_link_setup_psr() - configure psr link 65 * @stream: stream state 66 * 67 * Return: true if success 68 */ 69 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 70 { 71 struct dc_link *link = NULL; 72 struct psr_config psr_config = {0}; 73 struct psr_context psr_context = {0}; 74 bool ret = false; 75 76 if (stream == NULL) 77 return false; 78 79 link = stream->link; 80 81 if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { 82 psr_config.psr_version = link->psr_settings.psr_version; 83 psr_config.psr_frame_capture_indication_req = 0; 84 psr_config.psr_rfb_setup_time = 0x37; 85 psr_config.psr_sdp_transmit_line_num_deadline = 0x20; 86 psr_config.allow_smu_optimizations = 0x0; 87 88 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 89 90 } 91 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); 92 93 return ret; 94 } 95 96 /* 97 * amdgpu_dm_psr_enable() - enable psr f/w 98 * @stream: stream state 99 * 100 * Return: true if success 101 */ 102 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 103 { 104 struct dc_link *link = stream->link; 105 unsigned int vsync_rate_hz = 0; 106 struct dc_static_screen_params params = {0}; 107 /* Calculate number of static frames before generating interrupt to 108 * enter PSR. 109 */ 110 // Init fail safe of 2 frames static 111 unsigned int num_frames_static = 2; 112 113 DRM_DEBUG_DRIVER("Enabling psr...\n"); 114 115 vsync_rate_hz = div64_u64(div64_u64(( 116 stream->timing.pix_clk_100hz * 100), 117 stream->timing.v_total), 118 stream->timing.h_total); 119 120 /* Round up 121 * Calculate number of frames such that at least 30 ms of time has 122 * passed. 123 */ 124 if (vsync_rate_hz != 0) { 125 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 126 num_frames_static = (30000 / frame_time_microsec) + 1; 127 } 128 129 params.triggers.cursor_update = true; 130 params.triggers.overlay_update = true; 131 params.triggers.surface_update = true; 132 params.num_frames = num_frames_static; 133 134 dc_stream_set_static_screen_params(link->ctx->dc, 135 &stream, 1, 136 ¶ms); 137 138 return dc_link_set_psr_allow_active(link, true, false, false); 139 } 140 141 /* 142 * amdgpu_dm_psr_disable() - disable psr f/w 143 * @stream: stream state 144 * 145 * Return: true if success 146 */ 147 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream) 148 { 149 150 DRM_DEBUG_DRIVER("Disabling psr...\n"); 151 152 return dc_link_set_psr_allow_active(stream->link, false, true, false); 153 } 154 155 /* 156 * amdgpu_dm_psr_disable() - disable psr f/w 157 * if psr is enabled on any stream 158 * 159 * Return: true if success 160 */ 161 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 162 { 163 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 164 return dc_set_psr_allow_active(dm->dc, false); 165 } 166 167