1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 */ 24 #include <linux/string.h> 25 #include <linux/acpi.h> 26 27 #include <drm/drm_probe_helper.h> 28 #include <drm/amdgpu_drm.h> 29 #include "dm_services.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_irq.h" 33 #include "amdgpu_pm.h" 34 #include "dm_pp_smu.h" 35 #include "amdgpu_smu.h" 36 37 38 bool dm_pp_apply_display_requirements( 39 const struct dc_context *ctx, 40 const struct dm_pp_display_configuration *pp_display_cfg) 41 { 42 struct amdgpu_device *adev = ctx->driver_context; 43 struct smu_context *smu = &adev->smu; 44 int i; 45 46 if (adev->pm.dpm_enabled) { 47 48 memset(&adev->pm.pm_display_cfg, 0, 49 sizeof(adev->pm.pm_display_cfg)); 50 51 adev->pm.pm_display_cfg.cpu_cc6_disable = 52 pp_display_cfg->cpu_cc6_disable; 53 54 adev->pm.pm_display_cfg.cpu_pstate_disable = 55 pp_display_cfg->cpu_pstate_disable; 56 57 adev->pm.pm_display_cfg.cpu_pstate_separation_time = 58 pp_display_cfg->cpu_pstate_separation_time; 59 60 adev->pm.pm_display_cfg.nb_pstate_switch_disable = 61 pp_display_cfg->nb_pstate_switch_disable; 62 63 adev->pm.pm_display_cfg.num_display = 64 pp_display_cfg->display_count; 65 adev->pm.pm_display_cfg.num_path_including_non_display = 66 pp_display_cfg->display_count; 67 68 adev->pm.pm_display_cfg.min_core_set_clock = 69 pp_display_cfg->min_engine_clock_khz/10; 70 adev->pm.pm_display_cfg.min_core_set_clock_in_sr = 71 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 72 adev->pm.pm_display_cfg.min_mem_set_clock = 73 pp_display_cfg->min_memory_clock_khz/10; 74 75 adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk = 76 pp_display_cfg->min_engine_clock_deep_sleep_khz/10; 77 adev->pm.pm_display_cfg.min_dcef_set_clk = 78 pp_display_cfg->min_dcfclock_khz/10; 79 80 adev->pm.pm_display_cfg.multi_monitor_in_sync = 81 pp_display_cfg->all_displays_in_sync; 82 adev->pm.pm_display_cfg.min_vblank_time = 83 pp_display_cfg->avail_mclk_switch_time_us; 84 85 adev->pm.pm_display_cfg.display_clk = 86 pp_display_cfg->disp_clk_khz/10; 87 88 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency = 89 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us; 90 91 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index; 92 adev->pm.pm_display_cfg.line_time_in_us = 93 pp_display_cfg->line_time_in_us; 94 95 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh; 96 adev->pm.pm_display_cfg.crossfire_display_index = -1; 97 adev->pm.pm_display_cfg.min_bus_bandwidth = 0; 98 99 for (i = 0; i < pp_display_cfg->display_count; i++) { 100 const struct dm_pp_single_disp_config *dc_cfg = 101 &pp_display_cfg->disp_configs[i]; 102 adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1; 103 } 104 105 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_configuration_change) 106 adev->powerplay.pp_funcs->display_configuration_change( 107 adev->powerplay.pp_handle, 108 &adev->pm.pm_display_cfg); 109 else if (adev->smu.ppt_funcs) 110 smu_display_configuration_change(smu, 111 &adev->pm.pm_display_cfg); 112 113 amdgpu_pm_compute_clocks(adev); 114 } 115 116 return true; 117 } 118 119 static void get_default_clock_levels( 120 enum dm_pp_clock_type clk_type, 121 struct dm_pp_clock_levels *clks) 122 { 123 uint32_t disp_clks_in_khz[6] = { 124 300000, 400000, 496560, 626090, 685720, 757900 }; 125 uint32_t sclks_in_khz[6] = { 126 300000, 360000, 423530, 514290, 626090, 720000 }; 127 uint32_t mclks_in_khz[2] = { 333000, 800000 }; 128 129 switch (clk_type) { 130 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 131 clks->num_levels = 6; 132 memmove(clks->clocks_in_khz, disp_clks_in_khz, 133 sizeof(disp_clks_in_khz)); 134 break; 135 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 136 clks->num_levels = 6; 137 memmove(clks->clocks_in_khz, sclks_in_khz, 138 sizeof(sclks_in_khz)); 139 break; 140 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 141 clks->num_levels = 2; 142 memmove(clks->clocks_in_khz, mclks_in_khz, 143 sizeof(mclks_in_khz)); 144 break; 145 default: 146 clks->num_levels = 0; 147 break; 148 } 149 } 150 151 static enum smu_clk_type dc_to_smu_clock_type( 152 enum dm_pp_clock_type dm_pp_clk_type) 153 { 154 enum smu_clk_type smu_clk_type = SMU_CLK_COUNT; 155 156 switch (dm_pp_clk_type) { 157 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 158 smu_clk_type = SMU_DISPCLK; 159 break; 160 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 161 smu_clk_type = SMU_GFXCLK; 162 break; 163 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 164 smu_clk_type = SMU_MCLK; 165 break; 166 case DM_PP_CLOCK_TYPE_DCEFCLK: 167 smu_clk_type = SMU_DCEFCLK; 168 break; 169 case DM_PP_CLOCK_TYPE_SOCCLK: 170 smu_clk_type = SMU_SOCCLK; 171 break; 172 default: 173 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 174 dm_pp_clk_type); 175 break; 176 } 177 178 return smu_clk_type; 179 } 180 181 static enum amd_pp_clock_type dc_to_pp_clock_type( 182 enum dm_pp_clock_type dm_pp_clk_type) 183 { 184 enum amd_pp_clock_type amd_pp_clk_type = 0; 185 186 switch (dm_pp_clk_type) { 187 case DM_PP_CLOCK_TYPE_DISPLAY_CLK: 188 amd_pp_clk_type = amd_pp_disp_clock; 189 break; 190 case DM_PP_CLOCK_TYPE_ENGINE_CLK: 191 amd_pp_clk_type = amd_pp_sys_clock; 192 break; 193 case DM_PP_CLOCK_TYPE_MEMORY_CLK: 194 amd_pp_clk_type = amd_pp_mem_clock; 195 break; 196 case DM_PP_CLOCK_TYPE_DCEFCLK: 197 amd_pp_clk_type = amd_pp_dcef_clock; 198 break; 199 case DM_PP_CLOCK_TYPE_DCFCLK: 200 amd_pp_clk_type = amd_pp_dcf_clock; 201 break; 202 case DM_PP_CLOCK_TYPE_PIXELCLK: 203 amd_pp_clk_type = amd_pp_pixel_clock; 204 break; 205 case DM_PP_CLOCK_TYPE_FCLK: 206 amd_pp_clk_type = amd_pp_f_clock; 207 break; 208 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: 209 amd_pp_clk_type = amd_pp_phy_clock; 210 break; 211 case DM_PP_CLOCK_TYPE_DPPCLK: 212 amd_pp_clk_type = amd_pp_dpp_clock; 213 break; 214 default: 215 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n", 216 dm_pp_clk_type); 217 break; 218 } 219 220 return amd_pp_clk_type; 221 } 222 223 static enum dm_pp_clocks_state pp_to_dc_powerlevel_state( 224 enum PP_DAL_POWERLEVEL max_clocks_state) 225 { 226 switch (max_clocks_state) { 227 case PP_DAL_POWERLEVEL_0: 228 return DM_PP_CLOCKS_DPM_STATE_LEVEL_0; 229 case PP_DAL_POWERLEVEL_1: 230 return DM_PP_CLOCKS_DPM_STATE_LEVEL_1; 231 case PP_DAL_POWERLEVEL_2: 232 return DM_PP_CLOCKS_DPM_STATE_LEVEL_2; 233 case PP_DAL_POWERLEVEL_3: 234 return DM_PP_CLOCKS_DPM_STATE_LEVEL_3; 235 case PP_DAL_POWERLEVEL_4: 236 return DM_PP_CLOCKS_DPM_STATE_LEVEL_4; 237 case PP_DAL_POWERLEVEL_5: 238 return DM_PP_CLOCKS_DPM_STATE_LEVEL_5; 239 case PP_DAL_POWERLEVEL_6: 240 return DM_PP_CLOCKS_DPM_STATE_LEVEL_6; 241 case PP_DAL_POWERLEVEL_7: 242 return DM_PP_CLOCKS_DPM_STATE_LEVEL_7; 243 default: 244 DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n", 245 max_clocks_state); 246 return DM_PP_CLOCKS_STATE_INVALID; 247 } 248 } 249 250 static void pp_to_dc_clock_levels( 251 const struct amd_pp_clocks *pp_clks, 252 struct dm_pp_clock_levels *dc_clks, 253 enum dm_pp_clock_type dc_clk_type) 254 { 255 uint32_t i; 256 257 if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) { 258 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 259 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 260 pp_clks->count, 261 DM_PP_MAX_CLOCK_LEVELS); 262 263 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 264 } else 265 dc_clks->num_levels = pp_clks->count; 266 267 DRM_INFO("DM_PPLIB: values for %s clock\n", 268 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 269 270 for (i = 0; i < dc_clks->num_levels; i++) { 271 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]); 272 dc_clks->clocks_in_khz[i] = pp_clks->clock[i]; 273 } 274 } 275 276 static void pp_to_dc_clock_levels_with_latency( 277 const struct pp_clock_levels_with_latency *pp_clks, 278 struct dm_pp_clock_levels_with_latency *clk_level_info, 279 enum dm_pp_clock_type dc_clk_type) 280 { 281 uint32_t i; 282 283 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 284 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 285 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 286 pp_clks->num_levels, 287 DM_PP_MAX_CLOCK_LEVELS); 288 289 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; 290 } else 291 clk_level_info->num_levels = pp_clks->num_levels; 292 293 DRM_DEBUG("DM_PPLIB: values for %s clock\n", 294 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 295 296 for (i = 0; i < clk_level_info->num_levels; i++) { 297 DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz); 298 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; 299 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us; 300 } 301 } 302 303 static void pp_to_dc_clock_levels_with_voltage( 304 const struct pp_clock_levels_with_voltage *pp_clks, 305 struct dm_pp_clock_levels_with_voltage *clk_level_info, 306 enum dm_pp_clock_type dc_clk_type) 307 { 308 uint32_t i; 309 310 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 311 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", 312 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), 313 pp_clks->num_levels, 314 DM_PP_MAX_CLOCK_LEVELS); 315 316 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; 317 } else 318 clk_level_info->num_levels = pp_clks->num_levels; 319 320 DRM_INFO("DM_PPLIB: values for %s clock\n", 321 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); 322 323 for (i = 0; i < clk_level_info->num_levels; i++) { 324 DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz, 325 pp_clks->data[i].voltage_in_mv); 326 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; 327 clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv; 328 } 329 } 330 331 bool dm_pp_get_clock_levels_by_type( 332 const struct dc_context *ctx, 333 enum dm_pp_clock_type clk_type, 334 struct dm_pp_clock_levels *dc_clks) 335 { 336 struct amdgpu_device *adev = ctx->driver_context; 337 void *pp_handle = adev->powerplay.pp_handle; 338 struct amd_pp_clocks pp_clks = { 0 }; 339 struct amd_pp_simple_clock_info validation_clks = { 0 }; 340 uint32_t i; 341 342 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) { 343 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, 344 dc_to_pp_clock_type(clk_type), &pp_clks)) { 345 /* Error in pplib. Provide default values. */ 346 get_default_clock_levels(clk_type, dc_clks); 347 return true; 348 } 349 } 350 351 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); 352 353 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { 354 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( 355 pp_handle, &validation_clks)) { 356 /* Error in pplib. Provide default values. */ 357 DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); 358 validation_clks.engine_max_clock = 72000; 359 validation_clks.memory_max_clock = 80000; 360 validation_clks.level = 0; 361 } 362 } 363 364 DRM_INFO("DM_PPLIB: Validation clocks:\n"); 365 DRM_INFO("DM_PPLIB: engine_max_clock: %d\n", 366 validation_clks.engine_max_clock); 367 DRM_INFO("DM_PPLIB: memory_max_clock: %d\n", 368 validation_clks.memory_max_clock); 369 DRM_INFO("DM_PPLIB: level : %d\n", 370 validation_clks.level); 371 372 /* Translate 10 kHz to kHz. */ 373 validation_clks.engine_max_clock *= 10; 374 validation_clks.memory_max_clock *= 10; 375 376 /* Determine the highest non-boosted level from the Validation Clocks */ 377 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { 378 for (i = 0; i < dc_clks->num_levels; i++) { 379 if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { 380 /* This clock is higher the validation clock. 381 * Than means the previous one is the highest 382 * non-boosted one. */ 383 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", 384 dc_clks->num_levels, i); 385 dc_clks->num_levels = i > 0 ? i : 1; 386 break; 387 } 388 } 389 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { 390 for (i = 0; i < dc_clks->num_levels; i++) { 391 if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) { 392 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n", 393 dc_clks->num_levels, i); 394 dc_clks->num_levels = i > 0 ? i : 1; 395 break; 396 } 397 } 398 } 399 400 return true; 401 } 402 403 bool dm_pp_get_clock_levels_by_type_with_latency( 404 const struct dc_context *ctx, 405 enum dm_pp_clock_type clk_type, 406 struct dm_pp_clock_levels_with_latency *clk_level_info) 407 { 408 struct amdgpu_device *adev = ctx->driver_context; 409 void *pp_handle = adev->powerplay.pp_handle; 410 struct pp_clock_levels_with_latency pp_clks = { 0 }; 411 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 412 int ret; 413 414 if (pp_funcs && pp_funcs->get_clock_by_type_with_latency) { 415 ret = pp_funcs->get_clock_by_type_with_latency(pp_handle, 416 dc_to_pp_clock_type(clk_type), 417 &pp_clks); 418 if (ret) 419 return false; 420 } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) { 421 if (smu_get_clock_by_type_with_latency(&adev->smu, 422 dc_to_smu_clock_type(clk_type), 423 &pp_clks)) 424 return false; 425 } 426 427 428 pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); 429 430 return true; 431 } 432 433 bool dm_pp_get_clock_levels_by_type_with_voltage( 434 const struct dc_context *ctx, 435 enum dm_pp_clock_type clk_type, 436 struct dm_pp_clock_levels_with_voltage *clk_level_info) 437 { 438 struct amdgpu_device *adev = ctx->driver_context; 439 void *pp_handle = adev->powerplay.pp_handle; 440 struct pp_clock_levels_with_voltage pp_clk_info = {0}; 441 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 442 int ret; 443 444 if (pp_funcs && pp_funcs->get_clock_by_type_with_voltage) { 445 ret = pp_funcs->get_clock_by_type_with_voltage(pp_handle, 446 dc_to_pp_clock_type(clk_type), 447 &pp_clk_info); 448 if (ret) 449 return false; 450 } 451 452 pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type); 453 454 return true; 455 } 456 457 bool dm_pp_notify_wm_clock_changes( 458 const struct dc_context *ctx, 459 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) 460 { 461 struct amdgpu_device *adev = ctx->driver_context; 462 void *pp_handle = adev->powerplay.pp_handle; 463 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 464 465 if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) { 466 if (!pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, 467 (void *)wm_with_clock_ranges)) 468 return true; 469 } 470 471 return false; 472 } 473 474 bool dm_pp_apply_power_level_change_request( 475 const struct dc_context *ctx, 476 struct dm_pp_power_level_change_request *level_change_req) 477 { 478 /* TODO: to be implemented */ 479 return false; 480 } 481 482 bool dm_pp_apply_clock_for_voltage_request( 483 const struct dc_context *ctx, 484 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req) 485 { 486 struct amdgpu_device *adev = ctx->driver_context; 487 struct pp_display_clock_request pp_clock_request = {0}; 488 int ret = 0; 489 490 pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type); 491 pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz; 492 493 if (!pp_clock_request.clock_type) 494 return false; 495 496 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_clock_voltage_request) 497 ret = adev->powerplay.pp_funcs->display_clock_voltage_request( 498 adev->powerplay.pp_handle, 499 &pp_clock_request); 500 else if (adev->smu.ppt_funcs && 501 adev->smu.ppt_funcs->display_clock_voltage_request) 502 ret = smu_display_clock_voltage_request(&adev->smu, 503 &pp_clock_request); 504 if (ret) 505 return false; 506 return true; 507 } 508 509 bool dm_pp_get_static_clocks( 510 const struct dc_context *ctx, 511 struct dm_pp_static_clock_info *static_clk_info) 512 { 513 struct amdgpu_device *adev = ctx->driver_context; 514 struct amd_pp_clock_info pp_clk_info = {0}; 515 int ret = 0; 516 517 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_current_clocks) 518 ret = adev->powerplay.pp_funcs->get_current_clocks( 519 adev->powerplay.pp_handle, 520 &pp_clk_info); 521 else 522 return false; 523 if (ret) 524 return false; 525 526 static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state); 527 static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10; 528 static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10; 529 530 return true; 531 } 532 533 void pp_rv_set_wm_ranges(struct pp_smu *pp, 534 struct pp_smu_wm_range_sets *ranges) 535 { 536 const struct dc_context *ctx = pp->dm; 537 struct amdgpu_device *adev = ctx->driver_context; 538 void *pp_handle = adev->powerplay.pp_handle; 539 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 540 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; 541 struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges; 542 struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges; 543 int32_t i; 544 545 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets; 546 wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets; 547 548 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) { 549 if (ranges->reader_wm_sets[i].wm_inst > 3) 550 wm_dce_clocks[i].wm_set_id = WM_SET_A; 551 else 552 wm_dce_clocks[i].wm_set_id = 553 ranges->reader_wm_sets[i].wm_inst; 554 wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz = 555 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000; 556 wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz = 557 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000; 558 wm_dce_clocks[i].wm_max_mem_clk_in_khz = 559 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000; 560 wm_dce_clocks[i].wm_min_mem_clk_in_khz = 561 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; 562 } 563 564 for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) { 565 if (ranges->writer_wm_sets[i].wm_inst > 3) 566 wm_soc_clocks[i].wm_set_id = WM_SET_A; 567 else 568 wm_soc_clocks[i].wm_set_id = 569 ranges->writer_wm_sets[i].wm_inst; 570 wm_soc_clocks[i].wm_max_socclk_clk_in_khz = 571 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000; 572 wm_soc_clocks[i].wm_min_socclk_clk_in_khz = 573 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; 574 wm_soc_clocks[i].wm_max_mem_clk_in_khz = 575 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000; 576 wm_soc_clocks[i].wm_min_mem_clk_in_khz = 577 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; 578 } 579 580 if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) 581 pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, 582 &wm_with_clock_ranges); 583 } 584 585 void pp_rv_set_pme_wa_enable(struct pp_smu *pp) 586 { 587 const struct dc_context *ctx = pp->dm; 588 struct amdgpu_device *adev = ctx->driver_context; 589 void *pp_handle = adev->powerplay.pp_handle; 590 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 591 592 if (pp_funcs && pp_funcs->notify_smu_enable_pwe) 593 pp_funcs->notify_smu_enable_pwe(pp_handle); 594 } 595 596 void pp_rv_set_active_display_count(struct pp_smu *pp, int count) 597 { 598 const struct dc_context *ctx = pp->dm; 599 struct amdgpu_device *adev = ctx->driver_context; 600 void *pp_handle = adev->powerplay.pp_handle; 601 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 602 603 if (!pp_funcs || !pp_funcs->set_active_display_count) 604 return; 605 606 pp_funcs->set_active_display_count(pp_handle, count); 607 } 608 609 void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) 610 { 611 const struct dc_context *ctx = pp->dm; 612 struct amdgpu_device *adev = ctx->driver_context; 613 void *pp_handle = adev->powerplay.pp_handle; 614 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 615 616 if (!pp_funcs || !pp_funcs->set_min_deep_sleep_dcefclk) 617 return; 618 619 pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock); 620 } 621 622 void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) 623 { 624 const struct dc_context *ctx = pp->dm; 625 struct amdgpu_device *adev = ctx->driver_context; 626 void *pp_handle = adev->powerplay.pp_handle; 627 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 628 629 if (!pp_funcs || !pp_funcs->set_hard_min_dcefclk_by_freq) 630 return; 631 632 pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock); 633 } 634 635 void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) 636 { 637 const struct dc_context *ctx = pp->dm; 638 struct amdgpu_device *adev = ctx->driver_context; 639 void *pp_handle = adev->powerplay.pp_handle; 640 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 641 642 if (!pp_funcs || !pp_funcs->set_hard_min_fclk_by_freq) 643 return; 644 645 pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz); 646 } 647 648 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, 649 struct pp_smu_wm_range_sets *ranges) 650 { 651 const struct dc_context *ctx = pp->dm; 652 struct amdgpu_device *adev = ctx->driver_context; 653 654 smu_set_watermarks_for_clock_ranges(&adev->smu, ranges); 655 656 return PP_SMU_RESULT_OK; 657 } 658 659 enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp) 660 { 661 const struct dc_context *ctx = pp->dm; 662 struct amdgpu_device *adev = ctx->driver_context; 663 struct smu_context *smu = &adev->smu; 664 665 if (!smu->ppt_funcs) 666 return PP_SMU_RESULT_UNSUPPORTED; 667 668 /* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL; 1: fail */ 669 if (smu_set_azalia_d3_pme(smu)) 670 return PP_SMU_RESULT_FAIL; 671 672 return PP_SMU_RESULT_OK; 673 } 674 675 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) 676 { 677 const struct dc_context *ctx = pp->dm; 678 struct amdgpu_device *adev = ctx->driver_context; 679 struct smu_context *smu = &adev->smu; 680 681 if (!smu->ppt_funcs) 682 return PP_SMU_RESULT_UNSUPPORTED; 683 684 /* 0: successful or smu.ppt_funcs->set_display_count = NULL; 1: fail */ 685 if (smu_set_display_count(smu, count)) 686 return PP_SMU_RESULT_FAIL; 687 688 return PP_SMU_RESULT_OK; 689 } 690 691 static enum pp_smu_status 692 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) 693 { 694 const struct dc_context *ctx = pp->dm; 695 struct amdgpu_device *adev = ctx->driver_context; 696 struct smu_context *smu = &adev->smu; 697 698 if (!smu->ppt_funcs) 699 return PP_SMU_RESULT_UNSUPPORTED; 700 701 /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */ 702 if (smu_set_deep_sleep_dcefclk(smu, mhz)) 703 return PP_SMU_RESULT_FAIL; 704 705 return PP_SMU_RESULT_OK; 706 } 707 708 static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq( 709 struct pp_smu *pp, int mhz) 710 { 711 const struct dc_context *ctx = pp->dm; 712 struct amdgpu_device *adev = ctx->driver_context; 713 struct smu_context *smu = &adev->smu; 714 struct pp_display_clock_request clock_req; 715 716 if (!smu->ppt_funcs) 717 return PP_SMU_RESULT_UNSUPPORTED; 718 719 clock_req.clock_type = amd_pp_dcef_clock; 720 clock_req.clock_freq_in_khz = mhz * 1000; 721 722 /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL 723 * 1: fail 724 */ 725 if (smu_display_clock_voltage_request(smu, &clock_req)) 726 return PP_SMU_RESULT_FAIL; 727 728 return PP_SMU_RESULT_OK; 729 } 730 731 static enum pp_smu_status 732 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) 733 { 734 const struct dc_context *ctx = pp->dm; 735 struct amdgpu_device *adev = ctx->driver_context; 736 struct smu_context *smu = &adev->smu; 737 struct pp_display_clock_request clock_req; 738 739 if (!smu->ppt_funcs) 740 return PP_SMU_RESULT_UNSUPPORTED; 741 742 clock_req.clock_type = amd_pp_mem_clock; 743 clock_req.clock_freq_in_khz = mhz * 1000; 744 745 /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL 746 * 1: fail 747 */ 748 if (smu_display_clock_voltage_request(smu, &clock_req)) 749 return PP_SMU_RESULT_FAIL; 750 751 return PP_SMU_RESULT_OK; 752 } 753 754 static enum pp_smu_status pp_nv_set_pstate_handshake_support( 755 struct pp_smu *pp, bool pstate_handshake_supported) 756 { 757 const struct dc_context *ctx = pp->dm; 758 struct amdgpu_device *adev = ctx->driver_context; 759 struct smu_context *smu = &adev->smu; 760 761 if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported)) 762 return PP_SMU_RESULT_FAIL; 763 764 return PP_SMU_RESULT_OK; 765 } 766 767 static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, 768 enum pp_smu_nv_clock_id clock_id, int mhz) 769 { 770 const struct dc_context *ctx = pp->dm; 771 struct amdgpu_device *adev = ctx->driver_context; 772 struct smu_context *smu = &adev->smu; 773 struct pp_display_clock_request clock_req; 774 775 if (!smu->ppt_funcs) 776 return PP_SMU_RESULT_UNSUPPORTED; 777 778 switch (clock_id) { 779 case PP_SMU_NV_DISPCLK: 780 clock_req.clock_type = amd_pp_disp_clock; 781 break; 782 case PP_SMU_NV_PHYCLK: 783 clock_req.clock_type = amd_pp_phy_clock; 784 break; 785 case PP_SMU_NV_PIXELCLK: 786 clock_req.clock_type = amd_pp_pixel_clock; 787 break; 788 default: 789 break; 790 } 791 clock_req.clock_freq_in_khz = mhz * 1000; 792 793 /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL 794 * 1: fail 795 */ 796 if (smu_display_clock_voltage_request(smu, &clock_req)) 797 return PP_SMU_RESULT_FAIL; 798 799 return PP_SMU_RESULT_OK; 800 } 801 802 static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks( 803 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) 804 { 805 const struct dc_context *ctx = pp->dm; 806 struct amdgpu_device *adev = ctx->driver_context; 807 struct smu_context *smu = &adev->smu; 808 809 if (!smu->ppt_funcs) 810 return PP_SMU_RESULT_UNSUPPORTED; 811 812 if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 813 return PP_SMU_RESULT_UNSUPPORTED; 814 815 if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks)) 816 return PP_SMU_RESULT_OK; 817 818 return PP_SMU_RESULT_FAIL; 819 } 820 821 static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, 822 unsigned int *clock_values_in_khz, unsigned int *num_states) 823 { 824 const struct dc_context *ctx = pp->dm; 825 struct amdgpu_device *adev = ctx->driver_context; 826 struct smu_context *smu = &adev->smu; 827 828 if (!smu->ppt_funcs) 829 return PP_SMU_RESULT_UNSUPPORTED; 830 831 if (!smu->ppt_funcs->get_uclk_dpm_states) 832 return PP_SMU_RESULT_UNSUPPORTED; 833 834 if (!smu_get_uclk_dpm_states(smu, 835 clock_values_in_khz, num_states)) 836 return PP_SMU_RESULT_OK; 837 838 return PP_SMU_RESULT_FAIL; 839 } 840 841 static enum pp_smu_status pp_rn_get_dpm_clock_table( 842 struct pp_smu *pp, struct dpm_clocks *clock_table) 843 { 844 const struct dc_context *ctx = pp->dm; 845 struct amdgpu_device *adev = ctx->driver_context; 846 struct smu_context *smu = &adev->smu; 847 848 if (!smu->ppt_funcs) 849 return PP_SMU_RESULT_UNSUPPORTED; 850 851 if (!smu->ppt_funcs->get_dpm_clock_table) 852 return PP_SMU_RESULT_UNSUPPORTED; 853 854 if (!smu_get_dpm_clock_table(smu, clock_table)) 855 return PP_SMU_RESULT_OK; 856 857 return PP_SMU_RESULT_FAIL; 858 } 859 860 static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp, 861 struct pp_smu_wm_range_sets *ranges) 862 { 863 const struct dc_context *ctx = pp->dm; 864 struct amdgpu_device *adev = ctx->driver_context; 865 866 smu_set_watermarks_for_clock_ranges(&adev->smu, ranges); 867 868 return PP_SMU_RESULT_OK; 869 } 870 871 void dm_pp_get_funcs( 872 struct dc_context *ctx, 873 struct pp_smu_funcs *funcs) 874 { 875 switch (ctx->dce_version) { 876 case DCN_VERSION_1_0: 877 case DCN_VERSION_1_01: 878 funcs->ctx.ver = PP_SMU_VER_RV; 879 funcs->rv_funcs.pp_smu.dm = ctx; 880 funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges; 881 funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable; 882 funcs->rv_funcs.set_display_count = 883 pp_rv_set_active_display_count; 884 funcs->rv_funcs.set_min_deep_sleep_dcfclk = 885 pp_rv_set_min_deep_sleep_dcfclk; 886 funcs->rv_funcs.set_hard_min_dcfclk_by_freq = 887 pp_rv_set_hard_min_dcefclk_by_freq; 888 funcs->rv_funcs.set_hard_min_fclk_by_freq = 889 pp_rv_set_hard_min_fclk_by_freq; 890 break; 891 case DCN_VERSION_2_0: 892 funcs->ctx.ver = PP_SMU_VER_NV; 893 funcs->nv_funcs.pp_smu.dm = ctx; 894 funcs->nv_funcs.set_display_count = pp_nv_set_display_count; 895 funcs->nv_funcs.set_hard_min_dcfclk_by_freq = 896 pp_nv_set_hard_min_dcefclk_by_freq; 897 funcs->nv_funcs.set_min_deep_sleep_dcfclk = 898 pp_nv_set_min_deep_sleep_dcfclk; 899 funcs->nv_funcs.set_voltage_by_freq = 900 pp_nv_set_voltage_by_freq; 901 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges; 902 903 /* todo set_pme_wa_enable cause 4k@6ohz display not light up */ 904 funcs->nv_funcs.set_pme_wa_enable = NULL; 905 /* todo debug waring message */ 906 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq; 907 /* todo compare data with window driver*/ 908 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks; 909 /*todo compare data with window driver */ 910 funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states; 911 funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support; 912 break; 913 914 case DCN_VERSION_2_1: 915 funcs->ctx.ver = PP_SMU_VER_RN; 916 funcs->rn_funcs.pp_smu.dm = ctx; 917 funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges; 918 funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table; 919 break; 920 default: 921 DRM_ERROR("smu version is not supported !\n"); 922 break; 923 } 924 } 925