1f7c1ed34SMikita Lipski /*
2f7c1ed34SMikita Lipski * Copyright 2018 Advanced Micro Devices, Inc.
3f7c1ed34SMikita Lipski *
4f7c1ed34SMikita Lipski * Permission is hereby granted, free of charge, to any person obtaining a
5f7c1ed34SMikita Lipski * copy of this software and associated documentation files (the "Software"),
6f7c1ed34SMikita Lipski * to deal in the Software without restriction, including without limitation
7f7c1ed34SMikita Lipski * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f7c1ed34SMikita Lipski * and/or sell copies of the Software, and to permit persons to whom the
9f7c1ed34SMikita Lipski * Software is furnished to do so, subject to the following conditions:
10f7c1ed34SMikita Lipski *
11f7c1ed34SMikita Lipski * The above copyright notice and this permission notice shall be included in
12f7c1ed34SMikita Lipski * all copies or substantial portions of the Software.
13f7c1ed34SMikita Lipski *
14f7c1ed34SMikita Lipski * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f7c1ed34SMikita Lipski * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f7c1ed34SMikita Lipski * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f7c1ed34SMikita Lipski * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f7c1ed34SMikita Lipski * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f7c1ed34SMikita Lipski * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f7c1ed34SMikita Lipski * OTHER DEALINGS IN THE SOFTWARE.
21f7c1ed34SMikita Lipski *
22f7c1ed34SMikita Lipski * Authors: AMD
23f7c1ed34SMikita Lipski */
24f7c1ed34SMikita Lipski #include <linux/string.h>
25f7c1ed34SMikita Lipski #include <linux/acpi.h>
26f7c1ed34SMikita Lipski
27fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h>
28f7c1ed34SMikita Lipski #include <drm/amdgpu_drm.h>
29f7c1ed34SMikita Lipski #include "dm_services.h"
30f7c1ed34SMikita Lipski #include "amdgpu.h"
31f7c1ed34SMikita Lipski #include "amdgpu_dm.h"
32f7c1ed34SMikita Lipski #include "amdgpu_dm_irq.h"
33f7c1ed34SMikita Lipski #include "amdgpu_pm.h"
34f7c1ed34SMikita Lipski #include "dm_pp_smu.h"
35f7c1ed34SMikita Lipski
dm_pp_apply_display_requirements(const struct dc_context * ctx,const struct dm_pp_display_configuration * pp_display_cfg)36f7c1ed34SMikita Lipski bool dm_pp_apply_display_requirements(
37f7c1ed34SMikita Lipski const struct dc_context *ctx,
38f7c1ed34SMikita Lipski const struct dm_pp_display_configuration *pp_display_cfg)
39f7c1ed34SMikita Lipski {
40f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
41d4d5eaceSrex zhu int i;
42f7c1ed34SMikita Lipski
43f7c1ed34SMikita Lipski if (adev->pm.dpm_enabled) {
44f7c1ed34SMikita Lipski
45f7c1ed34SMikita Lipski memset(&adev->pm.pm_display_cfg, 0,
46f7c1ed34SMikita Lipski sizeof(adev->pm.pm_display_cfg));
47f7c1ed34SMikita Lipski
48f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.cpu_cc6_disable =
49f7c1ed34SMikita Lipski pp_display_cfg->cpu_cc6_disable;
50f7c1ed34SMikita Lipski
51f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.cpu_pstate_disable =
52f7c1ed34SMikita Lipski pp_display_cfg->cpu_pstate_disable;
53f7c1ed34SMikita Lipski
54f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.cpu_pstate_separation_time =
55f7c1ed34SMikita Lipski pp_display_cfg->cpu_pstate_separation_time;
56f7c1ed34SMikita Lipski
57f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.nb_pstate_switch_disable =
58f7c1ed34SMikita Lipski pp_display_cfg->nb_pstate_switch_disable;
59f7c1ed34SMikita Lipski
60f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.num_display =
61f7c1ed34SMikita Lipski pp_display_cfg->display_count;
62f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.num_path_including_non_display =
63f7c1ed34SMikita Lipski pp_display_cfg->display_count;
64f7c1ed34SMikita Lipski
65f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.min_core_set_clock =
66f7c1ed34SMikita Lipski pp_display_cfg->min_engine_clock_khz/10;
67f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
68f7c1ed34SMikita Lipski pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
69f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.min_mem_set_clock =
70f7c1ed34SMikita Lipski pp_display_cfg->min_memory_clock_khz/10;
71f7c1ed34SMikita Lipski
723180fb67Srex zhu adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk =
733180fb67Srex zhu pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
743180fb67Srex zhu adev->pm.pm_display_cfg.min_dcef_set_clk =
753180fb67Srex zhu pp_display_cfg->min_dcfclock_khz/10;
763180fb67Srex zhu
77f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.multi_monitor_in_sync =
78f7c1ed34SMikita Lipski pp_display_cfg->all_displays_in_sync;
79f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.min_vblank_time =
80f7c1ed34SMikita Lipski pp_display_cfg->avail_mclk_switch_time_us;
81f7c1ed34SMikita Lipski
82f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.display_clk =
83f7c1ed34SMikita Lipski pp_display_cfg->disp_clk_khz/10;
84f7c1ed34SMikita Lipski
85f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
86f7c1ed34SMikita Lipski pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
87f7c1ed34SMikita Lipski
88f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
89f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.line_time_in_us =
90f7c1ed34SMikita Lipski pp_display_cfg->line_time_in_us;
91f7c1ed34SMikita Lipski
92f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
93f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.crossfire_display_index = -1;
94f7c1ed34SMikita Lipski adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
95f7c1ed34SMikita Lipski
96d4d5eaceSrex zhu for (i = 0; i < pp_display_cfg->display_count; i++) {
97d4d5eaceSrex zhu const struct dm_pp_single_disp_config *dc_cfg =
98d4d5eaceSrex zhu &pp_display_cfg->disp_configs[i];
99d4d5eaceSrex zhu adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
100d4d5eaceSrex zhu }
101d4d5eaceSrex zhu
10213f5dbd6SEvan Quan amdgpu_dpm_display_configuration_change(adev, &adev->pm.pm_display_cfg);
10340d0ebd9SRex Zhu
10484176663SEvan Quan amdgpu_dpm_compute_clocks(adev);
105f7c1ed34SMikita Lipski }
106f7c1ed34SMikita Lipski
107f7c1ed34SMikita Lipski return true;
108f7c1ed34SMikita Lipski }
109f7c1ed34SMikita Lipski
get_default_clock_levels(enum dm_pp_clock_type clk_type,struct dm_pp_clock_levels * clks)110f7c1ed34SMikita Lipski static void get_default_clock_levels(
111f7c1ed34SMikita Lipski enum dm_pp_clock_type clk_type,
112f7c1ed34SMikita Lipski struct dm_pp_clock_levels *clks)
113f7c1ed34SMikita Lipski {
114f7c1ed34SMikita Lipski uint32_t disp_clks_in_khz[6] = {
115f7c1ed34SMikita Lipski 300000, 400000, 496560, 626090, 685720, 757900 };
116f7c1ed34SMikita Lipski uint32_t sclks_in_khz[6] = {
117f7c1ed34SMikita Lipski 300000, 360000, 423530, 514290, 626090, 720000 };
118f7c1ed34SMikita Lipski uint32_t mclks_in_khz[2] = { 333000, 800000 };
119f7c1ed34SMikita Lipski
120f7c1ed34SMikita Lipski switch (clk_type) {
121f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
122f7c1ed34SMikita Lipski clks->num_levels = 6;
123f7c1ed34SMikita Lipski memmove(clks->clocks_in_khz, disp_clks_in_khz,
124f7c1ed34SMikita Lipski sizeof(disp_clks_in_khz));
125f7c1ed34SMikita Lipski break;
126f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_ENGINE_CLK:
127f7c1ed34SMikita Lipski clks->num_levels = 6;
128f7c1ed34SMikita Lipski memmove(clks->clocks_in_khz, sclks_in_khz,
129f7c1ed34SMikita Lipski sizeof(sclks_in_khz));
130f7c1ed34SMikita Lipski break;
131f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_MEMORY_CLK:
132f7c1ed34SMikita Lipski clks->num_levels = 2;
133f7c1ed34SMikita Lipski memmove(clks->clocks_in_khz, mclks_in_khz,
134f7c1ed34SMikita Lipski sizeof(mclks_in_khz));
135f7c1ed34SMikita Lipski break;
136f7c1ed34SMikita Lipski default:
137f7c1ed34SMikita Lipski clks->num_levels = 0;
138f7c1ed34SMikita Lipski break;
139f7c1ed34SMikita Lipski }
140f7c1ed34SMikita Lipski }
141f7c1ed34SMikita Lipski
dc_to_pp_clock_type(enum dm_pp_clock_type dm_pp_clk_type)142f7c1ed34SMikita Lipski static enum amd_pp_clock_type dc_to_pp_clock_type(
143f7c1ed34SMikita Lipski enum dm_pp_clock_type dm_pp_clk_type)
144f7c1ed34SMikita Lipski {
145f7c1ed34SMikita Lipski enum amd_pp_clock_type amd_pp_clk_type = 0;
146f7c1ed34SMikita Lipski
147f7c1ed34SMikita Lipski switch (dm_pp_clk_type) {
148f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
149f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_disp_clock;
150f7c1ed34SMikita Lipski break;
151f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_ENGINE_CLK:
152f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_sys_clock;
153f7c1ed34SMikita Lipski break;
154f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_MEMORY_CLK:
155f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_mem_clock;
156f7c1ed34SMikita Lipski break;
157f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_DCEFCLK:
158f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_dcef_clock;
159f7c1ed34SMikita Lipski break;
160f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_DCFCLK:
161f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_dcf_clock;
162f7c1ed34SMikita Lipski break;
163f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_PIXELCLK:
164f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_pixel_clock;
165f7c1ed34SMikita Lipski break;
166f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_FCLK:
167f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_f_clock;
168f7c1ed34SMikita Lipski break;
169f7c1ed34SMikita Lipski case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
17066917e56Srex zhu amd_pp_clk_type = amd_pp_phy_clock;
17166917e56Srex zhu break;
17266917e56Srex zhu case DM_PP_CLOCK_TYPE_DPPCLK:
173f7c1ed34SMikita Lipski amd_pp_clk_type = amd_pp_dpp_clock;
174f7c1ed34SMikita Lipski break;
175f7c1ed34SMikita Lipski default:
176f7c1ed34SMikita Lipski DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
177f7c1ed34SMikita Lipski dm_pp_clk_type);
178f7c1ed34SMikita Lipski break;
179f7c1ed34SMikita Lipski }
180f7c1ed34SMikita Lipski
181f7c1ed34SMikita Lipski return amd_pp_clk_type;
182f7c1ed34SMikita Lipski }
183f7c1ed34SMikita Lipski
pp_to_dc_powerlevel_state(enum PP_DAL_POWERLEVEL max_clocks_state)184c2c09ed5SMikita Lipski static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
185c2c09ed5SMikita Lipski enum PP_DAL_POWERLEVEL max_clocks_state)
186c2c09ed5SMikita Lipski {
187c2c09ed5SMikita Lipski switch (max_clocks_state) {
188c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_0:
189c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
190c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_1:
191c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
192c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_2:
193c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
194c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_3:
195c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
196c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_4:
197c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
198c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_5:
199c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
200c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_6:
201c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
202c2c09ed5SMikita Lipski case PP_DAL_POWERLEVEL_7:
203c2c09ed5SMikita Lipski return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
204c2c09ed5SMikita Lipski default:
205c2c09ed5SMikita Lipski DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
206c2c09ed5SMikita Lipski max_clocks_state);
207c2c09ed5SMikita Lipski return DM_PP_CLOCKS_STATE_INVALID;
208c2c09ed5SMikita Lipski }
209c2c09ed5SMikita Lipski }
210c2c09ed5SMikita Lipski
pp_to_dc_clock_levels(const struct amd_pp_clocks * pp_clks,struct dm_pp_clock_levels * dc_clks,enum dm_pp_clock_type dc_clk_type)211f7c1ed34SMikita Lipski static void pp_to_dc_clock_levels(
212f7c1ed34SMikita Lipski const struct amd_pp_clocks *pp_clks,
213f7c1ed34SMikita Lipski struct dm_pp_clock_levels *dc_clks,
214f7c1ed34SMikita Lipski enum dm_pp_clock_type dc_clk_type)
215f7c1ed34SMikita Lipski {
216f7c1ed34SMikita Lipski uint32_t i;
217f7c1ed34SMikita Lipski
218f7c1ed34SMikita Lipski if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
219f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
220f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
221f7c1ed34SMikita Lipski pp_clks->count,
222f7c1ed34SMikita Lipski DM_PP_MAX_CLOCK_LEVELS);
223f7c1ed34SMikita Lipski
224f7c1ed34SMikita Lipski dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
225f7c1ed34SMikita Lipski } else
226f7c1ed34SMikita Lipski dc_clks->num_levels = pp_clks->count;
227f7c1ed34SMikita Lipski
228f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: values for %s clock\n",
229f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
230f7c1ed34SMikita Lipski
231f7c1ed34SMikita Lipski for (i = 0; i < dc_clks->num_levels; i++) {
232f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
23323ec3d14SRex Zhu dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
234f7c1ed34SMikita Lipski }
235f7c1ed34SMikita Lipski }
236f7c1ed34SMikita Lipski
pp_to_dc_clock_levels_with_latency(const struct pp_clock_levels_with_latency * pp_clks,struct dm_pp_clock_levels_with_latency * clk_level_info,enum dm_pp_clock_type dc_clk_type)237f7c1ed34SMikita Lipski static void pp_to_dc_clock_levels_with_latency(
238f7c1ed34SMikita Lipski const struct pp_clock_levels_with_latency *pp_clks,
239f7c1ed34SMikita Lipski struct dm_pp_clock_levels_with_latency *clk_level_info,
240f7c1ed34SMikita Lipski enum dm_pp_clock_type dc_clk_type)
241f7c1ed34SMikita Lipski {
242f7c1ed34SMikita Lipski uint32_t i;
243f7c1ed34SMikita Lipski
244f7c1ed34SMikita Lipski if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
245f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
246f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
247f7c1ed34SMikita Lipski pp_clks->num_levels,
248f7c1ed34SMikita Lipski DM_PP_MAX_CLOCK_LEVELS);
249f7c1ed34SMikita Lipski
250f7c1ed34SMikita Lipski clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
251f7c1ed34SMikita Lipski } else
252f7c1ed34SMikita Lipski clk_level_info->num_levels = pp_clks->num_levels;
253f7c1ed34SMikita Lipski
254f7c1ed34SMikita Lipski DRM_DEBUG("DM_PPLIB: values for %s clock\n",
255f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
256f7c1ed34SMikita Lipski
257f7c1ed34SMikita Lipski for (i = 0; i < clk_level_info->num_levels; i++) {
25823ec3d14SRex Zhu DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
25923ec3d14SRex Zhu clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
260f7c1ed34SMikita Lipski clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
261f7c1ed34SMikita Lipski }
262f7c1ed34SMikita Lipski }
263f7c1ed34SMikita Lipski
pp_to_dc_clock_levels_with_voltage(const struct pp_clock_levels_with_voltage * pp_clks,struct dm_pp_clock_levels_with_voltage * clk_level_info,enum dm_pp_clock_type dc_clk_type)264f7c1ed34SMikita Lipski static void pp_to_dc_clock_levels_with_voltage(
265f7c1ed34SMikita Lipski const struct pp_clock_levels_with_voltage *pp_clks,
266f7c1ed34SMikita Lipski struct dm_pp_clock_levels_with_voltage *clk_level_info,
267f7c1ed34SMikita Lipski enum dm_pp_clock_type dc_clk_type)
268f7c1ed34SMikita Lipski {
269f7c1ed34SMikita Lipski uint32_t i;
270f7c1ed34SMikita Lipski
271f7c1ed34SMikita Lipski if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
272f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
273f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
274f7c1ed34SMikita Lipski pp_clks->num_levels,
275f7c1ed34SMikita Lipski DM_PP_MAX_CLOCK_LEVELS);
276f7c1ed34SMikita Lipski
277f7c1ed34SMikita Lipski clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
278f7c1ed34SMikita Lipski } else
279f7c1ed34SMikita Lipski clk_level_info->num_levels = pp_clks->num_levels;
280f7c1ed34SMikita Lipski
281f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: values for %s clock\n",
282f7c1ed34SMikita Lipski DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
283f7c1ed34SMikita Lipski
284f7c1ed34SMikita Lipski for (i = 0; i < clk_level_info->num_levels; i++) {
2855f0f531cSPaul Menzel DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
2865f0f531cSPaul Menzel pp_clks->data[i].voltage_in_mv);
28723ec3d14SRex Zhu clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
288f7c1ed34SMikita Lipski clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
289f7c1ed34SMikita Lipski }
290f7c1ed34SMikita Lipski }
291f7c1ed34SMikita Lipski
dm_pp_get_clock_levels_by_type(const struct dc_context * ctx,enum dm_pp_clock_type clk_type,struct dm_pp_clock_levels * dc_clks)292f7c1ed34SMikita Lipski bool dm_pp_get_clock_levels_by_type(
293f7c1ed34SMikita Lipski const struct dc_context *ctx,
294f7c1ed34SMikita Lipski enum dm_pp_clock_type clk_type,
295f7c1ed34SMikita Lipski struct dm_pp_clock_levels *dc_clks)
296f7c1ed34SMikita Lipski {
297f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
298f7c1ed34SMikita Lipski struct amd_pp_clocks pp_clks = { 0 };
299f7c1ed34SMikita Lipski struct amd_pp_simple_clock_info validation_clks = { 0 };
300f7c1ed34SMikita Lipski uint32_t i;
301f7c1ed34SMikita Lipski
30213f5dbd6SEvan Quan if (amdgpu_dpm_get_clock_by_type(adev,
303f7c1ed34SMikita Lipski dc_to_pp_clock_type(clk_type), &pp_clks)) {
304f7c1ed34SMikita Lipski /* Error in pplib. Provide default values. */
305ee9ea6d8SAlex Deucher get_default_clock_levels(clk_type, dc_clks);
306b3ea88feSHuang Rui return true;
307b3ea88feSHuang Rui }
308f7c1ed34SMikita Lipski
309f7c1ed34SMikita Lipski pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
310f7c1ed34SMikita Lipski
31113f5dbd6SEvan Quan if (amdgpu_dpm_get_display_mode_validation_clks(adev, &validation_clks)) {
312f7c1ed34SMikita Lipski /* Error in pplib. Provide default values. */
313f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
314f7c1ed34SMikita Lipski validation_clks.engine_max_clock = 72000;
315f7c1ed34SMikita Lipski validation_clks.memory_max_clock = 80000;
316f7c1ed34SMikita Lipski validation_clks.level = 0;
317f7c1ed34SMikita Lipski }
318f7c1ed34SMikita Lipski
319f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: Validation clocks:\n");
320f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
321f7c1ed34SMikita Lipski validation_clks.engine_max_clock);
322f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
323f7c1ed34SMikita Lipski validation_clks.memory_max_clock);
324f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: level : %d\n",
325f7c1ed34SMikita Lipski validation_clks.level);
326f7c1ed34SMikita Lipski
327f7c1ed34SMikita Lipski /* Translate 10 kHz to kHz. */
328f7c1ed34SMikita Lipski validation_clks.engine_max_clock *= 10;
329f7c1ed34SMikita Lipski validation_clks.memory_max_clock *= 10;
330f7c1ed34SMikita Lipski
331f7c1ed34SMikita Lipski /* Determine the highest non-boosted level from the Validation Clocks */
332f7c1ed34SMikita Lipski if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
333f7c1ed34SMikita Lipski for (i = 0; i < dc_clks->num_levels; i++) {
334f7c1ed34SMikita Lipski if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
335f7c1ed34SMikita Lipski /* This clock is higher the validation clock.
336f7c1ed34SMikita Lipski * Than means the previous one is the highest
337*7c62129bSSrinivasan Shanmugam * non-boosted one.
338*7c62129bSSrinivasan Shanmugam */
339f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
340f7c1ed34SMikita Lipski dc_clks->num_levels, i);
341f7c1ed34SMikita Lipski dc_clks->num_levels = i > 0 ? i : 1;
342f7c1ed34SMikita Lipski break;
343f7c1ed34SMikita Lipski }
344f7c1ed34SMikita Lipski }
345f7c1ed34SMikita Lipski } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
346f7c1ed34SMikita Lipski for (i = 0; i < dc_clks->num_levels; i++) {
347f7c1ed34SMikita Lipski if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
348f7c1ed34SMikita Lipski DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
349f7c1ed34SMikita Lipski dc_clks->num_levels, i);
350f7c1ed34SMikita Lipski dc_clks->num_levels = i > 0 ? i : 1;
351f7c1ed34SMikita Lipski break;
352f7c1ed34SMikita Lipski }
353f7c1ed34SMikita Lipski }
354f7c1ed34SMikita Lipski }
355f7c1ed34SMikita Lipski
356f7c1ed34SMikita Lipski return true;
357f7c1ed34SMikita Lipski }
358f7c1ed34SMikita Lipski
dm_pp_get_clock_levels_by_type_with_latency(const struct dc_context * ctx,enum dm_pp_clock_type clk_type,struct dm_pp_clock_levels_with_latency * clk_level_info)359f7c1ed34SMikita Lipski bool dm_pp_get_clock_levels_by_type_with_latency(
360f7c1ed34SMikita Lipski const struct dc_context *ctx,
361f7c1ed34SMikita Lipski enum dm_pp_clock_type clk_type,
362f7c1ed34SMikita Lipski struct dm_pp_clock_levels_with_latency *clk_level_info)
363f7c1ed34SMikita Lipski {
364f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
365f7c1ed34SMikita Lipski struct pp_clock_levels_with_latency pp_clks = { 0 };
366e5e4e223SHuang Rui int ret;
367f7c1ed34SMikita Lipski
36813f5dbd6SEvan Quan ret = amdgpu_dpm_get_clock_by_type_with_latency(adev,
369e5e4e223SHuang Rui dc_to_pp_clock_type(clk_type),
370e5e4e223SHuang Rui &pp_clks);
371e5e4e223SHuang Rui if (ret)
372f7c1ed34SMikita Lipski return false;
373e5e4e223SHuang Rui
374f7c1ed34SMikita Lipski pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
375f7c1ed34SMikita Lipski
376f7c1ed34SMikita Lipski return true;
377f7c1ed34SMikita Lipski }
378f7c1ed34SMikita Lipski
dm_pp_get_clock_levels_by_type_with_voltage(const struct dc_context * ctx,enum dm_pp_clock_type clk_type,struct dm_pp_clock_levels_with_voltage * clk_level_info)379f7c1ed34SMikita Lipski bool dm_pp_get_clock_levels_by_type_with_voltage(
380f7c1ed34SMikita Lipski const struct dc_context *ctx,
381f7c1ed34SMikita Lipski enum dm_pp_clock_type clk_type,
382f7c1ed34SMikita Lipski struct dm_pp_clock_levels_with_voltage *clk_level_info)
383f7c1ed34SMikita Lipski {
384f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
385f7c1ed34SMikita Lipski struct pp_clock_levels_with_voltage pp_clk_info = {0};
3861e33d4d4SHuang Rui int ret;
387f7c1ed34SMikita Lipski
38813f5dbd6SEvan Quan ret = amdgpu_dpm_get_clock_by_type_with_voltage(adev,
3891e33d4d4SHuang Rui dc_to_pp_clock_type(clk_type),
3901e33d4d4SHuang Rui &pp_clk_info);
3911e33d4d4SHuang Rui if (ret)
3926f059c64SRex Zhu return false;
393f7c1ed34SMikita Lipski
394f7c1ed34SMikita Lipski pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
395f7c1ed34SMikita Lipski
396f7c1ed34SMikita Lipski return true;
397f7c1ed34SMikita Lipski }
398f7c1ed34SMikita Lipski
dm_pp_notify_wm_clock_changes(const struct dc_context * ctx,struct dm_pp_wm_sets_with_clock_ranges * wm_with_clock_ranges)399f7c1ed34SMikita Lipski bool dm_pp_notify_wm_clock_changes(
400f7c1ed34SMikita Lipski const struct dc_context *ctx,
401f7c1ed34SMikita Lipski struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
402f7c1ed34SMikita Lipski {
403b03fd3e7SEvan Quan struct amdgpu_device *adev = ctx->driver_context;
404b03fd3e7SEvan Quan
405adc9da64SEvan Quan /*
406adc9da64SEvan Quan * Limit this watermark setting for Polaris for now
407adc9da64SEvan Quan * TODO: expand this to other ASICs
408adc9da64SEvan Quan */
40913f5dbd6SEvan Quan if ((adev->asic_type >= CHIP_POLARIS10) &&
41013f5dbd6SEvan Quan (adev->asic_type <= CHIP_VEGAM) &&
41113f5dbd6SEvan Quan !amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
412b03fd3e7SEvan Quan (void *)wm_with_clock_ranges))
413b03fd3e7SEvan Quan return true;
414b03fd3e7SEvan Quan
415f7c1ed34SMikita Lipski return false;
416f7c1ed34SMikita Lipski }
417f7c1ed34SMikita Lipski
dm_pp_apply_power_level_change_request(const struct dc_context * ctx,struct dm_pp_power_level_change_request * level_change_req)418f7c1ed34SMikita Lipski bool dm_pp_apply_power_level_change_request(
419f7c1ed34SMikita Lipski const struct dc_context *ctx,
420f7c1ed34SMikita Lipski struct dm_pp_power_level_change_request *level_change_req)
421f7c1ed34SMikita Lipski {
422f7c1ed34SMikita Lipski /* TODO: to be implemented */
423f7c1ed34SMikita Lipski return false;
424f7c1ed34SMikita Lipski }
425f7c1ed34SMikita Lipski
dm_pp_apply_clock_for_voltage_request(const struct dc_context * ctx,struct dm_pp_clock_for_voltage_req * clock_for_voltage_req)426f7c1ed34SMikita Lipski bool dm_pp_apply_clock_for_voltage_request(
427f7c1ed34SMikita Lipski const struct dc_context *ctx,
428f7c1ed34SMikita Lipski struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
429f7c1ed34SMikita Lipski {
430f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
431f7c1ed34SMikita Lipski struct pp_display_clock_request pp_clock_request = {0};
432f7c1ed34SMikita Lipski int ret = 0;
433f7c1ed34SMikita Lipski
434f7c1ed34SMikita Lipski pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
435f7c1ed34SMikita Lipski pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
436f7c1ed34SMikita Lipski
437f7c1ed34SMikita Lipski if (!pp_clock_request.clock_type)
438f7c1ed34SMikita Lipski return false;
439f7c1ed34SMikita Lipski
44013f5dbd6SEvan Quan ret = amdgpu_dpm_display_clock_voltage_request(adev, &pp_clock_request);
44113f5dbd6SEvan Quan if (ret && (ret != -EOPNOTSUPP))
442f7c1ed34SMikita Lipski return false;
44313f5dbd6SEvan Quan
444f7c1ed34SMikita Lipski return true;
445f7c1ed34SMikita Lipski }
446f7c1ed34SMikita Lipski
dm_pp_get_static_clocks(const struct dc_context * ctx,struct dm_pp_static_clock_info * static_clk_info)447f7c1ed34SMikita Lipski bool dm_pp_get_static_clocks(
448f7c1ed34SMikita Lipski const struct dc_context *ctx,
449f7c1ed34SMikita Lipski struct dm_pp_static_clock_info *static_clk_info)
450f7c1ed34SMikita Lipski {
451f7c1ed34SMikita Lipski struct amdgpu_device *adev = ctx->driver_context;
452f7c1ed34SMikita Lipski struct amd_pp_clock_info pp_clk_info = {0};
453f7c1ed34SMikita Lipski
45413f5dbd6SEvan Quan if (amdgpu_dpm_get_current_clocks(adev, &pp_clk_info))
455f7c1ed34SMikita Lipski return false;
456f7c1ed34SMikita Lipski
457c2c09ed5SMikita Lipski static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
4583dbd823eSRex Zhu static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
4593dbd823eSRex Zhu static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
460f7c1ed34SMikita Lipski
461f7c1ed34SMikita Lipski return true;
462f7c1ed34SMikita Lipski }
463f7c1ed34SMikita Lipski
pp_rv_set_wm_ranges(struct pp_smu * pp,struct pp_smu_wm_range_sets * ranges)4643d3e9cddSLee Jones static void pp_rv_set_wm_ranges(struct pp_smu *pp,
465f7c1ed34SMikita Lipski struct pp_smu_wm_range_sets *ranges)
466f7c1ed34SMikita Lipski {
467265f5ba6SJun Lei const struct dc_context *ctx = pp->dm;
468b0a634acSRex Zhu struct amdgpu_device *adev = ctx->driver_context;
469b0a634acSRex Zhu struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
470b0a634acSRex Zhu struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
471b0a634acSRex Zhu struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
472b0a634acSRex Zhu int32_t i;
473f7c1ed34SMikita Lipski
474b0a634acSRex Zhu wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
475b0a634acSRex Zhu wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
476f7c1ed34SMikita Lipski
477b0a634acSRex Zhu for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
478f7c1ed34SMikita Lipski if (ranges->reader_wm_sets[i].wm_inst > 3)
479b0a634acSRex Zhu wm_dce_clocks[i].wm_set_id = WM_SET_A;
480f7c1ed34SMikita Lipski else
481b0a634acSRex Zhu wm_dce_clocks[i].wm_set_id =
482f7c1ed34SMikita Lipski ranges->reader_wm_sets[i].wm_inst;
483b0a634acSRex Zhu wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
484ba7b267aSFatemeh Darbehani ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
485b0a634acSRex Zhu wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
486ba7b267aSFatemeh Darbehani ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
487b0a634acSRex Zhu wm_dce_clocks[i].wm_max_mem_clk_in_khz =
488ba7b267aSFatemeh Darbehani ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
489b0a634acSRex Zhu wm_dce_clocks[i].wm_min_mem_clk_in_khz =
490ba7b267aSFatemeh Darbehani ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
491f7c1ed34SMikita Lipski }
492f7c1ed34SMikita Lipski
493b0a634acSRex Zhu for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
494f7c1ed34SMikita Lipski if (ranges->writer_wm_sets[i].wm_inst > 3)
495b0a634acSRex Zhu wm_soc_clocks[i].wm_set_id = WM_SET_A;
496f7c1ed34SMikita Lipski else
497b0a634acSRex Zhu wm_soc_clocks[i].wm_set_id =
498f7c1ed34SMikita Lipski ranges->writer_wm_sets[i].wm_inst;
499b0a634acSRex Zhu wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
500ba7b267aSFatemeh Darbehani ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
501b0a634acSRex Zhu wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
502ba7b267aSFatemeh Darbehani ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
503b0a634acSRex Zhu wm_soc_clocks[i].wm_max_mem_clk_in_khz =
504ba7b267aSFatemeh Darbehani ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
505b0a634acSRex Zhu wm_soc_clocks[i].wm_min_mem_clk_in_khz =
506ba7b267aSFatemeh Darbehani ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
507f7c1ed34SMikita Lipski }
508f7c1ed34SMikita Lipski
50913f5dbd6SEvan Quan amdgpu_dpm_set_watermarks_for_clocks_ranges(adev,
5102e069391SHuang Rui &wm_with_clock_ranges);
511f7c1ed34SMikita Lipski }
512f7c1ed34SMikita Lipski
pp_rv_set_pme_wa_enable(struct pp_smu * pp)5133d3e9cddSLee Jones static void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
514f7c1ed34SMikita Lipski {
515265f5ba6SJun Lei const struct dc_context *ctx = pp->dm;
516b0a634acSRex Zhu struct amdgpu_device *adev = ctx->driver_context;
517f7c1ed34SMikita Lipski
51813f5dbd6SEvan Quan amdgpu_dpm_notify_smu_enable_pwe(adev);
519f7c1ed34SMikita Lipski }
520f7c1ed34SMikita Lipski
pp_rv_set_active_display_count(struct pp_smu * pp,int count)5213d3e9cddSLee Jones static void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
522588715bdShersen wu {
523588715bdShersen wu const struct dc_context *ctx = pp->dm;
524588715bdShersen wu struct amdgpu_device *adev = ctx->driver_context;
525588715bdShersen wu
52613f5dbd6SEvan Quan amdgpu_dpm_set_active_display_count(adev, count);
527588715bdShersen wu }
528588715bdShersen wu
pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu * pp,int clock)5293d3e9cddSLee Jones static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
530588715bdShersen wu {
531588715bdShersen wu const struct dc_context *ctx = pp->dm;
532588715bdShersen wu struct amdgpu_device *adev = ctx->driver_context;
533588715bdShersen wu
53413f5dbd6SEvan Quan amdgpu_dpm_set_min_deep_sleep_dcefclk(adev, clock);
535588715bdShersen wu }
536588715bdShersen wu
pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu * pp,int clock)5373d3e9cddSLee Jones static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
538588715bdShersen wu {
539588715bdShersen wu const struct dc_context *ctx = pp->dm;
540588715bdShersen wu struct amdgpu_device *adev = ctx->driver_context;
541588715bdShersen wu
54213f5dbd6SEvan Quan amdgpu_dpm_set_hard_min_dcefclk_by_freq(adev, clock);
543588715bdShersen wu }
544588715bdShersen wu
pp_rv_set_hard_min_fclk_by_freq(struct pp_smu * pp,int mhz)5453d3e9cddSLee Jones static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
546588715bdShersen wu {
547588715bdShersen wu const struct dc_context *ctx = pp->dm;
548588715bdShersen wu struct amdgpu_device *adev = ctx->driver_context;
549588715bdShersen wu
55013f5dbd6SEvan Quan amdgpu_dpm_set_hard_min_fclk_by_freq(adev, mhz);
551588715bdShersen wu }
552588715bdShersen wu
pp_nv_set_wm_ranges(struct pp_smu * pp,struct pp_smu_wm_range_sets * ranges)553dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
55479a7b060Shersen wu struct pp_smu_wm_range_sets *ranges)
55579a7b060Shersen wu {
55679a7b060Shersen wu const struct dc_context *ctx = pp->dm;
55779a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
55879a7b060Shersen wu
55913f5dbd6SEvan Quan amdgpu_dpm_set_watermarks_for_clocks_ranges(adev, ranges);
56079a7b060Shersen wu
56179a7b060Shersen wu return PP_SMU_RESULT_OK;
56279a7b060Shersen wu }
56379a7b060Shersen wu
pp_nv_set_display_count(struct pp_smu * pp,int count)564dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
56579a7b060Shersen wu {
56679a7b060Shersen wu const struct dc_context *ctx = pp->dm;
56779a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
56813f5dbd6SEvan Quan int ret = 0;
56979a7b060Shersen wu
57013f5dbd6SEvan Quan ret = amdgpu_dpm_set_active_display_count(adev, count);
57113f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
57279a7b060Shersen wu return PP_SMU_RESULT_UNSUPPORTED;
57313f5dbd6SEvan Quan else if (ret)
5746c45e480SEvan Quan /* 0: successful or smu.ppt_funcs->set_display_count = NULL; 1: fail */
57579a7b060Shersen wu return PP_SMU_RESULT_FAIL;
57679a7b060Shersen wu
57779a7b060Shersen wu return PP_SMU_RESULT_OK;
57879a7b060Shersen wu }
57979a7b060Shersen wu
580dfd84d90SNirmoy Das static enum pp_smu_status
pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu * pp,int mhz)581dfd84d90SNirmoy Das pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
58279a7b060Shersen wu {
58379a7b060Shersen wu const struct dc_context *ctx = pp->dm;
58479a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
58513f5dbd6SEvan Quan int ret = 0;
58679a7b060Shersen wu
5876c45e480SEvan Quan /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
58813f5dbd6SEvan Quan ret = amdgpu_dpm_set_min_deep_sleep_dcefclk(adev, mhz);
58913f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
59013f5dbd6SEvan Quan return PP_SMU_RESULT_UNSUPPORTED;
59113f5dbd6SEvan Quan else if (ret)
59279a7b060Shersen wu return PP_SMU_RESULT_FAIL;
59379a7b060Shersen wu
59479a7b060Shersen wu return PP_SMU_RESULT_OK;
59579a7b060Shersen wu }
59679a7b060Shersen wu
pp_nv_set_hard_min_dcefclk_by_freq(struct pp_smu * pp,int mhz)597dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
59879a7b060Shersen wu struct pp_smu *pp, int mhz)
59979a7b060Shersen wu {
60079a7b060Shersen wu const struct dc_context *ctx = pp->dm;
60179a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
60279a7b060Shersen wu struct pp_display_clock_request clock_req;
60313f5dbd6SEvan Quan int ret = 0;
60479a7b060Shersen wu
60579a7b060Shersen wu clock_req.clock_type = amd_pp_dcef_clock;
60679a7b060Shersen wu clock_req.clock_freq_in_khz = mhz * 1000;
60779a7b060Shersen wu
6086c45e480SEvan Quan /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
60979a7b060Shersen wu * 1: fail
61079a7b060Shersen wu */
61113f5dbd6SEvan Quan ret = amdgpu_dpm_display_clock_voltage_request(adev, &clock_req);
61213f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
61313f5dbd6SEvan Quan return PP_SMU_RESULT_UNSUPPORTED;
61413f5dbd6SEvan Quan else if (ret)
61579a7b060Shersen wu return PP_SMU_RESULT_FAIL;
61679a7b060Shersen wu
61779a7b060Shersen wu return PP_SMU_RESULT_OK;
61879a7b060Shersen wu }
61979a7b060Shersen wu
620dfd84d90SNirmoy Das static enum pp_smu_status
pp_nv_set_hard_min_uclk_by_freq(struct pp_smu * pp,int mhz)621dfd84d90SNirmoy Das pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
62279a7b060Shersen wu {
62379a7b060Shersen wu const struct dc_context *ctx = pp->dm;
62479a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
62579a7b060Shersen wu struct pp_display_clock_request clock_req;
62613f5dbd6SEvan Quan int ret = 0;
62779a7b060Shersen wu
62879a7b060Shersen wu clock_req.clock_type = amd_pp_mem_clock;
62979a7b060Shersen wu clock_req.clock_freq_in_khz = mhz * 1000;
63079a7b060Shersen wu
6316c45e480SEvan Quan /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
63279a7b060Shersen wu * 1: fail
63379a7b060Shersen wu */
63413f5dbd6SEvan Quan ret = amdgpu_dpm_display_clock_voltage_request(adev, &clock_req);
63513f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
63613f5dbd6SEvan Quan return PP_SMU_RESULT_UNSUPPORTED;
63713f5dbd6SEvan Quan else if (ret)
63879a7b060Shersen wu return PP_SMU_RESULT_FAIL;
63979a7b060Shersen wu
64079a7b060Shersen wu return PP_SMU_RESULT_OK;
64179a7b060Shersen wu }
64279a7b060Shersen wu
pp_nv_set_pstate_handshake_support(struct pp_smu * pp,bool pstate_handshake_supported)643dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_set_pstate_handshake_support(
64426652cd8SFlora Cui struct pp_smu *pp, bool pstate_handshake_supported)
6456e92e156SKenneth Feng {
6466e92e156SKenneth Feng const struct dc_context *ctx = pp->dm;
6476e92e156SKenneth Feng struct amdgpu_device *adev = ctx->driver_context;
6486e92e156SKenneth Feng
64913f5dbd6SEvan Quan if (amdgpu_dpm_display_disable_memory_clock_switch(adev,
6505f400639SEvan Quan !pstate_handshake_supported))
6516e92e156SKenneth Feng return PP_SMU_RESULT_FAIL;
6526e92e156SKenneth Feng
6536e92e156SKenneth Feng return PP_SMU_RESULT_OK;
6546e92e156SKenneth Feng }
6556e92e156SKenneth Feng
pp_nv_set_voltage_by_freq(struct pp_smu * pp,enum pp_smu_nv_clock_id clock_id,int mhz)656dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
65779a7b060Shersen wu enum pp_smu_nv_clock_id clock_id, int mhz)
65879a7b060Shersen wu {
65979a7b060Shersen wu const struct dc_context *ctx = pp->dm;
66079a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
66179a7b060Shersen wu struct pp_display_clock_request clock_req;
66213f5dbd6SEvan Quan int ret = 0;
66379a7b060Shersen wu
66479a7b060Shersen wu switch (clock_id) {
66579a7b060Shersen wu case PP_SMU_NV_DISPCLK:
66679a7b060Shersen wu clock_req.clock_type = amd_pp_disp_clock;
66779a7b060Shersen wu break;
66879a7b060Shersen wu case PP_SMU_NV_PHYCLK:
66979a7b060Shersen wu clock_req.clock_type = amd_pp_phy_clock;
67079a7b060Shersen wu break;
67179a7b060Shersen wu case PP_SMU_NV_PIXELCLK:
67279a7b060Shersen wu clock_req.clock_type = amd_pp_pixel_clock;
67379a7b060Shersen wu break;
67479a7b060Shersen wu default:
67579a7b060Shersen wu break;
67679a7b060Shersen wu }
67779a7b060Shersen wu clock_req.clock_freq_in_khz = mhz * 1000;
67879a7b060Shersen wu
6796c45e480SEvan Quan /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
68079a7b060Shersen wu * 1: fail
68179a7b060Shersen wu */
68213f5dbd6SEvan Quan ret = amdgpu_dpm_display_clock_voltage_request(adev, &clock_req);
68313f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
68413f5dbd6SEvan Quan return PP_SMU_RESULT_UNSUPPORTED;
68513f5dbd6SEvan Quan else if (ret)
68679a7b060Shersen wu return PP_SMU_RESULT_FAIL;
68779a7b060Shersen wu
68879a7b060Shersen wu return PP_SMU_RESULT_OK;
68979a7b060Shersen wu }
69079a7b060Shersen wu
pp_nv_get_maximum_sustainable_clocks(struct pp_smu * pp,struct pp_smu_nv_clock_table * max_clocks)691dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
69279a7b060Shersen wu struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)
69379a7b060Shersen wu {
69479a7b060Shersen wu const struct dc_context *ctx = pp->dm;
69579a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
69613f5dbd6SEvan Quan int ret = 0;
69779a7b060Shersen wu
69813f5dbd6SEvan Quan ret = amdgpu_dpm_get_max_sustainable_clocks_by_dc(adev,
69913f5dbd6SEvan Quan max_clocks);
70013f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
70179a7b060Shersen wu return PP_SMU_RESULT_UNSUPPORTED;
70213f5dbd6SEvan Quan else if (ret)
70379a7b060Shersen wu return PP_SMU_RESULT_FAIL;
70413f5dbd6SEvan Quan
70513f5dbd6SEvan Quan return PP_SMU_RESULT_OK;
70679a7b060Shersen wu }
70779a7b060Shersen wu
pp_nv_get_uclk_dpm_states(struct pp_smu * pp,unsigned int * clock_values_in_khz,unsigned int * num_states)708dfd84d90SNirmoy Das static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
70979a7b060Shersen wu unsigned int *clock_values_in_khz, unsigned int *num_states)
71079a7b060Shersen wu {
71179a7b060Shersen wu const struct dc_context *ctx = pp->dm;
71279a7b060Shersen wu struct amdgpu_device *adev = ctx->driver_context;
71313f5dbd6SEvan Quan int ret = 0;
71479a7b060Shersen wu
71513f5dbd6SEvan Quan ret = amdgpu_dpm_get_uclk_dpm_states(adev,
7165f400639SEvan Quan clock_values_in_khz,
71713f5dbd6SEvan Quan num_states);
71813f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
71913f5dbd6SEvan Quan return PP_SMU_RESULT_UNSUPPORTED;
72013f5dbd6SEvan Quan else if (ret)
72179a7b060Shersen wu return PP_SMU_RESULT_FAIL;
72213f5dbd6SEvan Quan
72313f5dbd6SEvan Quan return PP_SMU_RESULT_OK;
72479a7b060Shersen wu }
72579a7b060Shersen wu
pp_rn_get_dpm_clock_table(struct pp_smu * pp,struct dpm_clocks * clock_table)726dfd84d90SNirmoy Das static enum pp_smu_status pp_rn_get_dpm_clock_table(
72771a0df4bSHersen Wu struct pp_smu *pp, struct dpm_clocks *clock_table)
72871a0df4bSHersen Wu {
72971a0df4bSHersen Wu const struct dc_context *ctx = pp->dm;
73071a0df4bSHersen Wu struct amdgpu_device *adev = ctx->driver_context;
73113f5dbd6SEvan Quan int ret = 0;
73271a0df4bSHersen Wu
73313f5dbd6SEvan Quan ret = amdgpu_dpm_get_dpm_clock_table(adev, clock_table);
73413f5dbd6SEvan Quan if (ret == -EOPNOTSUPP)
73571a0df4bSHersen Wu return PP_SMU_RESULT_UNSUPPORTED;
73613f5dbd6SEvan Quan else if (ret)
73771a0df4bSHersen Wu return PP_SMU_RESULT_FAIL;
73813f5dbd6SEvan Quan
73913f5dbd6SEvan Quan return PP_SMU_RESULT_OK;
74071a0df4bSHersen Wu }
74171a0df4bSHersen Wu
pp_rn_set_wm_ranges(struct pp_smu * pp,struct pp_smu_wm_range_sets * ranges)742dfd84d90SNirmoy Das static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
74371a0df4bSHersen Wu struct pp_smu_wm_range_sets *ranges)
74471a0df4bSHersen Wu {
74571a0df4bSHersen Wu const struct dc_context *ctx = pp->dm;
74671a0df4bSHersen Wu struct amdgpu_device *adev = ctx->driver_context;
74771a0df4bSHersen Wu
74813f5dbd6SEvan Quan amdgpu_dpm_set_watermarks_for_clocks_ranges(adev, ranges);
74971a0df4bSHersen Wu
75071a0df4bSHersen Wu return PP_SMU_RESULT_OK;
75171a0df4bSHersen Wu }
75271a0df4bSHersen Wu
dm_pp_get_funcs(struct dc_context * ctx,struct pp_smu_funcs * funcs)7530f1a6ad7SJun Lei void dm_pp_get_funcs(
754f7c1ed34SMikita Lipski struct dc_context *ctx,
7550f1a6ad7SJun Lei struct pp_smu_funcs *funcs)
756f7c1ed34SMikita Lipski {
75779a7b060Shersen wu switch (ctx->dce_version) {
75879a7b060Shersen wu case DCN_VERSION_1_0:
75979a7b060Shersen wu case DCN_VERSION_1_01:
76079a7b060Shersen wu funcs->ctx.ver = PP_SMU_VER_RV;
7610f1a6ad7SJun Lei funcs->rv_funcs.pp_smu.dm = ctx;
7620f1a6ad7SJun Lei funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
7630f1a6ad7SJun Lei funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
76479a7b060Shersen wu funcs->rv_funcs.set_display_count =
76579a7b060Shersen wu pp_rv_set_active_display_count;
76679a7b060Shersen wu funcs->rv_funcs.set_min_deep_sleep_dcfclk =
76779a7b060Shersen wu pp_rv_set_min_deep_sleep_dcfclk;
76879a7b060Shersen wu funcs->rv_funcs.set_hard_min_dcfclk_by_freq =
76979a7b060Shersen wu pp_rv_set_hard_min_dcefclk_by_freq;
77079a7b060Shersen wu funcs->rv_funcs.set_hard_min_fclk_by_freq =
77179a7b060Shersen wu pp_rv_set_hard_min_fclk_by_freq;
77279a7b060Shersen wu break;
77379a7b060Shersen wu case DCN_VERSION_2_0:
77479a7b060Shersen wu funcs->ctx.ver = PP_SMU_VER_NV;
77579a7b060Shersen wu funcs->nv_funcs.pp_smu.dm = ctx;
77679a7b060Shersen wu funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
77779a7b060Shersen wu funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
77879a7b060Shersen wu pp_nv_set_hard_min_dcefclk_by_freq;
77979a7b060Shersen wu funcs->nv_funcs.set_min_deep_sleep_dcfclk =
78079a7b060Shersen wu pp_nv_set_min_deep_sleep_dcfclk;
78179a7b060Shersen wu funcs->nv_funcs.set_voltage_by_freq =
78279a7b060Shersen wu pp_nv_set_voltage_by_freq;
78379a7b060Shersen wu funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
784588715bdShersen wu
78579a7b060Shersen wu /* todo set_pme_wa_enable cause 4k@6ohz display not light up */
78679a7b060Shersen wu funcs->nv_funcs.set_pme_wa_enable = NULL;
78779a7b060Shersen wu /* todo debug waring message */
78802316e96SNicholas Kazlauskas funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
78979a7b060Shersen wu /* todo compare data with window driver*/
79002316e96SNicholas Kazlauskas funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
79179a7b060Shersen wu /*todo compare data with window driver */
79202316e96SNicholas Kazlauskas funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
7936e92e156SKenneth Feng funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
79479a7b060Shersen wu break;
79571a0df4bSHersen Wu
79671a0df4bSHersen Wu case DCN_VERSION_2_1:
79771a0df4bSHersen Wu funcs->ctx.ver = PP_SMU_VER_RN;
79871a0df4bSHersen Wu funcs->rn_funcs.pp_smu.dm = ctx;
79971a0df4bSHersen Wu funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
80071a0df4bSHersen Wu funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
80171a0df4bSHersen Wu break;
80279a7b060Shersen wu default:
80379a7b060Shersen wu DRM_ERROR("smu version is not supported !\n");
80479a7b060Shersen wu break;
80579a7b060Shersen wu }
80679a7b060Shersen wu }
807