1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 35 #include "dc.h" 36 #include "dm_helpers.h" 37 38 #include "dc_link_ddc.h" 39 #include "ddc_service_types.h" 40 #include "dpcd_defs.h" 41 42 #include "i2caux_interface.h" 43 #include "dmub_cmd.h" 44 #if defined(CONFIG_DEBUG_FS) 45 #include "amdgpu_dm_debugfs.h" 46 #endif 47 48 #include "dc/dcn20/dcn20_resource.h" 49 bool is_timing_changed(struct dc_stream_state *cur_stream, 50 struct dc_stream_state *new_stream); 51 52 53 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 54 struct drm_dp_aux_msg *msg) 55 { 56 ssize_t result = 0; 57 struct aux_payload payload; 58 enum aux_return_code_type operation_result; 59 60 if (WARN_ON(msg->size > 16)) 61 return -E2BIG; 62 63 payload.address = msg->address; 64 payload.data = msg->buffer; 65 payload.length = msg->size; 66 payload.reply = &msg->reply; 67 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 68 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 69 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 70 payload.write_status_update = 71 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 72 payload.defer_delay = 0; 73 74 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 75 &operation_result); 76 77 if (payload.write && result >= 0) 78 result = msg->size; 79 80 if (result < 0) 81 switch (operation_result) { 82 case AUX_RET_SUCCESS: 83 break; 84 case AUX_RET_ERROR_HPD_DISCON: 85 case AUX_RET_ERROR_UNKNOWN: 86 case AUX_RET_ERROR_INVALID_OPERATION: 87 case AUX_RET_ERROR_PROTOCOL_ERROR: 88 result = -EIO; 89 break; 90 case AUX_RET_ERROR_INVALID_REPLY: 91 case AUX_RET_ERROR_ENGINE_ACQUIRE: 92 result = -EBUSY; 93 break; 94 case AUX_RET_ERROR_TIMEOUT: 95 result = -ETIMEDOUT; 96 break; 97 } 98 99 return result; 100 } 101 102 static void 103 dm_dp_mst_connector_destroy(struct drm_connector *connector) 104 { 105 struct amdgpu_dm_connector *aconnector = 106 to_amdgpu_dm_connector(connector); 107 108 if (aconnector->dc_sink) { 109 dc_link_remove_remote_sink(aconnector->dc_link, 110 aconnector->dc_sink); 111 dc_sink_release(aconnector->dc_sink); 112 } 113 114 kfree(aconnector->edid); 115 116 drm_connector_cleanup(connector); 117 drm_dp_mst_put_port_malloc(aconnector->port); 118 kfree(aconnector); 119 } 120 121 static int 122 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 123 { 124 struct amdgpu_dm_connector *amdgpu_dm_connector = 125 to_amdgpu_dm_connector(connector); 126 int r; 127 128 r = drm_dp_mst_connector_late_register(connector, 129 amdgpu_dm_connector->port); 130 if (r < 0) 131 return r; 132 133 #if defined(CONFIG_DEBUG_FS) 134 connector_debugfs_init(amdgpu_dm_connector); 135 #endif 136 137 return 0; 138 } 139 140 static void 141 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 142 { 143 struct amdgpu_dm_connector *amdgpu_dm_connector = 144 to_amdgpu_dm_connector(connector); 145 struct drm_dp_mst_port *port = amdgpu_dm_connector->port; 146 147 drm_dp_mst_connector_early_unregister(connector, port); 148 } 149 150 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 151 .fill_modes = drm_helper_probe_single_connector_modes, 152 .destroy = dm_dp_mst_connector_destroy, 153 .reset = amdgpu_dm_connector_funcs_reset, 154 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 155 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 156 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 157 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 158 .late_register = amdgpu_dm_mst_connector_late_register, 159 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 160 }; 161 162 #if defined(CONFIG_DRM_AMD_DC_DCN) 163 bool needs_dsc_aux_workaround(struct dc_link *link) 164 { 165 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 166 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 167 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 168 return true; 169 170 return false; 171 } 172 173 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 174 { 175 struct dc_sink *dc_sink = aconnector->dc_sink; 176 struct drm_dp_mst_port *port = aconnector->port; 177 u8 dsc_caps[16] = { 0 }; 178 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 179 u8 *dsc_branch_dec_caps = NULL; 180 181 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 182 183 /* 184 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 185 * because it only check the dsc/fec caps of the "port variable" and not the dock 186 * 187 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 188 * 189 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 190 * 191 */ 192 if (!aconnector->dsc_aux && !port->parent->port_parent && 193 needs_dsc_aux_workaround(aconnector->dc_link)) 194 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux; 195 196 if (!aconnector->dsc_aux) 197 return false; 198 199 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 200 return false; 201 202 if (drm_dp_dpcd_read(aconnector->dsc_aux, 203 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 204 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 205 206 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 207 dsc_caps, dsc_branch_dec_caps, 208 &dc_sink->dsc_caps.dsc_dec_caps)) 209 return false; 210 211 return true; 212 } 213 214 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 215 { 216 union dp_downstream_port_present ds_port_present; 217 218 if (!aconnector->dsc_aux) 219 return false; 220 221 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 222 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 223 return false; 224 } 225 226 aconnector->mst_downstream_port_present = ds_port_present; 227 DRM_INFO("Downstream port present %d, type %d\n", 228 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 229 230 return true; 231 } 232 #endif 233 234 static int dm_dp_mst_get_modes(struct drm_connector *connector) 235 { 236 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 237 int ret = 0; 238 239 if (!aconnector) 240 return drm_add_edid_modes(connector, NULL); 241 242 if (!aconnector->edid) { 243 struct edid *edid; 244 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); 245 246 if (!edid) { 247 drm_connector_update_edid_property( 248 &aconnector->base, 249 NULL); 250 251 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 252 if (!aconnector->dc_sink) { 253 struct dc_sink *dc_sink; 254 struct dc_sink_init_data init_params = { 255 .link = aconnector->dc_link, 256 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 257 258 dc_sink = dc_link_add_remote_sink( 259 aconnector->dc_link, 260 NULL, 261 0, 262 &init_params); 263 264 if (!dc_sink) { 265 DRM_ERROR("Unable to add a remote sink\n"); 266 return 0; 267 } 268 269 dc_sink->priv = aconnector; 270 aconnector->dc_sink = dc_sink; 271 } 272 273 return ret; 274 } 275 276 aconnector->edid = edid; 277 } 278 279 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 280 dc_sink_release(aconnector->dc_sink); 281 aconnector->dc_sink = NULL; 282 } 283 284 if (!aconnector->dc_sink) { 285 struct dc_sink *dc_sink; 286 struct dc_sink_init_data init_params = { 287 .link = aconnector->dc_link, 288 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 289 dc_sink = dc_link_add_remote_sink( 290 aconnector->dc_link, 291 (uint8_t *)aconnector->edid, 292 (aconnector->edid->extensions + 1) * EDID_LENGTH, 293 &init_params); 294 295 if (!dc_sink) { 296 DRM_ERROR("Unable to add a remote sink\n"); 297 return 0; 298 } 299 300 dc_sink->priv = aconnector; 301 /* dc_link_add_remote_sink returns a new reference */ 302 aconnector->dc_sink = dc_sink; 303 304 if (aconnector->dc_sink) { 305 amdgpu_dm_update_freesync_caps( 306 connector, aconnector->edid); 307 308 #if defined(CONFIG_DRM_AMD_DC_DCN) 309 if (!validate_dsc_caps_on_connector(aconnector)) 310 memset(&aconnector->dc_sink->dsc_caps, 311 0, sizeof(aconnector->dc_sink->dsc_caps)); 312 313 if (!retrieve_downstream_port_device(aconnector)) 314 memset(&aconnector->mst_downstream_port_present, 315 0, sizeof(aconnector->mst_downstream_port_present)); 316 #endif 317 } 318 } 319 320 drm_connector_update_edid_property( 321 &aconnector->base, aconnector->edid); 322 323 ret = drm_add_edid_modes(connector, aconnector->edid); 324 325 return ret; 326 } 327 328 static struct drm_encoder * 329 dm_mst_atomic_best_encoder(struct drm_connector *connector, 330 struct drm_atomic_state *state) 331 { 332 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 333 connector); 334 struct drm_device *dev = connector->dev; 335 struct amdgpu_device *adev = drm_to_adev(dev); 336 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 337 338 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 339 } 340 341 static int 342 dm_dp_mst_detect(struct drm_connector *connector, 343 struct drm_modeset_acquire_ctx *ctx, bool force) 344 { 345 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 346 struct amdgpu_dm_connector *master = aconnector->mst_port; 347 348 if (drm_connector_is_unregistered(connector)) 349 return connector_status_disconnected; 350 351 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 352 aconnector->port); 353 } 354 355 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 356 struct drm_atomic_state *state) 357 { 358 struct drm_connector_state *new_conn_state = 359 drm_atomic_get_new_connector_state(state, connector); 360 struct drm_connector_state *old_conn_state = 361 drm_atomic_get_old_connector_state(state, connector); 362 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 363 struct drm_crtc_state *new_crtc_state; 364 struct drm_dp_mst_topology_mgr *mst_mgr; 365 struct drm_dp_mst_port *mst_port; 366 367 mst_port = aconnector->port; 368 mst_mgr = &aconnector->mst_port->mst_mgr; 369 370 if (!old_conn_state->crtc) 371 return 0; 372 373 if (new_conn_state->crtc) { 374 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 375 if (!new_crtc_state || 376 !drm_atomic_crtc_needs_modeset(new_crtc_state) || 377 new_crtc_state->enable) 378 return 0; 379 } 380 381 return drm_dp_atomic_release_vcpi_slots(state, 382 mst_mgr, 383 mst_port); 384 } 385 386 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 387 .get_modes = dm_dp_mst_get_modes, 388 .mode_valid = amdgpu_dm_connector_mode_valid, 389 .atomic_best_encoder = dm_mst_atomic_best_encoder, 390 .detect_ctx = dm_dp_mst_detect, 391 .atomic_check = dm_dp_mst_atomic_check, 392 }; 393 394 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 395 { 396 drm_encoder_cleanup(encoder); 397 kfree(encoder); 398 } 399 400 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 401 .destroy = amdgpu_dm_encoder_destroy, 402 }; 403 404 void 405 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 406 { 407 struct drm_device *dev = adev_to_drm(adev); 408 int i; 409 410 for (i = 0; i < adev->dm.display_indexes_num; i++) { 411 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 412 struct drm_encoder *encoder = &amdgpu_encoder->base; 413 414 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 415 416 drm_encoder_init( 417 dev, 418 &amdgpu_encoder->base, 419 &amdgpu_dm_encoder_funcs, 420 DRM_MODE_ENCODER_DPMST, 421 NULL); 422 423 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 424 } 425 } 426 427 static struct drm_connector * 428 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 429 struct drm_dp_mst_port *port, 430 const char *pathprop) 431 { 432 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 433 struct drm_device *dev = master->base.dev; 434 struct amdgpu_device *adev = drm_to_adev(dev); 435 struct amdgpu_dm_connector *aconnector; 436 struct drm_connector *connector; 437 int i; 438 439 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 440 if (!aconnector) 441 return NULL; 442 443 connector = &aconnector->base; 444 aconnector->port = port; 445 aconnector->mst_port = master; 446 447 if (drm_connector_init( 448 dev, 449 connector, 450 &dm_dp_mst_connector_funcs, 451 DRM_MODE_CONNECTOR_DisplayPort)) { 452 kfree(aconnector); 453 return NULL; 454 } 455 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 456 457 amdgpu_dm_connector_init_helper( 458 &adev->dm, 459 aconnector, 460 DRM_MODE_CONNECTOR_DisplayPort, 461 master->dc_link, 462 master->connector_id); 463 464 for (i = 0; i < adev->dm.display_indexes_num; i++) { 465 drm_connector_attach_encoder(&aconnector->base, 466 &adev->dm.mst_encoders[i].base); 467 } 468 469 connector->max_bpc_property = master->base.max_bpc_property; 470 if (connector->max_bpc_property) 471 drm_connector_attach_max_bpc_property(connector, 8, 16); 472 473 connector->vrr_capable_property = master->base.vrr_capable_property; 474 if (connector->vrr_capable_property) 475 drm_connector_attach_vrr_capable_property(connector); 476 477 drm_object_attach_property( 478 &connector->base, 479 dev->mode_config.path_property, 480 0); 481 drm_object_attach_property( 482 &connector->base, 483 dev->mode_config.tile_property, 484 0); 485 486 drm_connector_set_path_property(connector, pathprop); 487 488 /* 489 * Initialize connector state before adding the connectror to drm and 490 * framebuffer lists 491 */ 492 amdgpu_dm_connector_funcs_reset(connector); 493 494 drm_dp_mst_get_port_malloc(port); 495 496 return connector; 497 } 498 499 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 500 .add_connector = dm_dp_add_mst_connector, 501 }; 502 503 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 504 struct amdgpu_dm_connector *aconnector, 505 int link_index) 506 { 507 struct dc_link_settings max_link_enc_cap = {0}; 508 509 aconnector->dm_dp_aux.aux.name = 510 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 511 link_index); 512 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 513 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 514 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 515 516 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 517 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 518 &aconnector->base); 519 520 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 521 return; 522 523 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 524 aconnector->mst_mgr.cbs = &dm_mst_cbs; 525 drm_dp_mst_topology_mgr_init( 526 &aconnector->mst_mgr, 527 adev_to_drm(dm->adev), 528 &aconnector->dm_dp_aux.aux, 529 16, 530 4, 531 max_link_enc_cap.lane_count, 532 drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), 533 aconnector->connector_id); 534 535 drm_connector_attach_dp_subconnector_property(&aconnector->base); 536 } 537 538 int dm_mst_get_pbn_divider(struct dc_link *link) 539 { 540 if (!link) 541 return 0; 542 543 return dc_link_bandwidth_kbps(link, 544 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 545 } 546 547 #if defined(CONFIG_DRM_AMD_DC_DCN) 548 549 struct dsc_mst_fairness_params { 550 struct dc_crtc_timing *timing; 551 struct dc_sink *sink; 552 struct dc_dsc_bw_range bw_range; 553 bool compression_possible; 554 struct drm_dp_mst_port *port; 555 enum dsc_clock_force_state clock_force_enable; 556 uint32_t num_slices_h; 557 uint32_t num_slices_v; 558 uint32_t bpp_overwrite; 559 struct amdgpu_dm_connector *aconnector; 560 }; 561 562 static int kbps_to_peak_pbn(int kbps) 563 { 564 u64 peak_kbps = kbps; 565 566 peak_kbps *= 1006; 567 peak_kbps = div_u64(peak_kbps, 1000); 568 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 569 } 570 571 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 572 struct dsc_mst_fairness_vars *vars, 573 int count, 574 int k) 575 { 576 int i; 577 578 for (i = 0; i < count; i++) { 579 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 580 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 581 params[i].sink->ctx->dc->res_pool->dscs[0], 582 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 583 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override, 584 params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit, 585 0, 586 params[i].timing, 587 ¶ms[i].timing->dsc_cfg)) { 588 params[i].timing->flags.DSC = 1; 589 590 if (params[i].bpp_overwrite) 591 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 592 else 593 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 594 595 if (params[i].num_slices_h) 596 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 597 598 if (params[i].num_slices_v) 599 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 600 } else { 601 params[i].timing->flags.DSC = 0; 602 } 603 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 604 } 605 606 for (i = 0; i < count; i++) { 607 if (params[i].sink) { 608 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 609 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 610 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 611 params[i].sink->edid_caps.display_name); 612 } 613 614 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 615 params[i].timing->flags.DSC, 616 params[i].timing->dsc_cfg.bits_per_pixel, 617 vars[i + k].pbn); 618 } 619 } 620 621 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 622 { 623 struct dc_dsc_config dsc_config; 624 u64 kbps; 625 626 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 627 dc_dsc_compute_config( 628 param.sink->ctx->dc->res_pool->dscs[0], 629 ¶m.sink->dsc_caps.dsc_dec_caps, 630 param.sink->ctx->dc->debug.dsc_min_slice_height_override, 631 param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit, 632 (int) kbps, param.timing, &dsc_config); 633 634 return dsc_config.bits_per_pixel; 635 } 636 637 static void increase_dsc_bpp(struct drm_atomic_state *state, 638 struct dc_link *dc_link, 639 struct dsc_mst_fairness_params *params, 640 struct dsc_mst_fairness_vars *vars, 641 int count, 642 int k) 643 { 644 int i; 645 bool bpp_increased[MAX_PIPES]; 646 int initial_slack[MAX_PIPES]; 647 int min_initial_slack; 648 int next_index; 649 int remaining_to_increase = 0; 650 int pbn_per_timeslot; 651 int link_timeslots_used; 652 int fair_pbn_alloc; 653 654 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); 655 656 for (i = 0; i < count; i++) { 657 if (vars[i + k].dsc_enabled) { 658 initial_slack[i] = 659 kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn; 660 bpp_increased[i] = false; 661 remaining_to_increase += 1; 662 } else { 663 initial_slack[i] = 0; 664 bpp_increased[i] = true; 665 } 666 } 667 668 while (remaining_to_increase) { 669 next_index = -1; 670 min_initial_slack = -1; 671 for (i = 0; i < count; i++) { 672 if (!bpp_increased[i]) { 673 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 674 min_initial_slack = initial_slack[i]; 675 next_index = i; 676 } 677 } 678 } 679 680 if (next_index == -1) 681 break; 682 683 link_timeslots_used = 0; 684 685 for (i = 0; i < count; i++) 686 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, pbn_per_timeslot); 687 688 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot; 689 690 if (initial_slack[next_index] > fair_pbn_alloc) { 691 vars[next_index].pbn += fair_pbn_alloc; 692 if (drm_dp_atomic_find_vcpi_slots(state, 693 params[next_index].port->mgr, 694 params[next_index].port, 695 vars[next_index].pbn, 696 pbn_per_timeslot) < 0) 697 return; 698 if (!drm_dp_mst_atomic_check(state)) { 699 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 700 } else { 701 vars[next_index].pbn -= fair_pbn_alloc; 702 if (drm_dp_atomic_find_vcpi_slots(state, 703 params[next_index].port->mgr, 704 params[next_index].port, 705 vars[next_index].pbn, 706 pbn_per_timeslot) < 0) 707 return; 708 } 709 } else { 710 vars[next_index].pbn += initial_slack[next_index]; 711 if (drm_dp_atomic_find_vcpi_slots(state, 712 params[next_index].port->mgr, 713 params[next_index].port, 714 vars[next_index].pbn, 715 pbn_per_timeslot) < 0) 716 return; 717 if (!drm_dp_mst_atomic_check(state)) { 718 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 719 } else { 720 vars[next_index].pbn -= initial_slack[next_index]; 721 if (drm_dp_atomic_find_vcpi_slots(state, 722 params[next_index].port->mgr, 723 params[next_index].port, 724 vars[next_index].pbn, 725 pbn_per_timeslot) < 0) 726 return; 727 } 728 } 729 730 bpp_increased[next_index] = true; 731 remaining_to_increase--; 732 } 733 } 734 735 static void try_disable_dsc(struct drm_atomic_state *state, 736 struct dc_link *dc_link, 737 struct dsc_mst_fairness_params *params, 738 struct dsc_mst_fairness_vars *vars, 739 int count, 740 int k) 741 { 742 int i; 743 bool tried[MAX_PIPES]; 744 int kbps_increase[MAX_PIPES]; 745 int max_kbps_increase; 746 int next_index; 747 int remaining_to_try = 0; 748 749 for (i = 0; i < count; i++) { 750 if (vars[i + k].dsc_enabled 751 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 752 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 753 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 754 tried[i] = false; 755 remaining_to_try += 1; 756 } else { 757 kbps_increase[i] = 0; 758 tried[i] = true; 759 } 760 } 761 762 while (remaining_to_try) { 763 next_index = -1; 764 max_kbps_increase = -1; 765 for (i = 0; i < count; i++) { 766 if (!tried[i]) { 767 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 768 max_kbps_increase = kbps_increase[i]; 769 next_index = i; 770 } 771 } 772 } 773 774 if (next_index == -1) 775 break; 776 777 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps); 778 if (drm_dp_atomic_find_vcpi_slots(state, 779 params[next_index].port->mgr, 780 params[next_index].port, 781 vars[next_index].pbn, 782 dm_mst_get_pbn_divider(dc_link)) < 0) 783 return; 784 785 if (!drm_dp_mst_atomic_check(state)) { 786 vars[next_index].dsc_enabled = false; 787 vars[next_index].bpp_x16 = 0; 788 } else { 789 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps); 790 if (drm_dp_atomic_find_vcpi_slots(state, 791 params[next_index].port->mgr, 792 params[next_index].port, 793 vars[next_index].pbn, 794 dm_mst_get_pbn_divider(dc_link)) < 0) 795 return; 796 } 797 798 tried[next_index] = true; 799 remaining_to_try--; 800 } 801 } 802 803 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 804 struct dc_state *dc_state, 805 struct dc_link *dc_link, 806 struct dsc_mst_fairness_vars *vars, 807 int *link_vars_start_index) 808 { 809 int i, k; 810 struct dc_stream_state *stream; 811 struct dsc_mst_fairness_params params[MAX_PIPES]; 812 struct amdgpu_dm_connector *aconnector; 813 int count = 0; 814 bool debugfs_overwrite = false; 815 816 memset(params, 0, sizeof(params)); 817 818 /* Set up params */ 819 for (i = 0; i < dc_state->stream_count; i++) { 820 struct dc_dsc_policy dsc_policy = {0}; 821 822 stream = dc_state->streams[i]; 823 824 if (stream->link != dc_link) 825 continue; 826 827 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 828 if (!aconnector) 829 continue; 830 831 if (!aconnector->port) 832 continue; 833 834 stream->timing.flags.DSC = 0; 835 836 params[count].timing = &stream->timing; 837 params[count].sink = stream->sink; 838 params[count].aconnector = aconnector; 839 params[count].port = aconnector->port; 840 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 841 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 842 debugfs_overwrite = true; 843 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 844 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 845 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 846 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 847 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 848 if (!dc_dsc_compute_bandwidth_range( 849 stream->sink->ctx->dc->res_pool->dscs[0], 850 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 851 dsc_policy.min_target_bpp * 16, 852 dsc_policy.max_target_bpp * 16, 853 &stream->sink->dsc_caps.dsc_dec_caps, 854 &stream->timing, ¶ms[count].bw_range)) 855 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 856 857 count++; 858 } 859 860 if (count == 0) { 861 ASSERT(0); 862 return true; 863 } 864 865 /* k is start index of vars for current phy link used by mst hub */ 866 k = *link_vars_start_index; 867 /* set vars start index for next mst hub phy link */ 868 *link_vars_start_index += count; 869 870 /* Try no compression */ 871 for (i = 0; i < count; i++) { 872 vars[i + k].aconnector = params[i].aconnector; 873 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 874 vars[i + k].dsc_enabled = false; 875 vars[i + k].bpp_x16 = 0; 876 if (drm_dp_atomic_find_vcpi_slots(state, 877 params[i].port->mgr, 878 params[i].port, 879 vars[i + k].pbn, 880 dm_mst_get_pbn_divider(dc_link)) < 0) 881 return false; 882 } 883 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) { 884 set_dsc_configs_from_fairness_vars(params, vars, count, k); 885 return true; 886 } 887 888 /* Try max compression */ 889 for (i = 0; i < count; i++) { 890 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 891 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps); 892 vars[i + k].dsc_enabled = true; 893 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 894 if (drm_dp_atomic_find_vcpi_slots(state, 895 params[i].port->mgr, 896 params[i].port, 897 vars[i + k].pbn, 898 dm_mst_get_pbn_divider(dc_link)) < 0) 899 return false; 900 } else { 901 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 902 vars[i + k].dsc_enabled = false; 903 vars[i + k].bpp_x16 = 0; 904 if (drm_dp_atomic_find_vcpi_slots(state, 905 params[i].port->mgr, 906 params[i].port, 907 vars[i + k].pbn, 908 dm_mst_get_pbn_divider(dc_link)) < 0) 909 return false; 910 } 911 } 912 if (drm_dp_mst_atomic_check(state)) 913 return false; 914 915 /* Optimize degree of compression */ 916 increase_dsc_bpp(state, dc_link, params, vars, count, k); 917 918 try_disable_dsc(state, dc_link, params, vars, count, k); 919 920 set_dsc_configs_from_fairness_vars(params, vars, count, k); 921 922 return true; 923 } 924 925 static bool is_dsc_need_re_compute( 926 struct drm_atomic_state *state, 927 struct dc_state *dc_state, 928 struct dc_link *dc_link) 929 { 930 int i, j; 931 bool is_dsc_need_re_compute = false; 932 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 933 int new_stream_on_link_num = 0; 934 struct amdgpu_dm_connector *aconnector; 935 struct dc_stream_state *stream; 936 const struct dc *dc = dc_link->dc; 937 938 /* only check phy used by dsc mst branch */ 939 if (dc_link->type != dc_connection_mst_branch) 940 return false; 941 942 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 943 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 944 return false; 945 946 for (i = 0; i < MAX_PIPES; i++) 947 stream_on_link[i] = NULL; 948 949 /* check if there is mode change in new request */ 950 for (i = 0; i < dc_state->stream_count; i++) { 951 struct drm_crtc_state *new_crtc_state; 952 struct drm_connector_state *new_conn_state; 953 954 stream = dc_state->streams[i]; 955 if (!stream) 956 continue; 957 958 /* check if stream using the same link for mst */ 959 if (stream->link != dc_link) 960 continue; 961 962 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 963 if (!aconnector) 964 continue; 965 966 stream_on_link[new_stream_on_link_num] = aconnector; 967 new_stream_on_link_num++; 968 969 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 970 if (!new_conn_state) 971 continue; 972 973 if (IS_ERR(new_conn_state)) 974 continue; 975 976 if (!new_conn_state->crtc) 977 continue; 978 979 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 980 if (!new_crtc_state) 981 continue; 982 983 if (IS_ERR(new_crtc_state)) 984 continue; 985 986 if (new_crtc_state->enable && new_crtc_state->active) { 987 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 988 new_crtc_state->connectors_changed) 989 return true; 990 } 991 } 992 993 /* check current_state if there stream on link but it is not in 994 * new request state 995 */ 996 for (i = 0; i < dc->current_state->stream_count; i++) { 997 stream = dc->current_state->streams[i]; 998 /* only check stream on the mst hub */ 999 if (stream->link != dc_link) 1000 continue; 1001 1002 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1003 if (!aconnector) 1004 continue; 1005 1006 for (j = 0; j < new_stream_on_link_num; j++) { 1007 if (stream_on_link[j]) { 1008 if (aconnector == stream_on_link[j]) 1009 break; 1010 } 1011 } 1012 1013 if (j == new_stream_on_link_num) { 1014 /* not in new state */ 1015 is_dsc_need_re_compute = true; 1016 break; 1017 } 1018 } 1019 1020 return is_dsc_need_re_compute; 1021 } 1022 1023 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1024 struct dc_state *dc_state, 1025 struct dsc_mst_fairness_vars *vars) 1026 { 1027 int i, j; 1028 struct dc_stream_state *stream; 1029 bool computed_streams[MAX_PIPES]; 1030 struct amdgpu_dm_connector *aconnector; 1031 int link_vars_start_index = 0; 1032 1033 for (i = 0; i < dc_state->stream_count; i++) 1034 computed_streams[i] = false; 1035 1036 for (i = 0; i < dc_state->stream_count; i++) { 1037 stream = dc_state->streams[i]; 1038 1039 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1040 continue; 1041 1042 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1043 1044 if (!aconnector || !aconnector->dc_sink) 1045 continue; 1046 1047 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1048 continue; 1049 1050 if (computed_streams[i]) 1051 continue; 1052 1053 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1054 return false; 1055 1056 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1057 continue; 1058 1059 mutex_lock(&aconnector->mst_mgr.lock); 1060 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, 1061 vars, &link_vars_start_index)) { 1062 mutex_unlock(&aconnector->mst_mgr.lock); 1063 return false; 1064 } 1065 mutex_unlock(&aconnector->mst_mgr.lock); 1066 1067 for (j = 0; j < dc_state->stream_count; j++) { 1068 if (dc_state->streams[j]->link == stream->link) 1069 computed_streams[j] = true; 1070 } 1071 } 1072 1073 for (i = 0; i < dc_state->stream_count; i++) { 1074 stream = dc_state->streams[i]; 1075 1076 if (stream->timing.flags.DSC == 1) 1077 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1078 return false; 1079 } 1080 1081 return true; 1082 } 1083 1084 static bool 1085 pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1086 struct dc_state *dc_state, 1087 struct dsc_mst_fairness_vars *vars) 1088 { 1089 int i, j; 1090 struct dc_stream_state *stream; 1091 bool computed_streams[MAX_PIPES]; 1092 struct amdgpu_dm_connector *aconnector; 1093 int link_vars_start_index = 0; 1094 1095 for (i = 0; i < dc_state->stream_count; i++) 1096 computed_streams[i] = false; 1097 1098 for (i = 0; i < dc_state->stream_count; i++) { 1099 stream = dc_state->streams[i]; 1100 1101 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1102 continue; 1103 1104 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1105 1106 if (!aconnector || !aconnector->dc_sink) 1107 continue; 1108 1109 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1110 continue; 1111 1112 if (computed_streams[i]) 1113 continue; 1114 1115 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1116 continue; 1117 1118 mutex_lock(&aconnector->mst_mgr.lock); 1119 if (!compute_mst_dsc_configs_for_link(state, 1120 dc_state, 1121 stream->link, 1122 vars, 1123 &link_vars_start_index)) { 1124 mutex_unlock(&aconnector->mst_mgr.lock); 1125 return false; 1126 } 1127 mutex_unlock(&aconnector->mst_mgr.lock); 1128 1129 for (j = 0; j < dc_state->stream_count; j++) { 1130 if (dc_state->streams[j]->link == stream->link) 1131 computed_streams[j] = true; 1132 } 1133 } 1134 1135 return true; 1136 } 1137 1138 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1139 struct dc_stream_state *stream) 1140 { 1141 int i; 1142 struct drm_crtc *crtc; 1143 struct drm_crtc_state *new_state, *old_state; 1144 1145 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1146 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1147 1148 if (dm_state->stream == stream) 1149 return i; 1150 } 1151 return -1; 1152 } 1153 1154 static bool is_link_to_dschub(struct dc_link *dc_link) 1155 { 1156 union dpcd_dsc_basic_capabilities *dsc_caps = 1157 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1158 1159 /* only check phy used by dsc mst branch */ 1160 if (dc_link->type != dc_connection_mst_branch) 1161 return false; 1162 1163 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1164 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1165 return false; 1166 return true; 1167 } 1168 1169 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1170 { 1171 int i; 1172 struct drm_crtc *crtc; 1173 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1174 bool ret = false; 1175 1176 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1177 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1178 1179 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1180 ret = false; 1181 break; 1182 } 1183 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1184 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1185 ret = true; 1186 } 1187 return ret; 1188 } 1189 1190 void pre_validate_dsc(struct drm_atomic_state *state, 1191 struct dm_atomic_state **dm_state_ptr, 1192 struct dsc_mst_fairness_vars *vars) 1193 { 1194 int i; 1195 struct dm_atomic_state *dm_state; 1196 struct dc_state *local_dc_state = NULL; 1197 1198 if (!is_dsc_precompute_needed(state)) { 1199 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1200 return; 1201 } 1202 if (dm_atomic_get_state(state, dm_state_ptr)) { 1203 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1204 return; 1205 } 1206 dm_state = *dm_state_ptr; 1207 1208 /* 1209 * create local vailable for dc_state. copy content of streams of dm_state->context 1210 * to local variable. make sure stream pointer of local variable not the same as stream 1211 * from dm_state->context. 1212 */ 1213 1214 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1215 if (!local_dc_state) 1216 return; 1217 1218 for (i = 0; i < local_dc_state->stream_count; i++) { 1219 struct dc_stream_state *stream = dm_state->context->streams[i]; 1220 int ind = find_crtc_index_in_state_by_stream(state, stream); 1221 1222 if (ind >= 0) { 1223 struct amdgpu_dm_connector *aconnector; 1224 struct drm_connector_state *drm_new_conn_state; 1225 struct dm_connector_state *dm_new_conn_state; 1226 struct dm_crtc_state *dm_old_crtc_state; 1227 1228 aconnector = 1229 amdgpu_dm_find_first_crtc_matching_connector(state, 1230 state->crtcs[ind].ptr); 1231 drm_new_conn_state = 1232 drm_atomic_get_new_connector_state(state, 1233 &aconnector->base); 1234 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1235 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1236 1237 local_dc_state->streams[i] = 1238 create_validate_stream_for_sink(aconnector, 1239 &state->crtcs[ind].new_state->mode, 1240 dm_new_conn_state, 1241 dm_old_crtc_state->stream); 1242 } 1243 } 1244 1245 if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) { 1246 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1247 goto clean_exit; 1248 } 1249 1250 /* 1251 * compare local_streams -> timing with dm_state->context, 1252 * if the same set crtc_state->mode-change = 0; 1253 */ 1254 for (i = 0; i < local_dc_state->stream_count; i++) { 1255 struct dc_stream_state *stream = dm_state->context->streams[i]; 1256 1257 if (local_dc_state->streams[i] && 1258 is_timing_changed(stream, local_dc_state->streams[i])) { 1259 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1260 } else { 1261 int ind = find_crtc_index_in_state_by_stream(state, stream); 1262 1263 if (ind >= 0) 1264 state->crtcs[ind].new_state->mode_changed = 0; 1265 } 1266 } 1267 clean_exit: 1268 for (i = 0; i < local_dc_state->stream_count; i++) { 1269 struct dc_stream_state *stream = dm_state->context->streams[i]; 1270 1271 if (local_dc_state->streams[i] != stream) 1272 dc_stream_release(local_dc_state->streams[i]); 1273 } 1274 1275 kfree(local_dc_state); 1276 } 1277 #endif 1278