1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 35 #include "dc.h" 36 #include "dm_helpers.h" 37 38 #include "dc_link_ddc.h" 39 #include "dc_link_dp.h" 40 #include "ddc_service_types.h" 41 #include "dpcd_defs.h" 42 43 #include "i2caux_interface.h" 44 #include "dmub_cmd.h" 45 #if defined(CONFIG_DEBUG_FS) 46 #include "amdgpu_dm_debugfs.h" 47 #endif 48 49 #include "dc/dcn20/dcn20_resource.h" 50 bool is_timing_changed(struct dc_stream_state *cur_stream, 51 struct dc_stream_state *new_stream); 52 53 54 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 55 struct drm_dp_aux_msg *msg) 56 { 57 ssize_t result = 0; 58 struct aux_payload payload; 59 enum aux_return_code_type operation_result; 60 struct amdgpu_device *adev; 61 struct ddc_service *ddc; 62 63 if (WARN_ON(msg->size > 16)) 64 return -E2BIG; 65 66 payload.address = msg->address; 67 payload.data = msg->buffer; 68 payload.length = msg->size; 69 payload.reply = &msg->reply; 70 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 71 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 72 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 73 payload.write_status_update = 74 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 75 payload.defer_delay = 0; 76 77 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 78 &operation_result); 79 80 /* 81 * w/a on certain intel platform where hpd is unexpected to pull low during 82 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 83 * aux transaction is succuess in such case, therefore bypass the error 84 */ 85 ddc = TO_DM_AUX(aux)->ddc_service; 86 adev = ddc->ctx->driver_context; 87 if (adev->dm.aux_hpd_discon_quirk) { 88 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 89 operation_result == AUX_RET_ERROR_HPD_DISCON) { 90 result = 0; 91 operation_result = AUX_RET_SUCCESS; 92 } 93 } 94 95 if (payload.write && result >= 0) 96 result = msg->size; 97 98 if (result < 0) 99 switch (operation_result) { 100 case AUX_RET_SUCCESS: 101 break; 102 case AUX_RET_ERROR_HPD_DISCON: 103 case AUX_RET_ERROR_UNKNOWN: 104 case AUX_RET_ERROR_INVALID_OPERATION: 105 case AUX_RET_ERROR_PROTOCOL_ERROR: 106 result = -EIO; 107 break; 108 case AUX_RET_ERROR_INVALID_REPLY: 109 case AUX_RET_ERROR_ENGINE_ACQUIRE: 110 result = -EBUSY; 111 break; 112 case AUX_RET_ERROR_TIMEOUT: 113 result = -ETIMEDOUT; 114 break; 115 } 116 117 return result; 118 } 119 120 static void 121 dm_dp_mst_connector_destroy(struct drm_connector *connector) 122 { 123 struct amdgpu_dm_connector *aconnector = 124 to_amdgpu_dm_connector(connector); 125 126 if (aconnector->dc_sink) { 127 dc_link_remove_remote_sink(aconnector->dc_link, 128 aconnector->dc_sink); 129 dc_sink_release(aconnector->dc_sink); 130 } 131 132 kfree(aconnector->edid); 133 134 drm_connector_cleanup(connector); 135 drm_dp_mst_put_port_malloc(aconnector->port); 136 kfree(aconnector); 137 } 138 139 static int 140 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 141 { 142 struct amdgpu_dm_connector *amdgpu_dm_connector = 143 to_amdgpu_dm_connector(connector); 144 int r; 145 146 r = drm_dp_mst_connector_late_register(connector, 147 amdgpu_dm_connector->port); 148 if (r < 0) 149 return r; 150 151 #if defined(CONFIG_DEBUG_FS) 152 connector_debugfs_init(amdgpu_dm_connector); 153 #endif 154 155 return 0; 156 } 157 158 static void 159 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 160 { 161 struct amdgpu_dm_connector *aconnector = 162 to_amdgpu_dm_connector(connector); 163 struct drm_dp_mst_port *port = aconnector->port; 164 struct amdgpu_dm_connector *root = aconnector->mst_port; 165 struct dc_link *dc_link = aconnector->dc_link; 166 struct dc_sink *dc_sink = aconnector->dc_sink; 167 168 drm_dp_mst_connector_early_unregister(connector, port); 169 170 /* 171 * Release dc_sink for connector which its attached port is 172 * no longer in the mst topology 173 */ 174 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 175 if (dc_sink) { 176 if (dc_link->sink_count) 177 dc_link_remove_remote_sink(dc_link, dc_sink); 178 179 dc_sink_release(dc_sink); 180 aconnector->dc_sink = NULL; 181 aconnector->edid = NULL; 182 } 183 184 aconnector->mst_status = MST_STATUS_DEFAULT; 185 drm_modeset_unlock(&root->mst_mgr.base.lock); 186 } 187 188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 189 .fill_modes = drm_helper_probe_single_connector_modes, 190 .destroy = dm_dp_mst_connector_destroy, 191 .reset = amdgpu_dm_connector_funcs_reset, 192 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 193 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 194 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 195 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 196 .late_register = amdgpu_dm_mst_connector_late_register, 197 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 198 }; 199 200 #if defined(CONFIG_DRM_AMD_DC_DCN) 201 bool needs_dsc_aux_workaround(struct dc_link *link) 202 { 203 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 204 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 205 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 206 return true; 207 208 return false; 209 } 210 211 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 212 { 213 struct dc_sink *dc_sink = aconnector->dc_sink; 214 struct drm_dp_mst_port *port = aconnector->port; 215 u8 dsc_caps[16] = { 0 }; 216 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 217 u8 *dsc_branch_dec_caps = NULL; 218 219 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 220 221 /* 222 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 223 * because it only check the dsc/fec caps of the "port variable" and not the dock 224 * 225 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 226 * 227 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 228 * 229 */ 230 if (!aconnector->dsc_aux && !port->parent->port_parent && 231 needs_dsc_aux_workaround(aconnector->dc_link)) 232 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux; 233 234 if (!aconnector->dsc_aux) 235 return false; 236 237 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 238 return false; 239 240 if (drm_dp_dpcd_read(aconnector->dsc_aux, 241 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 242 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 243 244 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 245 dsc_caps, dsc_branch_dec_caps, 246 &dc_sink->dsc_caps.dsc_dec_caps)) 247 return false; 248 249 return true; 250 } 251 252 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 253 { 254 union dp_downstream_port_present ds_port_present; 255 256 if (!aconnector->dsc_aux) 257 return false; 258 259 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 260 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 261 return false; 262 } 263 264 aconnector->mst_downstream_port_present = ds_port_present; 265 DRM_INFO("Downstream port present %d, type %d\n", 266 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 267 268 return true; 269 } 270 #endif 271 272 static int dm_dp_mst_get_modes(struct drm_connector *connector) 273 { 274 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 275 int ret = 0; 276 277 if (!aconnector) 278 return drm_add_edid_modes(connector, NULL); 279 280 if (!aconnector->edid) { 281 struct edid *edid; 282 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port); 283 284 if (!edid) { 285 amdgpu_dm_set_mst_status(&aconnector->mst_status, 286 MST_REMOTE_EDID, false); 287 288 drm_connector_update_edid_property( 289 &aconnector->base, 290 NULL); 291 292 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 293 if (!aconnector->dc_sink) { 294 struct dc_sink *dc_sink; 295 struct dc_sink_init_data init_params = { 296 .link = aconnector->dc_link, 297 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 298 299 dc_sink = dc_link_add_remote_sink( 300 aconnector->dc_link, 301 NULL, 302 0, 303 &init_params); 304 305 if (!dc_sink) { 306 DRM_ERROR("Unable to add a remote sink\n"); 307 return 0; 308 } 309 310 dc_sink->priv = aconnector; 311 aconnector->dc_sink = dc_sink; 312 } 313 314 return ret; 315 } 316 317 aconnector->edid = edid; 318 amdgpu_dm_set_mst_status(&aconnector->mst_status, 319 MST_REMOTE_EDID, true); 320 } 321 322 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 323 dc_sink_release(aconnector->dc_sink); 324 aconnector->dc_sink = NULL; 325 } 326 327 if (!aconnector->dc_sink) { 328 struct dc_sink *dc_sink; 329 struct dc_sink_init_data init_params = { 330 .link = aconnector->dc_link, 331 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 332 dc_sink = dc_link_add_remote_sink( 333 aconnector->dc_link, 334 (uint8_t *)aconnector->edid, 335 (aconnector->edid->extensions + 1) * EDID_LENGTH, 336 &init_params); 337 338 if (!dc_sink) { 339 DRM_ERROR("Unable to add a remote sink\n"); 340 return 0; 341 } 342 343 dc_sink->priv = aconnector; 344 /* dc_link_add_remote_sink returns a new reference */ 345 aconnector->dc_sink = dc_sink; 346 347 if (aconnector->dc_sink) { 348 amdgpu_dm_update_freesync_caps( 349 connector, aconnector->edid); 350 351 #if defined(CONFIG_DRM_AMD_DC_DCN) 352 if (!validate_dsc_caps_on_connector(aconnector)) 353 memset(&aconnector->dc_sink->dsc_caps, 354 0, sizeof(aconnector->dc_sink->dsc_caps)); 355 356 if (!retrieve_downstream_port_device(aconnector)) 357 memset(&aconnector->mst_downstream_port_present, 358 0, sizeof(aconnector->mst_downstream_port_present)); 359 #endif 360 } 361 } 362 363 drm_connector_update_edid_property( 364 &aconnector->base, aconnector->edid); 365 366 ret = drm_add_edid_modes(connector, aconnector->edid); 367 368 return ret; 369 } 370 371 static struct drm_encoder * 372 dm_mst_atomic_best_encoder(struct drm_connector *connector, 373 struct drm_atomic_state *state) 374 { 375 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 376 connector); 377 struct drm_device *dev = connector->dev; 378 struct amdgpu_device *adev = drm_to_adev(dev); 379 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 380 381 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 382 } 383 384 static int 385 dm_dp_mst_detect(struct drm_connector *connector, 386 struct drm_modeset_acquire_ctx *ctx, bool force) 387 { 388 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 389 struct amdgpu_dm_connector *master = aconnector->mst_port; 390 struct drm_dp_mst_port *port = aconnector->port; 391 int connection_status; 392 393 if (drm_connector_is_unregistered(connector)) 394 return connector_status_disconnected; 395 396 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 397 aconnector->port); 398 399 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 400 uint8_t dpcd_rev; 401 int ret; 402 403 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 404 405 if (ret == 1) { 406 port->dpcd_rev = dpcd_rev; 407 408 /* Could be DP1.2 DP Rx case*/ 409 if (!dpcd_rev) { 410 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 411 412 if (ret == 1) 413 port->dpcd_rev = dpcd_rev; 414 } 415 416 if (!dpcd_rev) 417 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 418 } 419 420 /* 421 * Could be legacy sink, logical port etc on DP1.2. 422 * Will get Nack under these cases when issue remote 423 * DPCD read. 424 */ 425 if (ret != 1) 426 DRM_DEBUG_KMS("Can't access DPCD"); 427 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 428 port->dpcd_rev = 0; 429 } 430 431 /* 432 * Release dc_sink for connector which unplug event is notified by CSN msg 433 */ 434 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 435 if (aconnector->dc_link->sink_count) 436 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 437 438 dc_sink_release(aconnector->dc_sink); 439 aconnector->dc_sink = NULL; 440 aconnector->edid = NULL; 441 442 amdgpu_dm_set_mst_status(&aconnector->mst_status, 443 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 444 false); 445 } 446 447 return connection_status; 448 } 449 450 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 451 struct drm_atomic_state *state) 452 { 453 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 454 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr; 455 struct drm_dp_mst_port *mst_port = aconnector->port; 456 457 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 458 } 459 460 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 461 .get_modes = dm_dp_mst_get_modes, 462 .mode_valid = amdgpu_dm_connector_mode_valid, 463 .atomic_best_encoder = dm_mst_atomic_best_encoder, 464 .detect_ctx = dm_dp_mst_detect, 465 .atomic_check = dm_dp_mst_atomic_check, 466 }; 467 468 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 469 { 470 drm_encoder_cleanup(encoder); 471 kfree(encoder); 472 } 473 474 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 475 .destroy = amdgpu_dm_encoder_destroy, 476 }; 477 478 void 479 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 480 { 481 struct drm_device *dev = adev_to_drm(adev); 482 int i; 483 484 for (i = 0; i < adev->dm.display_indexes_num; i++) { 485 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 486 struct drm_encoder *encoder = &amdgpu_encoder->base; 487 488 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 489 490 drm_encoder_init( 491 dev, 492 &amdgpu_encoder->base, 493 &amdgpu_dm_encoder_funcs, 494 DRM_MODE_ENCODER_DPMST, 495 NULL); 496 497 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 498 } 499 } 500 501 static struct drm_connector * 502 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 503 struct drm_dp_mst_port *port, 504 const char *pathprop) 505 { 506 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 507 struct drm_device *dev = master->base.dev; 508 struct amdgpu_device *adev = drm_to_adev(dev); 509 struct amdgpu_dm_connector *aconnector; 510 struct drm_connector *connector; 511 int i; 512 513 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 514 if (!aconnector) 515 return NULL; 516 517 connector = &aconnector->base; 518 aconnector->port = port; 519 aconnector->mst_port = master; 520 amdgpu_dm_set_mst_status(&aconnector->mst_status, 521 MST_PROBE, true); 522 523 if (drm_connector_init( 524 dev, 525 connector, 526 &dm_dp_mst_connector_funcs, 527 DRM_MODE_CONNECTOR_DisplayPort)) { 528 kfree(aconnector); 529 return NULL; 530 } 531 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 532 533 amdgpu_dm_connector_init_helper( 534 &adev->dm, 535 aconnector, 536 DRM_MODE_CONNECTOR_DisplayPort, 537 master->dc_link, 538 master->connector_id); 539 540 for (i = 0; i < adev->dm.display_indexes_num; i++) { 541 drm_connector_attach_encoder(&aconnector->base, 542 &adev->dm.mst_encoders[i].base); 543 } 544 545 connector->max_bpc_property = master->base.max_bpc_property; 546 if (connector->max_bpc_property) 547 drm_connector_attach_max_bpc_property(connector, 8, 16); 548 549 connector->vrr_capable_property = master->base.vrr_capable_property; 550 if (connector->vrr_capable_property) 551 drm_connector_attach_vrr_capable_property(connector); 552 553 drm_object_attach_property( 554 &connector->base, 555 dev->mode_config.path_property, 556 0); 557 drm_object_attach_property( 558 &connector->base, 559 dev->mode_config.tile_property, 560 0); 561 562 drm_connector_set_path_property(connector, pathprop); 563 564 /* 565 * Initialize connector state before adding the connectror to drm and 566 * framebuffer lists 567 */ 568 amdgpu_dm_connector_funcs_reset(connector); 569 570 drm_dp_mst_get_port_malloc(port); 571 572 return connector; 573 } 574 575 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 576 .add_connector = dm_dp_add_mst_connector, 577 }; 578 579 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 580 struct amdgpu_dm_connector *aconnector, 581 int link_index) 582 { 583 struct dc_link_settings max_link_enc_cap = {0}; 584 585 aconnector->dm_dp_aux.aux.name = 586 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 587 link_index); 588 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 589 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 590 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 591 592 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 593 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 594 &aconnector->base); 595 596 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 597 return; 598 599 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 600 aconnector->mst_mgr.cbs = &dm_mst_cbs; 601 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 602 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 603 604 drm_connector_attach_dp_subconnector_property(&aconnector->base); 605 } 606 607 int dm_mst_get_pbn_divider(struct dc_link *link) 608 { 609 if (!link) 610 return 0; 611 612 return dc_link_bandwidth_kbps(link, 613 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 614 } 615 616 #if defined(CONFIG_DRM_AMD_DC_DCN) 617 618 struct dsc_mst_fairness_params { 619 struct dc_crtc_timing *timing; 620 struct dc_sink *sink; 621 struct dc_dsc_bw_range bw_range; 622 bool compression_possible; 623 struct drm_dp_mst_port *port; 624 enum dsc_clock_force_state clock_force_enable; 625 uint32_t num_slices_h; 626 uint32_t num_slices_v; 627 uint32_t bpp_overwrite; 628 struct amdgpu_dm_connector *aconnector; 629 }; 630 631 static int kbps_to_peak_pbn(int kbps) 632 { 633 u64 peak_kbps = kbps; 634 635 peak_kbps *= 1006; 636 peak_kbps = div_u64(peak_kbps, 1000); 637 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 638 } 639 640 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 641 struct dsc_mst_fairness_vars *vars, 642 int count, 643 int k) 644 { 645 struct drm_connector *drm_connector; 646 int i; 647 648 for (i = 0; i < count; i++) { 649 drm_connector = ¶ms[i].aconnector->base; 650 651 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 652 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 653 params[i].sink->ctx->dc->res_pool->dscs[0], 654 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 655 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override, 656 drm_connector->display_info.max_dsc_bpp, 657 0, 658 params[i].timing, 659 ¶ms[i].timing->dsc_cfg)) { 660 params[i].timing->flags.DSC = 1; 661 662 if (params[i].bpp_overwrite) 663 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 664 else 665 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 666 667 if (params[i].num_slices_h) 668 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 669 670 if (params[i].num_slices_v) 671 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 672 } else { 673 params[i].timing->flags.DSC = 0; 674 } 675 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 676 } 677 678 for (i = 0; i < count; i++) { 679 if (params[i].sink) { 680 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 681 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 682 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 683 params[i].sink->edid_caps.display_name); 684 } 685 686 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 687 params[i].timing->flags.DSC, 688 params[i].timing->dsc_cfg.bits_per_pixel, 689 vars[i + k].pbn); 690 } 691 } 692 693 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 694 { 695 struct dc_dsc_config dsc_config; 696 u64 kbps; 697 698 struct drm_connector *drm_connector = ¶m.aconnector->base; 699 uint32_t max_dsc_target_bpp_limit_override = 700 drm_connector->display_info.max_dsc_bpp; 701 702 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 703 dc_dsc_compute_config( 704 param.sink->ctx->dc->res_pool->dscs[0], 705 ¶m.sink->dsc_caps.dsc_dec_caps, 706 param.sink->ctx->dc->debug.dsc_min_slice_height_override, 707 max_dsc_target_bpp_limit_override, 708 (int) kbps, param.timing, &dsc_config); 709 710 return dsc_config.bits_per_pixel; 711 } 712 713 static int increase_dsc_bpp(struct drm_atomic_state *state, 714 struct drm_dp_mst_topology_state *mst_state, 715 struct dc_link *dc_link, 716 struct dsc_mst_fairness_params *params, 717 struct dsc_mst_fairness_vars *vars, 718 int count, 719 int k) 720 { 721 int i; 722 bool bpp_increased[MAX_PIPES]; 723 int initial_slack[MAX_PIPES]; 724 int min_initial_slack; 725 int next_index; 726 int remaining_to_increase = 0; 727 int link_timeslots_used; 728 int fair_pbn_alloc; 729 int ret = 0; 730 731 for (i = 0; i < count; i++) { 732 if (vars[i + k].dsc_enabled) { 733 initial_slack[i] = 734 kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn; 735 bpp_increased[i] = false; 736 remaining_to_increase += 1; 737 } else { 738 initial_slack[i] = 0; 739 bpp_increased[i] = true; 740 } 741 } 742 743 while (remaining_to_increase) { 744 next_index = -1; 745 min_initial_slack = -1; 746 for (i = 0; i < count; i++) { 747 if (!bpp_increased[i]) { 748 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 749 min_initial_slack = initial_slack[i]; 750 next_index = i; 751 } 752 } 753 } 754 755 if (next_index == -1) 756 break; 757 758 link_timeslots_used = 0; 759 760 for (i = 0; i < count; i++) 761 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); 762 763 fair_pbn_alloc = 764 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; 765 766 if (initial_slack[next_index] > fair_pbn_alloc) { 767 vars[next_index].pbn += fair_pbn_alloc; 768 ret = drm_dp_atomic_find_time_slots(state, 769 params[next_index].port->mgr, 770 params[next_index].port, 771 vars[next_index].pbn); 772 if (ret < 0) 773 return ret; 774 775 ret = drm_dp_mst_atomic_check(state); 776 if (ret == 0) { 777 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 778 } else { 779 vars[next_index].pbn -= fair_pbn_alloc; 780 ret = drm_dp_atomic_find_time_slots(state, 781 params[next_index].port->mgr, 782 params[next_index].port, 783 vars[next_index].pbn); 784 if (ret < 0) 785 return ret; 786 } 787 } else { 788 vars[next_index].pbn += initial_slack[next_index]; 789 ret = drm_dp_atomic_find_time_slots(state, 790 params[next_index].port->mgr, 791 params[next_index].port, 792 vars[next_index].pbn); 793 if (ret < 0) 794 return ret; 795 796 ret = drm_dp_mst_atomic_check(state); 797 if (ret == 0) { 798 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 799 } else { 800 vars[next_index].pbn -= initial_slack[next_index]; 801 ret = drm_dp_atomic_find_time_slots(state, 802 params[next_index].port->mgr, 803 params[next_index].port, 804 vars[next_index].pbn); 805 if (ret < 0) 806 return ret; 807 } 808 } 809 810 bpp_increased[next_index] = true; 811 remaining_to_increase--; 812 } 813 return 0; 814 } 815 816 static int try_disable_dsc(struct drm_atomic_state *state, 817 struct dc_link *dc_link, 818 struct dsc_mst_fairness_params *params, 819 struct dsc_mst_fairness_vars *vars, 820 int count, 821 int k) 822 { 823 int i; 824 bool tried[MAX_PIPES]; 825 int kbps_increase[MAX_PIPES]; 826 int max_kbps_increase; 827 int next_index; 828 int remaining_to_try = 0; 829 int ret; 830 831 for (i = 0; i < count; i++) { 832 if (vars[i + k].dsc_enabled 833 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 834 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 835 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 836 tried[i] = false; 837 remaining_to_try += 1; 838 } else { 839 kbps_increase[i] = 0; 840 tried[i] = true; 841 } 842 } 843 844 while (remaining_to_try) { 845 next_index = -1; 846 max_kbps_increase = -1; 847 for (i = 0; i < count; i++) { 848 if (!tried[i]) { 849 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 850 max_kbps_increase = kbps_increase[i]; 851 next_index = i; 852 } 853 } 854 } 855 856 if (next_index == -1) 857 break; 858 859 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps); 860 ret = drm_dp_atomic_find_time_slots(state, 861 params[next_index].port->mgr, 862 params[next_index].port, 863 vars[next_index].pbn); 864 if (ret < 0) 865 return ret; 866 867 ret = drm_dp_mst_atomic_check(state); 868 if (ret == 0) { 869 vars[next_index].dsc_enabled = false; 870 vars[next_index].bpp_x16 = 0; 871 } else { 872 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps); 873 ret = drm_dp_atomic_find_time_slots(state, 874 params[next_index].port->mgr, 875 params[next_index].port, 876 vars[next_index].pbn); 877 if (ret < 0) 878 return ret; 879 } 880 881 tried[next_index] = true; 882 remaining_to_try--; 883 } 884 return 0; 885 } 886 887 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 888 struct dc_state *dc_state, 889 struct dc_link *dc_link, 890 struct dsc_mst_fairness_vars *vars, 891 struct drm_dp_mst_topology_mgr *mgr, 892 int *link_vars_start_index) 893 { 894 struct dc_stream_state *stream; 895 struct dsc_mst_fairness_params params[MAX_PIPES]; 896 struct amdgpu_dm_connector *aconnector; 897 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 898 int count = 0; 899 int i, k, ret; 900 bool debugfs_overwrite = false; 901 902 memset(params, 0, sizeof(params)); 903 904 if (IS_ERR(mst_state)) 905 return PTR_ERR(mst_state); 906 907 mst_state->pbn_div = dm_mst_get_pbn_divider(dc_link); 908 #if defined(CONFIG_DRM_AMD_DC_DCN) 909 drm_dp_mst_update_slots(mst_state, dc_link_dp_mst_decide_link_encoding_format(dc_link)); 910 #endif 911 912 /* Set up params */ 913 for (i = 0; i < dc_state->stream_count; i++) { 914 struct dc_dsc_policy dsc_policy = {0}; 915 916 stream = dc_state->streams[i]; 917 918 if (stream->link != dc_link) 919 continue; 920 921 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 922 if (!aconnector) 923 continue; 924 925 if (!aconnector->port) 926 continue; 927 928 stream->timing.flags.DSC = 0; 929 930 params[count].timing = &stream->timing; 931 params[count].sink = stream->sink; 932 params[count].aconnector = aconnector; 933 params[count].port = aconnector->port; 934 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 935 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 936 debugfs_overwrite = true; 937 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 938 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 939 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 940 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 941 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 942 if (!dc_dsc_compute_bandwidth_range( 943 stream->sink->ctx->dc->res_pool->dscs[0], 944 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 945 dsc_policy.min_target_bpp * 16, 946 dsc_policy.max_target_bpp * 16, 947 &stream->sink->dsc_caps.dsc_dec_caps, 948 &stream->timing, ¶ms[count].bw_range)) 949 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 950 951 count++; 952 } 953 954 if (count == 0) { 955 ASSERT(0); 956 return 0; 957 } 958 959 /* k is start index of vars for current phy link used by mst hub */ 960 k = *link_vars_start_index; 961 /* set vars start index for next mst hub phy link */ 962 *link_vars_start_index += count; 963 964 /* Try no compression */ 965 for (i = 0; i < count; i++) { 966 vars[i + k].aconnector = params[i].aconnector; 967 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 968 vars[i + k].dsc_enabled = false; 969 vars[i + k].bpp_x16 = 0; 970 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 971 vars[i + k].pbn); 972 if (ret < 0) 973 return ret; 974 } 975 ret = drm_dp_mst_atomic_check(state); 976 if (ret == 0 && !debugfs_overwrite) { 977 set_dsc_configs_from_fairness_vars(params, vars, count, k); 978 return 0; 979 } else if (ret != -ENOSPC) { 980 return ret; 981 } 982 983 /* Try max compression */ 984 for (i = 0; i < count; i++) { 985 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 986 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps); 987 vars[i + k].dsc_enabled = true; 988 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 989 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 990 params[i].port, vars[i + k].pbn); 991 if (ret < 0) 992 return ret; 993 } else { 994 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 995 vars[i + k].dsc_enabled = false; 996 vars[i + k].bpp_x16 = 0; 997 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 998 params[i].port, vars[i + k].pbn); 999 if (ret < 0) 1000 return ret; 1001 } 1002 } 1003 ret = drm_dp_mst_atomic_check(state); 1004 if (ret != 0) 1005 return ret; 1006 1007 /* Optimize degree of compression */ 1008 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1009 if (ret < 0) 1010 return ret; 1011 1012 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1013 if (ret < 0) 1014 return ret; 1015 1016 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1017 1018 return 0; 1019 } 1020 1021 static bool is_dsc_need_re_compute( 1022 struct drm_atomic_state *state, 1023 struct dc_state *dc_state, 1024 struct dc_link *dc_link) 1025 { 1026 int i, j; 1027 bool is_dsc_need_re_compute = false; 1028 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1029 int new_stream_on_link_num = 0; 1030 struct amdgpu_dm_connector *aconnector; 1031 struct dc_stream_state *stream; 1032 const struct dc *dc = dc_link->dc; 1033 1034 /* only check phy used by dsc mst branch */ 1035 if (dc_link->type != dc_connection_mst_branch) 1036 return false; 1037 1038 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1039 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1040 return false; 1041 1042 for (i = 0; i < MAX_PIPES; i++) 1043 stream_on_link[i] = NULL; 1044 1045 /* check if there is mode change in new request */ 1046 for (i = 0; i < dc_state->stream_count; i++) { 1047 struct drm_crtc_state *new_crtc_state; 1048 struct drm_connector_state *new_conn_state; 1049 1050 stream = dc_state->streams[i]; 1051 if (!stream) 1052 continue; 1053 1054 /* check if stream using the same link for mst */ 1055 if (stream->link != dc_link) 1056 continue; 1057 1058 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1059 if (!aconnector) 1060 continue; 1061 1062 stream_on_link[new_stream_on_link_num] = aconnector; 1063 new_stream_on_link_num++; 1064 1065 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1066 if (!new_conn_state) 1067 continue; 1068 1069 if (IS_ERR(new_conn_state)) 1070 continue; 1071 1072 if (!new_conn_state->crtc) 1073 continue; 1074 1075 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1076 if (!new_crtc_state) 1077 continue; 1078 1079 if (IS_ERR(new_crtc_state)) 1080 continue; 1081 1082 if (new_crtc_state->enable && new_crtc_state->active) { 1083 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1084 new_crtc_state->connectors_changed) 1085 return true; 1086 } 1087 } 1088 1089 /* check current_state if there stream on link but it is not in 1090 * new request state 1091 */ 1092 for (i = 0; i < dc->current_state->stream_count; i++) { 1093 stream = dc->current_state->streams[i]; 1094 /* only check stream on the mst hub */ 1095 if (stream->link != dc_link) 1096 continue; 1097 1098 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1099 if (!aconnector) 1100 continue; 1101 1102 for (j = 0; j < new_stream_on_link_num; j++) { 1103 if (stream_on_link[j]) { 1104 if (aconnector == stream_on_link[j]) 1105 break; 1106 } 1107 } 1108 1109 if (j == new_stream_on_link_num) { 1110 /* not in new state */ 1111 is_dsc_need_re_compute = true; 1112 break; 1113 } 1114 } 1115 1116 return is_dsc_need_re_compute; 1117 } 1118 1119 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1120 struct dc_state *dc_state, 1121 struct dsc_mst_fairness_vars *vars) 1122 { 1123 int i, j; 1124 struct dc_stream_state *stream; 1125 bool computed_streams[MAX_PIPES]; 1126 struct amdgpu_dm_connector *aconnector; 1127 struct drm_dp_mst_topology_mgr *mst_mgr; 1128 int link_vars_start_index = 0; 1129 int ret = 0; 1130 1131 for (i = 0; i < dc_state->stream_count; i++) 1132 computed_streams[i] = false; 1133 1134 for (i = 0; i < dc_state->stream_count; i++) { 1135 stream = dc_state->streams[i]; 1136 1137 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1138 continue; 1139 1140 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1141 1142 if (!aconnector || !aconnector->dc_sink || !aconnector->port) 1143 continue; 1144 1145 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1146 continue; 1147 1148 if (computed_streams[i]) 1149 continue; 1150 1151 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1152 return -EINVAL; 1153 1154 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1155 continue; 1156 1157 mst_mgr = aconnector->port->mgr; 1158 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1159 &link_vars_start_index); 1160 if (ret != 0) 1161 return ret; 1162 1163 for (j = 0; j < dc_state->stream_count; j++) { 1164 if (dc_state->streams[j]->link == stream->link) 1165 computed_streams[j] = true; 1166 } 1167 } 1168 1169 for (i = 0; i < dc_state->stream_count; i++) { 1170 stream = dc_state->streams[i]; 1171 1172 if (stream->timing.flags.DSC == 1) 1173 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1174 return -EINVAL; 1175 } 1176 1177 return ret; 1178 } 1179 1180 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1181 struct dc_state *dc_state, 1182 struct dsc_mst_fairness_vars *vars) 1183 { 1184 int i, j; 1185 struct dc_stream_state *stream; 1186 bool computed_streams[MAX_PIPES]; 1187 struct amdgpu_dm_connector *aconnector; 1188 struct drm_dp_mst_topology_mgr *mst_mgr; 1189 int link_vars_start_index = 0; 1190 int ret = 0; 1191 1192 for (i = 0; i < dc_state->stream_count; i++) 1193 computed_streams[i] = false; 1194 1195 for (i = 0; i < dc_state->stream_count; i++) { 1196 stream = dc_state->streams[i]; 1197 1198 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1199 continue; 1200 1201 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1202 1203 if (!aconnector || !aconnector->dc_sink || !aconnector->port) 1204 continue; 1205 1206 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1207 continue; 1208 1209 if (computed_streams[i]) 1210 continue; 1211 1212 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1213 continue; 1214 1215 mst_mgr = aconnector->port->mgr; 1216 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1217 &link_vars_start_index); 1218 if (ret != 0) 1219 return ret; 1220 1221 for (j = 0; j < dc_state->stream_count; j++) { 1222 if (dc_state->streams[j]->link == stream->link) 1223 computed_streams[j] = true; 1224 } 1225 } 1226 1227 return ret; 1228 } 1229 1230 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1231 struct dc_stream_state *stream) 1232 { 1233 int i; 1234 struct drm_crtc *crtc; 1235 struct drm_crtc_state *new_state, *old_state; 1236 1237 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1238 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1239 1240 if (dm_state->stream == stream) 1241 return i; 1242 } 1243 return -1; 1244 } 1245 1246 static bool is_link_to_dschub(struct dc_link *dc_link) 1247 { 1248 union dpcd_dsc_basic_capabilities *dsc_caps = 1249 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1250 1251 /* only check phy used by dsc mst branch */ 1252 if (dc_link->type != dc_connection_mst_branch) 1253 return false; 1254 1255 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1256 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1257 return false; 1258 return true; 1259 } 1260 1261 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1262 { 1263 int i; 1264 struct drm_crtc *crtc; 1265 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1266 bool ret = false; 1267 1268 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1269 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1270 1271 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1272 ret = false; 1273 break; 1274 } 1275 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1276 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1277 ret = true; 1278 } 1279 return ret; 1280 } 1281 1282 int pre_validate_dsc(struct drm_atomic_state *state, 1283 struct dm_atomic_state **dm_state_ptr, 1284 struct dsc_mst_fairness_vars *vars) 1285 { 1286 int i; 1287 struct dm_atomic_state *dm_state; 1288 struct dc_state *local_dc_state = NULL; 1289 int ret = 0; 1290 1291 if (!is_dsc_precompute_needed(state)) { 1292 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1293 return 0; 1294 } 1295 ret = dm_atomic_get_state(state, dm_state_ptr); 1296 if (ret != 0) { 1297 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1298 return ret; 1299 } 1300 dm_state = *dm_state_ptr; 1301 1302 /* 1303 * create local vailable for dc_state. copy content of streams of dm_state->context 1304 * to local variable. make sure stream pointer of local variable not the same as stream 1305 * from dm_state->context. 1306 */ 1307 1308 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1309 if (!local_dc_state) 1310 return -ENOMEM; 1311 1312 for (i = 0; i < local_dc_state->stream_count; i++) { 1313 struct dc_stream_state *stream = dm_state->context->streams[i]; 1314 int ind = find_crtc_index_in_state_by_stream(state, stream); 1315 1316 if (ind >= 0) { 1317 struct amdgpu_dm_connector *aconnector; 1318 struct drm_connector_state *drm_new_conn_state; 1319 struct dm_connector_state *dm_new_conn_state; 1320 struct dm_crtc_state *dm_old_crtc_state; 1321 1322 aconnector = 1323 amdgpu_dm_find_first_crtc_matching_connector(state, 1324 state->crtcs[ind].ptr); 1325 drm_new_conn_state = 1326 drm_atomic_get_new_connector_state(state, 1327 &aconnector->base); 1328 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1329 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1330 1331 local_dc_state->streams[i] = 1332 create_validate_stream_for_sink(aconnector, 1333 &state->crtcs[ind].new_state->mode, 1334 dm_new_conn_state, 1335 dm_old_crtc_state->stream); 1336 if (local_dc_state->streams[i] == NULL) { 1337 ret = -EINVAL; 1338 break; 1339 } 1340 } 1341 } 1342 1343 if (ret != 0) 1344 goto clean_exit; 1345 1346 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1347 if (ret != 0) { 1348 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1349 goto clean_exit; 1350 } 1351 1352 /* 1353 * compare local_streams -> timing with dm_state->context, 1354 * if the same set crtc_state->mode-change = 0; 1355 */ 1356 for (i = 0; i < local_dc_state->stream_count; i++) { 1357 struct dc_stream_state *stream = dm_state->context->streams[i]; 1358 1359 if (local_dc_state->streams[i] && 1360 is_timing_changed(stream, local_dc_state->streams[i])) { 1361 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1362 } else { 1363 int ind = find_crtc_index_in_state_by_stream(state, stream); 1364 1365 if (ind >= 0) 1366 state->crtcs[ind].new_state->mode_changed = 0; 1367 } 1368 } 1369 clean_exit: 1370 for (i = 0; i < local_dc_state->stream_count; i++) { 1371 struct dc_stream_state *stream = dm_state->context->streams[i]; 1372 1373 if (local_dc_state->streams[i] != stream) 1374 dc_stream_release(local_dc_state->streams[i]); 1375 } 1376 1377 kfree(local_dc_state); 1378 1379 return ret; 1380 } 1381 1382 static unsigned int kbps_from_pbn(unsigned int pbn) 1383 { 1384 unsigned int kbps = pbn; 1385 1386 kbps *= (1000000 / PEAK_FACTOR_X1000); 1387 kbps *= 8; 1388 kbps *= 54; 1389 kbps /= 64; 1390 1391 return kbps; 1392 } 1393 1394 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1395 struct dc_dsc_bw_range *bw_range) 1396 { 1397 struct dc_dsc_policy dsc_policy = {0}; 1398 1399 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); 1400 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1401 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1402 dsc_policy.min_target_bpp * 16, 1403 dsc_policy.max_target_bpp * 16, 1404 &stream->sink->dsc_caps.dsc_dec_caps, 1405 &stream->timing, bw_range); 1406 1407 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1408 } 1409 #endif /* CONFIG_DRM_AMD_DC_DCN */ 1410 1411 enum dc_status dm_dp_mst_is_port_support_mode( 1412 struct amdgpu_dm_connector *aconnector, 1413 struct dc_stream_state *stream) 1414 { 1415 int bpp, pbn, branch_max_throughput_mps = 0; 1416 #if defined(CONFIG_DRM_AMD_DC_DCN) 1417 struct dc_link_settings cur_link_settings; 1418 unsigned int end_to_end_bw_in_kbps = 0; 1419 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1420 unsigned int max_compressed_bw_in_kbps = 0; 1421 struct dc_dsc_bw_range bw_range = {0}; 1422 struct drm_dp_mst_topology_mgr *mst_mgr; 1423 1424 /* 1425 * check if the mode could be supported if DSC pass-through is supported 1426 * AND check if there enough bandwidth available to support the mode 1427 * with DSC enabled. 1428 */ 1429 if (is_dsc_common_config_possible(stream, &bw_range) && 1430 aconnector->port->passthrough_aux) { 1431 mst_mgr = aconnector->port->mgr; 1432 mutex_lock(&mst_mgr->lock); 1433 1434 cur_link_settings = stream->link->verified_link_cap; 1435 1436 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1437 &cur_link_settings 1438 ); 1439 down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn); 1440 1441 /* pick the bottleneck */ 1442 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, 1443 down_link_bw_in_kbps); 1444 1445 mutex_unlock(&mst_mgr->lock); 1446 1447 /* 1448 * use the maximum dsc compression bandwidth as the required 1449 * bandwidth for the mode 1450 */ 1451 max_compressed_bw_in_kbps = bw_range.min_kbps; 1452 1453 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) { 1454 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n"); 1455 return DC_FAIL_BANDWIDTH_VALIDATE; 1456 } 1457 } else { 1458 #endif 1459 /* check if mode could be supported within full_pbn */ 1460 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1461 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); 1462 1463 if (pbn > aconnector->port->full_pbn) 1464 return DC_FAIL_BANDWIDTH_VALIDATE; 1465 #if defined(CONFIG_DRM_AMD_DC_DCN) 1466 } 1467 #endif 1468 1469 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1470 switch (stream->timing.pixel_encoding) { 1471 case PIXEL_ENCODING_RGB: 1472 case PIXEL_ENCODING_YCBCR444: 1473 branch_max_throughput_mps = 1474 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1475 break; 1476 case PIXEL_ENCODING_YCBCR422: 1477 case PIXEL_ENCODING_YCBCR420: 1478 branch_max_throughput_mps = 1479 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1480 break; 1481 default: 1482 break; 1483 } 1484 1485 if (branch_max_throughput_mps != 0 && 1486 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1487 return DC_FAIL_BANDWIDTH_VALIDATE; 1488 1489 return DC_OK; 1490 } 1491