1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 35 #ifdef CONFIG_DRM_AMD_DC_HDCP 36 #include "amdgpu_dm_hdcp.h" 37 #endif 38 39 #include "dc.h" 40 #include "dm_helpers.h" 41 42 #include "ddc_service_types.h" 43 #include "dpcd_defs.h" 44 45 #include "dmub_cmd.h" 46 #if defined(CONFIG_DEBUG_FS) 47 #include "amdgpu_dm_debugfs.h" 48 #endif 49 50 #include "dc/dcn20/dcn20_resource.h" 51 bool is_timing_changed(struct dc_stream_state *cur_stream, 52 struct dc_stream_state *new_stream); 53 #define PEAK_FACTOR_X1000 1006 54 55 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 56 struct drm_dp_aux_msg *msg) 57 { 58 ssize_t result = 0; 59 struct aux_payload payload; 60 enum aux_return_code_type operation_result; 61 struct amdgpu_device *adev; 62 struct ddc_service *ddc; 63 64 if (WARN_ON(msg->size > 16)) 65 return -E2BIG; 66 67 payload.address = msg->address; 68 payload.data = msg->buffer; 69 payload.length = msg->size; 70 payload.reply = &msg->reply; 71 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 72 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 73 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 74 payload.write_status_update = 75 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 76 payload.defer_delay = 0; 77 78 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 79 &operation_result); 80 81 /* 82 * w/a on certain intel platform where hpd is unexpected to pull low during 83 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 84 * aux transaction is succuess in such case, therefore bypass the error 85 */ 86 ddc = TO_DM_AUX(aux)->ddc_service; 87 adev = ddc->ctx->driver_context; 88 if (adev->dm.aux_hpd_discon_quirk) { 89 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 90 operation_result == AUX_RET_ERROR_HPD_DISCON) { 91 result = 0; 92 operation_result = AUX_RET_SUCCESS; 93 } 94 } 95 96 if (payload.write && result >= 0) 97 result = msg->size; 98 99 if (result < 0) 100 switch (operation_result) { 101 case AUX_RET_SUCCESS: 102 break; 103 case AUX_RET_ERROR_HPD_DISCON: 104 case AUX_RET_ERROR_UNKNOWN: 105 case AUX_RET_ERROR_INVALID_OPERATION: 106 case AUX_RET_ERROR_PROTOCOL_ERROR: 107 result = -EIO; 108 break; 109 case AUX_RET_ERROR_INVALID_REPLY: 110 case AUX_RET_ERROR_ENGINE_ACQUIRE: 111 result = -EBUSY; 112 break; 113 case AUX_RET_ERROR_TIMEOUT: 114 result = -ETIMEDOUT; 115 break; 116 } 117 118 return result; 119 } 120 121 static void 122 dm_dp_mst_connector_destroy(struct drm_connector *connector) 123 { 124 struct amdgpu_dm_connector *aconnector = 125 to_amdgpu_dm_connector(connector); 126 127 if (aconnector->dc_sink) { 128 dc_link_remove_remote_sink(aconnector->dc_link, 129 aconnector->dc_sink); 130 dc_sink_release(aconnector->dc_sink); 131 } 132 133 kfree(aconnector->edid); 134 135 drm_connector_cleanup(connector); 136 drm_dp_mst_put_port_malloc(aconnector->mst_output_port); 137 kfree(aconnector); 138 } 139 140 static int 141 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 142 { 143 struct amdgpu_dm_connector *amdgpu_dm_connector = 144 to_amdgpu_dm_connector(connector); 145 int r; 146 147 r = drm_dp_mst_connector_late_register(connector, 148 amdgpu_dm_connector->mst_output_port); 149 if (r < 0) 150 return r; 151 152 #if defined(CONFIG_DEBUG_FS) 153 connector_debugfs_init(amdgpu_dm_connector); 154 #endif 155 156 return 0; 157 } 158 159 static void 160 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 161 { 162 struct amdgpu_dm_connector *aconnector = 163 to_amdgpu_dm_connector(connector); 164 struct drm_dp_mst_port *port = aconnector->mst_output_port; 165 struct amdgpu_dm_connector *root = aconnector->mst_root; 166 struct dc_link *dc_link = aconnector->dc_link; 167 struct dc_sink *dc_sink = aconnector->dc_sink; 168 169 drm_dp_mst_connector_early_unregister(connector, port); 170 171 /* 172 * Release dc_sink for connector which its attached port is 173 * no longer in the mst topology 174 */ 175 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 176 if (dc_sink) { 177 if (dc_link->sink_count) 178 dc_link_remove_remote_sink(dc_link, dc_sink); 179 180 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 181 dc_sink, dc_link->sink_count); 182 183 dc_sink_release(dc_sink); 184 aconnector->dc_sink = NULL; 185 aconnector->edid = NULL; 186 } 187 188 aconnector->mst_status = MST_STATUS_DEFAULT; 189 drm_modeset_unlock(&root->mst_mgr.base.lock); 190 } 191 192 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 193 .fill_modes = drm_helper_probe_single_connector_modes, 194 .destroy = dm_dp_mst_connector_destroy, 195 .reset = amdgpu_dm_connector_funcs_reset, 196 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 197 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 198 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 199 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 200 .late_register = amdgpu_dm_mst_connector_late_register, 201 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 202 }; 203 204 #if defined(CONFIG_DRM_AMD_DC_DCN) 205 bool needs_dsc_aux_workaround(struct dc_link *link) 206 { 207 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 208 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 209 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 210 return true; 211 212 return false; 213 } 214 215 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 216 { 217 struct dc_sink *dc_sink = aconnector->dc_sink; 218 struct drm_dp_mst_port *port = aconnector->mst_output_port; 219 u8 dsc_caps[16] = { 0 }; 220 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 221 u8 *dsc_branch_dec_caps = NULL; 222 223 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 224 225 /* 226 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 227 * because it only check the dsc/fec caps of the "port variable" and not the dock 228 * 229 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 230 * 231 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 232 * 233 */ 234 if (!aconnector->dsc_aux && !port->parent->port_parent && 235 needs_dsc_aux_workaround(aconnector->dc_link)) 236 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; 237 238 if (!aconnector->dsc_aux) 239 return false; 240 241 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 242 return false; 243 244 if (drm_dp_dpcd_read(aconnector->dsc_aux, 245 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 246 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 247 248 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 249 dsc_caps, dsc_branch_dec_caps, 250 &dc_sink->dsc_caps.dsc_dec_caps)) 251 return false; 252 253 return true; 254 } 255 256 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 257 { 258 union dp_downstream_port_present ds_port_present; 259 260 if (!aconnector->dsc_aux) 261 return false; 262 263 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 264 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 265 return false; 266 } 267 268 aconnector->mst_downstream_port_present = ds_port_present; 269 DRM_INFO("Downstream port present %d, type %d\n", 270 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 271 272 return true; 273 } 274 #endif 275 276 static int dm_dp_mst_get_modes(struct drm_connector *connector) 277 { 278 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 279 int ret = 0; 280 281 if (!aconnector) 282 return drm_add_edid_modes(connector, NULL); 283 284 if (!aconnector->edid) { 285 struct edid *edid; 286 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); 287 288 if (!edid) { 289 amdgpu_dm_set_mst_status(&aconnector->mst_status, 290 MST_REMOTE_EDID, false); 291 292 drm_connector_update_edid_property( 293 &aconnector->base, 294 NULL); 295 296 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 297 if (!aconnector->dc_sink) { 298 struct dc_sink *dc_sink; 299 struct dc_sink_init_data init_params = { 300 .link = aconnector->dc_link, 301 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 302 303 dc_sink = dc_link_add_remote_sink( 304 aconnector->dc_link, 305 NULL, 306 0, 307 &init_params); 308 309 if (!dc_sink) { 310 DRM_ERROR("Unable to add a remote sink\n"); 311 return 0; 312 } 313 314 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 315 dc_sink, aconnector->dc_link->sink_count); 316 317 dc_sink->priv = aconnector; 318 aconnector->dc_sink = dc_sink; 319 } 320 321 return ret; 322 } 323 324 aconnector->edid = edid; 325 amdgpu_dm_set_mst_status(&aconnector->mst_status, 326 MST_REMOTE_EDID, true); 327 } 328 329 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 330 dc_sink_release(aconnector->dc_sink); 331 aconnector->dc_sink = NULL; 332 } 333 334 if (!aconnector->dc_sink) { 335 struct dc_sink *dc_sink; 336 struct dc_sink_init_data init_params = { 337 .link = aconnector->dc_link, 338 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 339 dc_sink = dc_link_add_remote_sink( 340 aconnector->dc_link, 341 (uint8_t *)aconnector->edid, 342 (aconnector->edid->extensions + 1) * EDID_LENGTH, 343 &init_params); 344 345 if (!dc_sink) { 346 DRM_ERROR("Unable to add a remote sink\n"); 347 return 0; 348 } 349 350 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 351 dc_sink, aconnector->dc_link->sink_count); 352 353 dc_sink->priv = aconnector; 354 /* dc_link_add_remote_sink returns a new reference */ 355 aconnector->dc_sink = dc_sink; 356 357 /* when display is unplugged from mst hub, connctor will be 358 * destroyed within dm_dp_mst_connector_destroy. connector 359 * hdcp perperties, like type, undesired, desired, enabled, 360 * will be lost. So, save hdcp properties into hdcp_work within 361 * amdgpu_dm_atomic_commit_tail. if the same display is 362 * plugged back with same display index, its hdcp properties 363 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 364 */ 365 #ifdef CONFIG_DRM_AMD_DC_HDCP 366 if (aconnector->dc_sink && connector->state) { 367 struct drm_device *dev = connector->dev; 368 struct amdgpu_device *adev = drm_to_adev(dev); 369 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 370 struct hdcp_workqueue *hdcp_w = &hdcp_work[aconnector->dc_link->link_index]; 371 372 connector->state->hdcp_content_type = 373 hdcp_w->hdcp_content_type[connector->index]; 374 connector->state->content_protection = 375 hdcp_w->content_protection[connector->index]; 376 } 377 #endif 378 379 if (aconnector->dc_sink) { 380 amdgpu_dm_update_freesync_caps( 381 connector, aconnector->edid); 382 383 #if defined(CONFIG_DRM_AMD_DC_DCN) 384 if (!validate_dsc_caps_on_connector(aconnector)) 385 memset(&aconnector->dc_sink->dsc_caps, 386 0, sizeof(aconnector->dc_sink->dsc_caps)); 387 388 if (!retrieve_downstream_port_device(aconnector)) 389 memset(&aconnector->mst_downstream_port_present, 390 0, sizeof(aconnector->mst_downstream_port_present)); 391 #endif 392 } 393 } 394 395 drm_connector_update_edid_property( 396 &aconnector->base, aconnector->edid); 397 398 ret = drm_add_edid_modes(connector, aconnector->edid); 399 400 return ret; 401 } 402 403 static struct drm_encoder * 404 dm_mst_atomic_best_encoder(struct drm_connector *connector, 405 struct drm_atomic_state *state) 406 { 407 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 408 connector); 409 struct drm_device *dev = connector->dev; 410 struct amdgpu_device *adev = drm_to_adev(dev); 411 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 412 413 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 414 } 415 416 static int 417 dm_dp_mst_detect(struct drm_connector *connector, 418 struct drm_modeset_acquire_ctx *ctx, bool force) 419 { 420 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 421 struct amdgpu_dm_connector *master = aconnector->mst_root; 422 struct drm_dp_mst_port *port = aconnector->mst_output_port; 423 int connection_status; 424 425 if (drm_connector_is_unregistered(connector)) 426 return connector_status_disconnected; 427 428 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 429 aconnector->mst_output_port); 430 431 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 432 uint8_t dpcd_rev; 433 int ret; 434 435 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 436 437 if (ret == 1) { 438 port->dpcd_rev = dpcd_rev; 439 440 /* Could be DP1.2 DP Rx case*/ 441 if (!dpcd_rev) { 442 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 443 444 if (ret == 1) 445 port->dpcd_rev = dpcd_rev; 446 } 447 448 if (!dpcd_rev) 449 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 450 } 451 452 /* 453 * Could be legacy sink, logical port etc on DP1.2. 454 * Will get Nack under these cases when issue remote 455 * DPCD read. 456 */ 457 if (ret != 1) 458 DRM_DEBUG_KMS("Can't access DPCD"); 459 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 460 port->dpcd_rev = 0; 461 } 462 463 /* 464 * Release dc_sink for connector which unplug event is notified by CSN msg 465 */ 466 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 467 if (aconnector->dc_link->sink_count) 468 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 469 470 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 471 aconnector->dc_link, aconnector->dc_link->sink_count); 472 473 dc_sink_release(aconnector->dc_sink); 474 aconnector->dc_sink = NULL; 475 aconnector->edid = NULL; 476 477 amdgpu_dm_set_mst_status(&aconnector->mst_status, 478 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 479 false); 480 } 481 482 return connection_status; 483 } 484 485 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 486 struct drm_atomic_state *state) 487 { 488 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 489 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; 490 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; 491 492 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 493 } 494 495 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 496 .get_modes = dm_dp_mst_get_modes, 497 .mode_valid = amdgpu_dm_connector_mode_valid, 498 .atomic_best_encoder = dm_mst_atomic_best_encoder, 499 .detect_ctx = dm_dp_mst_detect, 500 .atomic_check = dm_dp_mst_atomic_check, 501 }; 502 503 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 504 { 505 drm_encoder_cleanup(encoder); 506 } 507 508 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 509 .destroy = amdgpu_dm_encoder_destroy, 510 }; 511 512 void 513 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 514 { 515 struct drm_device *dev = adev_to_drm(adev); 516 int i; 517 518 for (i = 0; i < adev->dm.display_indexes_num; i++) { 519 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 520 struct drm_encoder *encoder = &amdgpu_encoder->base; 521 522 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 523 524 drm_encoder_init( 525 dev, 526 &amdgpu_encoder->base, 527 &amdgpu_dm_encoder_funcs, 528 DRM_MODE_ENCODER_DPMST, 529 NULL); 530 531 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 532 } 533 } 534 535 static struct drm_connector * 536 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 537 struct drm_dp_mst_port *port, 538 const char *pathprop) 539 { 540 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 541 struct drm_device *dev = master->base.dev; 542 struct amdgpu_device *adev = drm_to_adev(dev); 543 struct amdgpu_dm_connector *aconnector; 544 struct drm_connector *connector; 545 int i; 546 547 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 548 if (!aconnector) 549 return NULL; 550 551 connector = &aconnector->base; 552 aconnector->mst_output_port = port; 553 aconnector->mst_root = master; 554 amdgpu_dm_set_mst_status(&aconnector->mst_status, 555 MST_PROBE, true); 556 557 if (drm_connector_init( 558 dev, 559 connector, 560 &dm_dp_mst_connector_funcs, 561 DRM_MODE_CONNECTOR_DisplayPort)) { 562 kfree(aconnector); 563 return NULL; 564 } 565 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 566 567 amdgpu_dm_connector_init_helper( 568 &adev->dm, 569 aconnector, 570 DRM_MODE_CONNECTOR_DisplayPort, 571 master->dc_link, 572 master->connector_id); 573 574 for (i = 0; i < adev->dm.display_indexes_num; i++) { 575 drm_connector_attach_encoder(&aconnector->base, 576 &adev->dm.mst_encoders[i].base); 577 } 578 579 connector->max_bpc_property = master->base.max_bpc_property; 580 if (connector->max_bpc_property) 581 drm_connector_attach_max_bpc_property(connector, 8, 16); 582 583 connector->vrr_capable_property = master->base.vrr_capable_property; 584 if (connector->vrr_capable_property) 585 drm_connector_attach_vrr_capable_property(connector); 586 587 drm_object_attach_property( 588 &connector->base, 589 dev->mode_config.path_property, 590 0); 591 drm_object_attach_property( 592 &connector->base, 593 dev->mode_config.tile_property, 594 0); 595 596 drm_connector_set_path_property(connector, pathprop); 597 598 /* 599 * Initialize connector state before adding the connectror to drm and 600 * framebuffer lists 601 */ 602 amdgpu_dm_connector_funcs_reset(connector); 603 604 drm_dp_mst_get_port_malloc(port); 605 606 return connector; 607 } 608 609 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 610 .add_connector = dm_dp_add_mst_connector, 611 }; 612 613 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 614 struct amdgpu_dm_connector *aconnector, 615 int link_index) 616 { 617 struct dc_link_settings max_link_enc_cap = {0}; 618 619 aconnector->dm_dp_aux.aux.name = 620 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 621 link_index); 622 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 623 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 624 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 625 626 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 627 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 628 &aconnector->base); 629 630 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 631 return; 632 633 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 634 aconnector->mst_mgr.cbs = &dm_mst_cbs; 635 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 636 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 637 638 drm_connector_attach_dp_subconnector_property(&aconnector->base); 639 } 640 641 int dm_mst_get_pbn_divider(struct dc_link *link) 642 { 643 if (!link) 644 return 0; 645 646 return dc_link_bandwidth_kbps(link, 647 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 648 } 649 650 #if defined(CONFIG_DRM_AMD_DC_DCN) 651 652 struct dsc_mst_fairness_params { 653 struct dc_crtc_timing *timing; 654 struct dc_sink *sink; 655 struct dc_dsc_bw_range bw_range; 656 bool compression_possible; 657 struct drm_dp_mst_port *port; 658 enum dsc_clock_force_state clock_force_enable; 659 uint32_t num_slices_h; 660 uint32_t num_slices_v; 661 uint32_t bpp_overwrite; 662 struct amdgpu_dm_connector *aconnector; 663 }; 664 665 static int kbps_to_peak_pbn(int kbps) 666 { 667 u64 peak_kbps = kbps; 668 669 peak_kbps *= 1006; 670 peak_kbps = div_u64(peak_kbps, 1000); 671 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 672 } 673 674 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 675 struct dsc_mst_fairness_vars *vars, 676 int count, 677 int k) 678 { 679 struct drm_connector *drm_connector; 680 int i; 681 682 for (i = 0; i < count; i++) { 683 drm_connector = ¶ms[i].aconnector->base; 684 685 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 686 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 687 params[i].sink->ctx->dc->res_pool->dscs[0], 688 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 689 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override, 690 drm_connector->display_info.max_dsc_bpp, 691 0, 692 params[i].timing, 693 ¶ms[i].timing->dsc_cfg)) { 694 params[i].timing->flags.DSC = 1; 695 696 if (params[i].bpp_overwrite) 697 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 698 else 699 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 700 701 if (params[i].num_slices_h) 702 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 703 704 if (params[i].num_slices_v) 705 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 706 } else { 707 params[i].timing->flags.DSC = 0; 708 } 709 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 710 } 711 712 for (i = 0; i < count; i++) { 713 if (params[i].sink) { 714 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 715 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 716 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 717 params[i].sink->edid_caps.display_name); 718 } 719 720 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 721 params[i].timing->flags.DSC, 722 params[i].timing->dsc_cfg.bits_per_pixel, 723 vars[i + k].pbn); 724 } 725 } 726 727 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 728 { 729 struct dc_dsc_config dsc_config; 730 u64 kbps; 731 732 struct drm_connector *drm_connector = ¶m.aconnector->base; 733 uint32_t max_dsc_target_bpp_limit_override = 734 drm_connector->display_info.max_dsc_bpp; 735 736 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 737 dc_dsc_compute_config( 738 param.sink->ctx->dc->res_pool->dscs[0], 739 ¶m.sink->dsc_caps.dsc_dec_caps, 740 param.sink->ctx->dc->debug.dsc_min_slice_height_override, 741 max_dsc_target_bpp_limit_override, 742 (int) kbps, param.timing, &dsc_config); 743 744 return dsc_config.bits_per_pixel; 745 } 746 747 static int increase_dsc_bpp(struct drm_atomic_state *state, 748 struct drm_dp_mst_topology_state *mst_state, 749 struct dc_link *dc_link, 750 struct dsc_mst_fairness_params *params, 751 struct dsc_mst_fairness_vars *vars, 752 int count, 753 int k) 754 { 755 int i; 756 bool bpp_increased[MAX_PIPES]; 757 int initial_slack[MAX_PIPES]; 758 int min_initial_slack; 759 int next_index; 760 int remaining_to_increase = 0; 761 int link_timeslots_used; 762 int fair_pbn_alloc; 763 int ret = 0; 764 765 for (i = 0; i < count; i++) { 766 if (vars[i + k].dsc_enabled) { 767 initial_slack[i] = 768 kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn; 769 bpp_increased[i] = false; 770 remaining_to_increase += 1; 771 } else { 772 initial_slack[i] = 0; 773 bpp_increased[i] = true; 774 } 775 } 776 777 while (remaining_to_increase) { 778 next_index = -1; 779 min_initial_slack = -1; 780 for (i = 0; i < count; i++) { 781 if (!bpp_increased[i]) { 782 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 783 min_initial_slack = initial_slack[i]; 784 next_index = i; 785 } 786 } 787 } 788 789 if (next_index == -1) 790 break; 791 792 link_timeslots_used = 0; 793 794 for (i = 0; i < count; i++) 795 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); 796 797 fair_pbn_alloc = 798 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; 799 800 if (initial_slack[next_index] > fair_pbn_alloc) { 801 vars[next_index].pbn += fair_pbn_alloc; 802 ret = drm_dp_atomic_find_time_slots(state, 803 params[next_index].port->mgr, 804 params[next_index].port, 805 vars[next_index].pbn); 806 if (ret < 0) 807 return ret; 808 809 ret = drm_dp_mst_atomic_check(state); 810 if (ret == 0) { 811 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 812 } else { 813 vars[next_index].pbn -= fair_pbn_alloc; 814 ret = drm_dp_atomic_find_time_slots(state, 815 params[next_index].port->mgr, 816 params[next_index].port, 817 vars[next_index].pbn); 818 if (ret < 0) 819 return ret; 820 } 821 } else { 822 vars[next_index].pbn += initial_slack[next_index]; 823 ret = drm_dp_atomic_find_time_slots(state, 824 params[next_index].port->mgr, 825 params[next_index].port, 826 vars[next_index].pbn); 827 if (ret < 0) 828 return ret; 829 830 ret = drm_dp_mst_atomic_check(state); 831 if (ret == 0) { 832 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 833 } else { 834 vars[next_index].pbn -= initial_slack[next_index]; 835 ret = drm_dp_atomic_find_time_slots(state, 836 params[next_index].port->mgr, 837 params[next_index].port, 838 vars[next_index].pbn); 839 if (ret < 0) 840 return ret; 841 } 842 } 843 844 bpp_increased[next_index] = true; 845 remaining_to_increase--; 846 } 847 return 0; 848 } 849 850 static int try_disable_dsc(struct drm_atomic_state *state, 851 struct dc_link *dc_link, 852 struct dsc_mst_fairness_params *params, 853 struct dsc_mst_fairness_vars *vars, 854 int count, 855 int k) 856 { 857 int i; 858 bool tried[MAX_PIPES]; 859 int kbps_increase[MAX_PIPES]; 860 int max_kbps_increase; 861 int next_index; 862 int remaining_to_try = 0; 863 int ret; 864 865 for (i = 0; i < count; i++) { 866 if (vars[i + k].dsc_enabled 867 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 868 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 869 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 870 tried[i] = false; 871 remaining_to_try += 1; 872 } else { 873 kbps_increase[i] = 0; 874 tried[i] = true; 875 } 876 } 877 878 while (remaining_to_try) { 879 next_index = -1; 880 max_kbps_increase = -1; 881 for (i = 0; i < count; i++) { 882 if (!tried[i]) { 883 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 884 max_kbps_increase = kbps_increase[i]; 885 next_index = i; 886 } 887 } 888 } 889 890 if (next_index == -1) 891 break; 892 893 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps); 894 ret = drm_dp_atomic_find_time_slots(state, 895 params[next_index].port->mgr, 896 params[next_index].port, 897 vars[next_index].pbn); 898 if (ret < 0) 899 return ret; 900 901 ret = drm_dp_mst_atomic_check(state); 902 if (ret == 0) { 903 vars[next_index].dsc_enabled = false; 904 vars[next_index].bpp_x16 = 0; 905 } else { 906 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps); 907 ret = drm_dp_atomic_find_time_slots(state, 908 params[next_index].port->mgr, 909 params[next_index].port, 910 vars[next_index].pbn); 911 if (ret < 0) 912 return ret; 913 } 914 915 tried[next_index] = true; 916 remaining_to_try--; 917 } 918 return 0; 919 } 920 921 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 922 struct dc_state *dc_state, 923 struct dc_link *dc_link, 924 struct dsc_mst_fairness_vars *vars, 925 struct drm_dp_mst_topology_mgr *mgr, 926 int *link_vars_start_index) 927 { 928 struct dc_stream_state *stream; 929 struct dsc_mst_fairness_params params[MAX_PIPES]; 930 struct amdgpu_dm_connector *aconnector; 931 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 932 int count = 0; 933 int i, k, ret; 934 bool debugfs_overwrite = false; 935 936 memset(params, 0, sizeof(params)); 937 938 if (IS_ERR(mst_state)) 939 return PTR_ERR(mst_state); 940 941 /* Set up params */ 942 for (i = 0; i < dc_state->stream_count; i++) { 943 struct dc_dsc_policy dsc_policy = {0}; 944 945 stream = dc_state->streams[i]; 946 947 if (stream->link != dc_link) 948 continue; 949 950 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 951 if (!aconnector) 952 continue; 953 954 if (!aconnector->mst_output_port) 955 continue; 956 957 stream->timing.flags.DSC = 0; 958 959 params[count].timing = &stream->timing; 960 params[count].sink = stream->sink; 961 params[count].aconnector = aconnector; 962 params[count].port = aconnector->mst_output_port; 963 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 964 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 965 debugfs_overwrite = true; 966 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 967 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 968 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 969 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 970 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 971 if (!dc_dsc_compute_bandwidth_range( 972 stream->sink->ctx->dc->res_pool->dscs[0], 973 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 974 dsc_policy.min_target_bpp * 16, 975 dsc_policy.max_target_bpp * 16, 976 &stream->sink->dsc_caps.dsc_dec_caps, 977 &stream->timing, ¶ms[count].bw_range)) 978 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 979 980 count++; 981 } 982 983 if (count == 0) { 984 ASSERT(0); 985 return 0; 986 } 987 988 /* k is start index of vars for current phy link used by mst hub */ 989 k = *link_vars_start_index; 990 /* set vars start index for next mst hub phy link */ 991 *link_vars_start_index += count; 992 993 /* Try no compression */ 994 for (i = 0; i < count; i++) { 995 vars[i + k].aconnector = params[i].aconnector; 996 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 997 vars[i + k].dsc_enabled = false; 998 vars[i + k].bpp_x16 = 0; 999 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 1000 vars[i + k].pbn); 1001 if (ret < 0) 1002 return ret; 1003 } 1004 ret = drm_dp_mst_atomic_check(state); 1005 if (ret == 0 && !debugfs_overwrite) { 1006 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1007 return 0; 1008 } else if (ret != -ENOSPC) { 1009 return ret; 1010 } 1011 1012 /* Try max compression */ 1013 for (i = 0; i < count; i++) { 1014 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1015 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps); 1016 vars[i + k].dsc_enabled = true; 1017 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1018 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1019 params[i].port, vars[i + k].pbn); 1020 if (ret < 0) 1021 return ret; 1022 } else { 1023 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); 1024 vars[i + k].dsc_enabled = false; 1025 vars[i + k].bpp_x16 = 0; 1026 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1027 params[i].port, vars[i + k].pbn); 1028 if (ret < 0) 1029 return ret; 1030 } 1031 } 1032 ret = drm_dp_mst_atomic_check(state); 1033 if (ret != 0) 1034 return ret; 1035 1036 /* Optimize degree of compression */ 1037 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1038 if (ret < 0) 1039 return ret; 1040 1041 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1042 if (ret < 0) 1043 return ret; 1044 1045 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1046 1047 return 0; 1048 } 1049 1050 static bool is_dsc_need_re_compute( 1051 struct drm_atomic_state *state, 1052 struct dc_state *dc_state, 1053 struct dc_link *dc_link) 1054 { 1055 int i, j; 1056 bool is_dsc_need_re_compute = false; 1057 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1058 int new_stream_on_link_num = 0; 1059 struct amdgpu_dm_connector *aconnector; 1060 struct dc_stream_state *stream; 1061 const struct dc *dc = dc_link->dc; 1062 1063 /* only check phy used by dsc mst branch */ 1064 if (dc_link->type != dc_connection_mst_branch) 1065 return false; 1066 1067 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1068 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1069 return false; 1070 1071 for (i = 0; i < MAX_PIPES; i++) 1072 stream_on_link[i] = NULL; 1073 1074 /* check if there is mode change in new request */ 1075 for (i = 0; i < dc_state->stream_count; i++) { 1076 struct drm_crtc_state *new_crtc_state; 1077 struct drm_connector_state *new_conn_state; 1078 1079 stream = dc_state->streams[i]; 1080 if (!stream) 1081 continue; 1082 1083 /* check if stream using the same link for mst */ 1084 if (stream->link != dc_link) 1085 continue; 1086 1087 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1088 if (!aconnector) 1089 continue; 1090 1091 stream_on_link[new_stream_on_link_num] = aconnector; 1092 new_stream_on_link_num++; 1093 1094 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1095 if (!new_conn_state) 1096 continue; 1097 1098 if (IS_ERR(new_conn_state)) 1099 continue; 1100 1101 if (!new_conn_state->crtc) 1102 continue; 1103 1104 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1105 if (!new_crtc_state) 1106 continue; 1107 1108 if (IS_ERR(new_crtc_state)) 1109 continue; 1110 1111 if (new_crtc_state->enable && new_crtc_state->active) { 1112 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1113 new_crtc_state->connectors_changed) 1114 return true; 1115 } 1116 } 1117 1118 /* check current_state if there stream on link but it is not in 1119 * new request state 1120 */ 1121 for (i = 0; i < dc->current_state->stream_count; i++) { 1122 stream = dc->current_state->streams[i]; 1123 /* only check stream on the mst hub */ 1124 if (stream->link != dc_link) 1125 continue; 1126 1127 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1128 if (!aconnector) 1129 continue; 1130 1131 for (j = 0; j < new_stream_on_link_num; j++) { 1132 if (stream_on_link[j]) { 1133 if (aconnector == stream_on_link[j]) 1134 break; 1135 } 1136 } 1137 1138 if (j == new_stream_on_link_num) { 1139 /* not in new state */ 1140 is_dsc_need_re_compute = true; 1141 break; 1142 } 1143 } 1144 1145 return is_dsc_need_re_compute; 1146 } 1147 1148 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1149 struct dc_state *dc_state, 1150 struct dsc_mst_fairness_vars *vars) 1151 { 1152 int i, j; 1153 struct dc_stream_state *stream; 1154 bool computed_streams[MAX_PIPES]; 1155 struct amdgpu_dm_connector *aconnector; 1156 struct drm_dp_mst_topology_mgr *mst_mgr; 1157 int link_vars_start_index = 0; 1158 int ret = 0; 1159 1160 for (i = 0; i < dc_state->stream_count; i++) 1161 computed_streams[i] = false; 1162 1163 for (i = 0; i < dc_state->stream_count; i++) { 1164 stream = dc_state->streams[i]; 1165 1166 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1167 continue; 1168 1169 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1170 1171 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1172 continue; 1173 1174 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1175 continue; 1176 1177 if (computed_streams[i]) 1178 continue; 1179 1180 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1181 return -EINVAL; 1182 1183 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1184 continue; 1185 1186 mst_mgr = aconnector->mst_output_port->mgr; 1187 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1188 &link_vars_start_index); 1189 if (ret != 0) 1190 return ret; 1191 1192 for (j = 0; j < dc_state->stream_count; j++) { 1193 if (dc_state->streams[j]->link == stream->link) 1194 computed_streams[j] = true; 1195 } 1196 } 1197 1198 for (i = 0; i < dc_state->stream_count; i++) { 1199 stream = dc_state->streams[i]; 1200 1201 if (stream->timing.flags.DSC == 1) 1202 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1203 return -EINVAL; 1204 } 1205 1206 return ret; 1207 } 1208 1209 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1210 struct dc_state *dc_state, 1211 struct dsc_mst_fairness_vars *vars) 1212 { 1213 int i, j; 1214 struct dc_stream_state *stream; 1215 bool computed_streams[MAX_PIPES]; 1216 struct amdgpu_dm_connector *aconnector; 1217 struct drm_dp_mst_topology_mgr *mst_mgr; 1218 int link_vars_start_index = 0; 1219 int ret = 0; 1220 1221 for (i = 0; i < dc_state->stream_count; i++) 1222 computed_streams[i] = false; 1223 1224 for (i = 0; i < dc_state->stream_count; i++) { 1225 stream = dc_state->streams[i]; 1226 1227 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1228 continue; 1229 1230 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1231 1232 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1233 continue; 1234 1235 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1236 continue; 1237 1238 if (computed_streams[i]) 1239 continue; 1240 1241 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1242 continue; 1243 1244 mst_mgr = aconnector->mst_output_port->mgr; 1245 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1246 &link_vars_start_index); 1247 if (ret != 0) 1248 return ret; 1249 1250 for (j = 0; j < dc_state->stream_count; j++) { 1251 if (dc_state->streams[j]->link == stream->link) 1252 computed_streams[j] = true; 1253 } 1254 } 1255 1256 return ret; 1257 } 1258 1259 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1260 struct dc_stream_state *stream) 1261 { 1262 int i; 1263 struct drm_crtc *crtc; 1264 struct drm_crtc_state *new_state, *old_state; 1265 1266 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1267 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1268 1269 if (dm_state->stream == stream) 1270 return i; 1271 } 1272 return -1; 1273 } 1274 1275 static bool is_link_to_dschub(struct dc_link *dc_link) 1276 { 1277 union dpcd_dsc_basic_capabilities *dsc_caps = 1278 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1279 1280 /* only check phy used by dsc mst branch */ 1281 if (dc_link->type != dc_connection_mst_branch) 1282 return false; 1283 1284 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1285 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1286 return false; 1287 return true; 1288 } 1289 1290 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1291 { 1292 int i; 1293 struct drm_crtc *crtc; 1294 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1295 bool ret = false; 1296 1297 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1298 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1299 1300 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1301 ret = false; 1302 break; 1303 } 1304 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1305 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1306 ret = true; 1307 } 1308 return ret; 1309 } 1310 1311 int pre_validate_dsc(struct drm_atomic_state *state, 1312 struct dm_atomic_state **dm_state_ptr, 1313 struct dsc_mst_fairness_vars *vars) 1314 { 1315 int i; 1316 struct dm_atomic_state *dm_state; 1317 struct dc_state *local_dc_state = NULL; 1318 int ret = 0; 1319 1320 if (!is_dsc_precompute_needed(state)) { 1321 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1322 return 0; 1323 } 1324 ret = dm_atomic_get_state(state, dm_state_ptr); 1325 if (ret != 0) { 1326 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1327 return ret; 1328 } 1329 dm_state = *dm_state_ptr; 1330 1331 /* 1332 * create local vailable for dc_state. copy content of streams of dm_state->context 1333 * to local variable. make sure stream pointer of local variable not the same as stream 1334 * from dm_state->context. 1335 */ 1336 1337 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1338 if (!local_dc_state) 1339 return -ENOMEM; 1340 1341 for (i = 0; i < local_dc_state->stream_count; i++) { 1342 struct dc_stream_state *stream = dm_state->context->streams[i]; 1343 int ind = find_crtc_index_in_state_by_stream(state, stream); 1344 1345 if (ind >= 0) { 1346 struct amdgpu_dm_connector *aconnector; 1347 struct drm_connector_state *drm_new_conn_state; 1348 struct dm_connector_state *dm_new_conn_state; 1349 struct dm_crtc_state *dm_old_crtc_state; 1350 1351 aconnector = 1352 amdgpu_dm_find_first_crtc_matching_connector(state, 1353 state->crtcs[ind].ptr); 1354 drm_new_conn_state = 1355 drm_atomic_get_new_connector_state(state, 1356 &aconnector->base); 1357 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1358 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1359 1360 local_dc_state->streams[i] = 1361 create_validate_stream_for_sink(aconnector, 1362 &state->crtcs[ind].new_state->mode, 1363 dm_new_conn_state, 1364 dm_old_crtc_state->stream); 1365 if (local_dc_state->streams[i] == NULL) { 1366 ret = -EINVAL; 1367 break; 1368 } 1369 } 1370 } 1371 1372 if (ret != 0) 1373 goto clean_exit; 1374 1375 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1376 if (ret != 0) { 1377 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1378 goto clean_exit; 1379 } 1380 1381 /* 1382 * compare local_streams -> timing with dm_state->context, 1383 * if the same set crtc_state->mode-change = 0; 1384 */ 1385 for (i = 0; i < local_dc_state->stream_count; i++) { 1386 struct dc_stream_state *stream = dm_state->context->streams[i]; 1387 1388 if (local_dc_state->streams[i] && 1389 is_timing_changed(stream, local_dc_state->streams[i])) { 1390 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1391 } else { 1392 int ind = find_crtc_index_in_state_by_stream(state, stream); 1393 1394 if (ind >= 0) 1395 state->crtcs[ind].new_state->mode_changed = 0; 1396 } 1397 } 1398 clean_exit: 1399 for (i = 0; i < local_dc_state->stream_count; i++) { 1400 struct dc_stream_state *stream = dm_state->context->streams[i]; 1401 1402 if (local_dc_state->streams[i] != stream) 1403 dc_stream_release(local_dc_state->streams[i]); 1404 } 1405 1406 kfree(local_dc_state); 1407 1408 return ret; 1409 } 1410 1411 static unsigned int kbps_from_pbn(unsigned int pbn) 1412 { 1413 unsigned int kbps = pbn; 1414 1415 kbps *= (1000000 / PEAK_FACTOR_X1000); 1416 kbps *= 8; 1417 kbps *= 54; 1418 kbps /= 64; 1419 1420 return kbps; 1421 } 1422 1423 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1424 struct dc_dsc_bw_range *bw_range) 1425 { 1426 struct dc_dsc_policy dsc_policy = {0}; 1427 1428 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); 1429 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1430 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1431 dsc_policy.min_target_bpp * 16, 1432 dsc_policy.max_target_bpp * 16, 1433 &stream->sink->dsc_caps.dsc_dec_caps, 1434 &stream->timing, bw_range); 1435 1436 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1437 } 1438 #endif /* CONFIG_DRM_AMD_DC_DCN */ 1439 1440 enum dc_status dm_dp_mst_is_port_support_mode( 1441 struct amdgpu_dm_connector *aconnector, 1442 struct dc_stream_state *stream) 1443 { 1444 int bpp, pbn, branch_max_throughput_mps = 0; 1445 #if defined(CONFIG_DRM_AMD_DC_DCN) 1446 struct dc_link_settings cur_link_settings; 1447 unsigned int end_to_end_bw_in_kbps = 0; 1448 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1449 unsigned int max_compressed_bw_in_kbps = 0; 1450 struct dc_dsc_bw_range bw_range = {0}; 1451 struct drm_dp_mst_topology_mgr *mst_mgr; 1452 1453 /* 1454 * check if the mode could be supported if DSC pass-through is supported 1455 * AND check if there enough bandwidth available to support the mode 1456 * with DSC enabled. 1457 */ 1458 if (is_dsc_common_config_possible(stream, &bw_range) && 1459 aconnector->mst_output_port->passthrough_aux) { 1460 mst_mgr = aconnector->mst_output_port->mgr; 1461 mutex_lock(&mst_mgr->lock); 1462 1463 cur_link_settings = stream->link->verified_link_cap; 1464 1465 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1466 &cur_link_settings 1467 ); 1468 down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn); 1469 1470 /* pick the bottleneck */ 1471 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, 1472 down_link_bw_in_kbps); 1473 1474 mutex_unlock(&mst_mgr->lock); 1475 1476 /* 1477 * use the maximum dsc compression bandwidth as the required 1478 * bandwidth for the mode 1479 */ 1480 max_compressed_bw_in_kbps = bw_range.min_kbps; 1481 1482 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) { 1483 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n"); 1484 return DC_FAIL_BANDWIDTH_VALIDATE; 1485 } 1486 } else { 1487 #endif 1488 /* check if mode could be supported within full_pbn */ 1489 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1490 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); 1491 1492 if (pbn > aconnector->mst_output_port->full_pbn) 1493 return DC_FAIL_BANDWIDTH_VALIDATE; 1494 #if defined(CONFIG_DRM_AMD_DC_DCN) 1495 } 1496 #endif 1497 1498 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1499 switch (stream->timing.pixel_encoding) { 1500 case PIXEL_ENCODING_RGB: 1501 case PIXEL_ENCODING_YCBCR444: 1502 branch_max_throughput_mps = 1503 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1504 break; 1505 case PIXEL_ENCODING_YCBCR422: 1506 case PIXEL_ENCODING_YCBCR420: 1507 branch_max_throughput_mps = 1508 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1509 break; 1510 default: 1511 break; 1512 } 1513 1514 if (branch_max_throughput_mps != 0 && 1515 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1516 return DC_FAIL_BANDWIDTH_VALIDATE; 1517 1518 return DC_OK; 1519 } 1520