1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 #include "amdgpu_dm_hdcp.h" 35 36 #include "dc.h" 37 #include "dm_helpers.h" 38 39 #include "ddc_service_types.h" 40 #include "dpcd_defs.h" 41 42 #include "dmub_cmd.h" 43 #if defined(CONFIG_DEBUG_FS) 44 #include "amdgpu_dm_debugfs.h" 45 #endif 46 47 #include "dc/dcn20/dcn20_resource.h" 48 bool is_timing_changed(struct dc_stream_state *cur_stream, 49 struct dc_stream_state *new_stream); 50 #define PEAK_FACTOR_X1000 1006 51 52 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 53 struct drm_dp_aux_msg *msg) 54 { 55 ssize_t result = 0; 56 struct aux_payload payload; 57 enum aux_return_code_type operation_result; 58 struct amdgpu_device *adev; 59 struct ddc_service *ddc; 60 61 if (WARN_ON(msg->size > 16)) 62 return -E2BIG; 63 64 payload.address = msg->address; 65 payload.data = msg->buffer; 66 payload.length = msg->size; 67 payload.reply = &msg->reply; 68 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 69 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 70 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 71 payload.write_status_update = 72 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 73 payload.defer_delay = 0; 74 75 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 76 &operation_result); 77 78 /* 79 * w/a on certain intel platform where hpd is unexpected to pull low during 80 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 81 * aux transaction is succuess in such case, therefore bypass the error 82 */ 83 ddc = TO_DM_AUX(aux)->ddc_service; 84 adev = ddc->ctx->driver_context; 85 if (adev->dm.aux_hpd_discon_quirk) { 86 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 87 operation_result == AUX_RET_ERROR_HPD_DISCON) { 88 result = 0; 89 operation_result = AUX_RET_SUCCESS; 90 } 91 } 92 93 if (payload.write && result >= 0) 94 result = msg->size; 95 96 if (result < 0) 97 switch (operation_result) { 98 case AUX_RET_SUCCESS: 99 break; 100 case AUX_RET_ERROR_HPD_DISCON: 101 case AUX_RET_ERROR_UNKNOWN: 102 case AUX_RET_ERROR_INVALID_OPERATION: 103 case AUX_RET_ERROR_PROTOCOL_ERROR: 104 result = -EIO; 105 break; 106 case AUX_RET_ERROR_INVALID_REPLY: 107 case AUX_RET_ERROR_ENGINE_ACQUIRE: 108 result = -EBUSY; 109 break; 110 case AUX_RET_ERROR_TIMEOUT: 111 result = -ETIMEDOUT; 112 break; 113 } 114 115 return result; 116 } 117 118 static void 119 dm_dp_mst_connector_destroy(struct drm_connector *connector) 120 { 121 struct amdgpu_dm_connector *aconnector = 122 to_amdgpu_dm_connector(connector); 123 124 if (aconnector->dc_sink) { 125 dc_link_remove_remote_sink(aconnector->dc_link, 126 aconnector->dc_sink); 127 dc_sink_release(aconnector->dc_sink); 128 } 129 130 kfree(aconnector->edid); 131 132 drm_connector_cleanup(connector); 133 drm_dp_mst_put_port_malloc(aconnector->mst_output_port); 134 kfree(aconnector); 135 } 136 137 static int 138 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 139 { 140 struct amdgpu_dm_connector *amdgpu_dm_connector = 141 to_amdgpu_dm_connector(connector); 142 int r; 143 144 r = drm_dp_mst_connector_late_register(connector, 145 amdgpu_dm_connector->mst_output_port); 146 if (r < 0) 147 return r; 148 149 #if defined(CONFIG_DEBUG_FS) 150 connector_debugfs_init(amdgpu_dm_connector); 151 #endif 152 153 return 0; 154 } 155 156 static void 157 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 158 { 159 struct amdgpu_dm_connector *aconnector = 160 to_amdgpu_dm_connector(connector); 161 struct drm_dp_mst_port *port = aconnector->mst_output_port; 162 struct amdgpu_dm_connector *root = aconnector->mst_root; 163 struct dc_link *dc_link = aconnector->dc_link; 164 struct dc_sink *dc_sink = aconnector->dc_sink; 165 166 drm_dp_mst_connector_early_unregister(connector, port); 167 168 /* 169 * Release dc_sink for connector which its attached port is 170 * no longer in the mst topology 171 */ 172 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 173 if (dc_sink) { 174 if (dc_link->sink_count) 175 dc_link_remove_remote_sink(dc_link, dc_sink); 176 177 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 178 dc_sink, dc_link->sink_count); 179 180 dc_sink_release(dc_sink); 181 aconnector->dc_sink = NULL; 182 aconnector->edid = NULL; 183 } 184 185 aconnector->mst_status = MST_STATUS_DEFAULT; 186 drm_modeset_unlock(&root->mst_mgr.base.lock); 187 } 188 189 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 190 .fill_modes = drm_helper_probe_single_connector_modes, 191 .destroy = dm_dp_mst_connector_destroy, 192 .reset = amdgpu_dm_connector_funcs_reset, 193 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 194 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 195 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 196 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 197 .late_register = amdgpu_dm_mst_connector_late_register, 198 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 199 }; 200 201 bool needs_dsc_aux_workaround(struct dc_link *link) 202 { 203 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 204 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 205 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 206 return true; 207 208 return false; 209 } 210 211 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port) 212 { 213 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F 214 215 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) { 216 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 217 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) { 218 DRM_INFO("Synaptics Cascaded MST hub\n"); 219 return true; 220 } 221 } 222 223 return false; 224 } 225 226 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 227 { 228 struct dc_sink *dc_sink = aconnector->dc_sink; 229 struct drm_dp_mst_port *port = aconnector->mst_output_port; 230 u8 dsc_caps[16] = { 0 }; 231 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 232 u8 *dsc_branch_dec_caps = NULL; 233 234 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 235 236 /* 237 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 238 * because it only check the dsc/fec caps of the "port variable" and not the dock 239 * 240 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 241 * 242 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 243 * 244 */ 245 if (!aconnector->dsc_aux && !port->parent->port_parent && 246 needs_dsc_aux_workaround(aconnector->dc_link)) 247 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; 248 249 /* synaptics cascaded MST hub case */ 250 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port)) 251 aconnector->dsc_aux = port->mgr->aux; 252 253 if (!aconnector->dsc_aux) 254 return false; 255 256 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 257 return false; 258 259 if (drm_dp_dpcd_read(aconnector->dsc_aux, 260 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 261 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 262 263 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 264 dsc_caps, dsc_branch_dec_caps, 265 &dc_sink->dsc_caps.dsc_dec_caps)) 266 return false; 267 268 return true; 269 } 270 271 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 272 { 273 union dp_downstream_port_present ds_port_present; 274 275 if (!aconnector->dsc_aux) 276 return false; 277 278 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 279 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 280 return false; 281 } 282 283 aconnector->mst_downstream_port_present = ds_port_present; 284 DRM_INFO("Downstream port present %d, type %d\n", 285 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 286 287 return true; 288 } 289 290 static int dm_dp_mst_get_modes(struct drm_connector *connector) 291 { 292 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 293 int ret = 0; 294 295 if (!aconnector) 296 return drm_add_edid_modes(connector, NULL); 297 298 if (!aconnector->edid) { 299 struct edid *edid; 300 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); 301 302 if (!edid) { 303 amdgpu_dm_set_mst_status(&aconnector->mst_status, 304 MST_REMOTE_EDID, false); 305 306 drm_connector_update_edid_property( 307 &aconnector->base, 308 NULL); 309 310 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 311 if (!aconnector->dc_sink) { 312 struct dc_sink *dc_sink; 313 struct dc_sink_init_data init_params = { 314 .link = aconnector->dc_link, 315 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 316 317 dc_sink = dc_link_add_remote_sink( 318 aconnector->dc_link, 319 NULL, 320 0, 321 &init_params); 322 323 if (!dc_sink) { 324 DRM_ERROR("Unable to add a remote sink\n"); 325 return 0; 326 } 327 328 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 329 dc_sink, aconnector->dc_link->sink_count); 330 331 dc_sink->priv = aconnector; 332 aconnector->dc_sink = dc_sink; 333 } 334 335 return ret; 336 } 337 338 aconnector->edid = edid; 339 amdgpu_dm_set_mst_status(&aconnector->mst_status, 340 MST_REMOTE_EDID, true); 341 } 342 343 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 344 dc_sink_release(aconnector->dc_sink); 345 aconnector->dc_sink = NULL; 346 } 347 348 if (!aconnector->dc_sink) { 349 struct dc_sink *dc_sink; 350 struct dc_sink_init_data init_params = { 351 .link = aconnector->dc_link, 352 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 353 dc_sink = dc_link_add_remote_sink( 354 aconnector->dc_link, 355 (uint8_t *)aconnector->edid, 356 (aconnector->edid->extensions + 1) * EDID_LENGTH, 357 &init_params); 358 359 if (!dc_sink) { 360 DRM_ERROR("Unable to add a remote sink\n"); 361 return 0; 362 } 363 364 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 365 dc_sink, aconnector->dc_link->sink_count); 366 367 dc_sink->priv = aconnector; 368 /* dc_link_add_remote_sink returns a new reference */ 369 aconnector->dc_sink = dc_sink; 370 371 /* when display is unplugged from mst hub, connctor will be 372 * destroyed within dm_dp_mst_connector_destroy. connector 373 * hdcp perperties, like type, undesired, desired, enabled, 374 * will be lost. So, save hdcp properties into hdcp_work within 375 * amdgpu_dm_atomic_commit_tail. if the same display is 376 * plugged back with same display index, its hdcp properties 377 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 378 */ 379 if (aconnector->dc_sink && connector->state) { 380 struct drm_device *dev = connector->dev; 381 struct amdgpu_device *adev = drm_to_adev(dev); 382 383 if (adev->dm.hdcp_workqueue) { 384 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 385 struct hdcp_workqueue *hdcp_w = 386 &hdcp_work[aconnector->dc_link->link_index]; 387 388 connector->state->hdcp_content_type = 389 hdcp_w->hdcp_content_type[connector->index]; 390 connector->state->content_protection = 391 hdcp_w->content_protection[connector->index]; 392 } 393 } 394 395 if (aconnector->dc_sink) { 396 amdgpu_dm_update_freesync_caps( 397 connector, aconnector->edid); 398 399 if (!validate_dsc_caps_on_connector(aconnector)) 400 memset(&aconnector->dc_sink->dsc_caps, 401 0, sizeof(aconnector->dc_sink->dsc_caps)); 402 403 if (!retrieve_downstream_port_device(aconnector)) 404 memset(&aconnector->mst_downstream_port_present, 405 0, sizeof(aconnector->mst_downstream_port_present)); 406 } 407 } 408 409 drm_connector_update_edid_property( 410 &aconnector->base, aconnector->edid); 411 412 ret = drm_add_edid_modes(connector, aconnector->edid); 413 414 return ret; 415 } 416 417 static struct drm_encoder * 418 dm_mst_atomic_best_encoder(struct drm_connector *connector, 419 struct drm_atomic_state *state) 420 { 421 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 422 connector); 423 struct drm_device *dev = connector->dev; 424 struct amdgpu_device *adev = drm_to_adev(dev); 425 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 426 427 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 428 } 429 430 static int 431 dm_dp_mst_detect(struct drm_connector *connector, 432 struct drm_modeset_acquire_ctx *ctx, bool force) 433 { 434 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 435 struct amdgpu_dm_connector *master = aconnector->mst_root; 436 struct drm_dp_mst_port *port = aconnector->mst_output_port; 437 int connection_status; 438 439 if (drm_connector_is_unregistered(connector)) 440 return connector_status_disconnected; 441 442 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 443 aconnector->mst_output_port); 444 445 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 446 uint8_t dpcd_rev; 447 int ret; 448 449 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 450 451 if (ret == 1) { 452 port->dpcd_rev = dpcd_rev; 453 454 /* Could be DP1.2 DP Rx case*/ 455 if (!dpcd_rev) { 456 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 457 458 if (ret == 1) 459 port->dpcd_rev = dpcd_rev; 460 } 461 462 if (!dpcd_rev) 463 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 464 } 465 466 /* 467 * Could be legacy sink, logical port etc on DP1.2. 468 * Will get Nack under these cases when issue remote 469 * DPCD read. 470 */ 471 if (ret != 1) 472 DRM_DEBUG_KMS("Can't access DPCD"); 473 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 474 port->dpcd_rev = 0; 475 } 476 477 /* 478 * Release dc_sink for connector which unplug event is notified by CSN msg 479 */ 480 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 481 if (aconnector->dc_link->sink_count) 482 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 483 484 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 485 aconnector->dc_link, aconnector->dc_link->sink_count); 486 487 dc_sink_release(aconnector->dc_sink); 488 aconnector->dc_sink = NULL; 489 aconnector->edid = NULL; 490 491 amdgpu_dm_set_mst_status(&aconnector->mst_status, 492 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 493 false); 494 } 495 496 return connection_status; 497 } 498 499 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 500 struct drm_atomic_state *state) 501 { 502 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 503 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; 504 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; 505 506 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 507 } 508 509 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 510 .get_modes = dm_dp_mst_get_modes, 511 .mode_valid = amdgpu_dm_connector_mode_valid, 512 .atomic_best_encoder = dm_mst_atomic_best_encoder, 513 .detect_ctx = dm_dp_mst_detect, 514 .atomic_check = dm_dp_mst_atomic_check, 515 }; 516 517 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 518 { 519 drm_encoder_cleanup(encoder); 520 } 521 522 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 523 .destroy = amdgpu_dm_encoder_destroy, 524 }; 525 526 void 527 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 528 { 529 struct drm_device *dev = adev_to_drm(adev); 530 int i; 531 532 for (i = 0; i < adev->dm.display_indexes_num; i++) { 533 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 534 struct drm_encoder *encoder = &amdgpu_encoder->base; 535 536 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 537 538 drm_encoder_init( 539 dev, 540 &amdgpu_encoder->base, 541 &amdgpu_dm_encoder_funcs, 542 DRM_MODE_ENCODER_DPMST, 543 NULL); 544 545 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 546 } 547 } 548 549 static struct drm_connector * 550 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 551 struct drm_dp_mst_port *port, 552 const char *pathprop) 553 { 554 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 555 struct drm_device *dev = master->base.dev; 556 struct amdgpu_device *adev = drm_to_adev(dev); 557 struct amdgpu_dm_connector *aconnector; 558 struct drm_connector *connector; 559 int i; 560 561 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 562 if (!aconnector) 563 return NULL; 564 565 connector = &aconnector->base; 566 aconnector->mst_output_port = port; 567 aconnector->mst_root = master; 568 amdgpu_dm_set_mst_status(&aconnector->mst_status, 569 MST_PROBE, true); 570 571 if (drm_connector_init( 572 dev, 573 connector, 574 &dm_dp_mst_connector_funcs, 575 DRM_MODE_CONNECTOR_DisplayPort)) { 576 kfree(aconnector); 577 return NULL; 578 } 579 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 580 581 amdgpu_dm_connector_init_helper( 582 &adev->dm, 583 aconnector, 584 DRM_MODE_CONNECTOR_DisplayPort, 585 master->dc_link, 586 master->connector_id); 587 588 for (i = 0; i < adev->dm.display_indexes_num; i++) { 589 drm_connector_attach_encoder(&aconnector->base, 590 &adev->dm.mst_encoders[i].base); 591 } 592 593 connector->max_bpc_property = master->base.max_bpc_property; 594 if (connector->max_bpc_property) 595 drm_connector_attach_max_bpc_property(connector, 8, 16); 596 597 connector->vrr_capable_property = master->base.vrr_capable_property; 598 if (connector->vrr_capable_property) 599 drm_connector_attach_vrr_capable_property(connector); 600 601 drm_object_attach_property( 602 &connector->base, 603 dev->mode_config.path_property, 604 0); 605 drm_object_attach_property( 606 &connector->base, 607 dev->mode_config.tile_property, 608 0); 609 610 drm_connector_set_path_property(connector, pathprop); 611 612 /* 613 * Initialize connector state before adding the connectror to drm and 614 * framebuffer lists 615 */ 616 amdgpu_dm_connector_funcs_reset(connector); 617 618 drm_dp_mst_get_port_malloc(port); 619 620 return connector; 621 } 622 623 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 624 .add_connector = dm_dp_add_mst_connector, 625 }; 626 627 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 628 struct amdgpu_dm_connector *aconnector, 629 int link_index) 630 { 631 struct dc_link_settings max_link_enc_cap = {0}; 632 633 aconnector->dm_dp_aux.aux.name = 634 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 635 link_index); 636 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 637 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 638 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 639 640 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 641 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 642 &aconnector->base); 643 644 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 645 return; 646 647 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 648 aconnector->mst_mgr.cbs = &dm_mst_cbs; 649 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 650 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 651 652 drm_connector_attach_dp_subconnector_property(&aconnector->base); 653 } 654 655 int dm_mst_get_pbn_divider(struct dc_link *link) 656 { 657 if (!link) 658 return 0; 659 660 return dc_link_bandwidth_kbps(link, 661 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 662 } 663 664 struct dsc_mst_fairness_params { 665 struct dc_crtc_timing *timing; 666 struct dc_sink *sink; 667 struct dc_dsc_bw_range bw_range; 668 bool compression_possible; 669 struct drm_dp_mst_port *port; 670 enum dsc_clock_force_state clock_force_enable; 671 uint32_t num_slices_h; 672 uint32_t num_slices_v; 673 uint32_t bpp_overwrite; 674 struct amdgpu_dm_connector *aconnector; 675 }; 676 677 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) 678 { 679 u8 link_coding_cap; 680 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B; 681 682 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link); 683 if (link_coding_cap == DP_128b_132b_ENCODING) 684 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B; 685 686 return fec_overhead_multiplier_x1000; 687 } 688 689 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) 690 { 691 u64 peak_kbps = kbps; 692 693 peak_kbps *= 1006; 694 peak_kbps *= fec_overhead_multiplier_x1000; 695 peak_kbps = div_u64(peak_kbps, 1000 * 1000); 696 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 697 } 698 699 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 700 struct dsc_mst_fairness_vars *vars, 701 int count, 702 int k) 703 { 704 struct drm_connector *drm_connector; 705 int i; 706 struct dc_dsc_config_options dsc_options = {0}; 707 708 for (i = 0; i < count; i++) { 709 drm_connector = ¶ms[i].aconnector->base; 710 711 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); 712 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 713 714 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 715 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 716 params[i].sink->ctx->dc->res_pool->dscs[0], 717 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 718 &dsc_options, 719 0, 720 params[i].timing, 721 ¶ms[i].timing->dsc_cfg)) { 722 params[i].timing->flags.DSC = 1; 723 724 if (params[i].bpp_overwrite) 725 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 726 else 727 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 728 729 if (params[i].num_slices_h) 730 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 731 732 if (params[i].num_slices_v) 733 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 734 } else { 735 params[i].timing->flags.DSC = 0; 736 } 737 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 738 } 739 740 for (i = 0; i < count; i++) { 741 if (params[i].sink) { 742 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 743 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 744 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 745 params[i].sink->edid_caps.display_name); 746 } 747 748 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 749 params[i].timing->flags.DSC, 750 params[i].timing->dsc_cfg.bits_per_pixel, 751 vars[i + k].pbn); 752 } 753 } 754 755 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 756 { 757 struct dc_dsc_config dsc_config; 758 u64 kbps; 759 760 struct drm_connector *drm_connector = ¶m.aconnector->base; 761 struct dc_dsc_config_options dsc_options = {0}; 762 763 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); 764 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 765 766 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 767 dc_dsc_compute_config( 768 param.sink->ctx->dc->res_pool->dscs[0], 769 ¶m.sink->dsc_caps.dsc_dec_caps, 770 &dsc_options, 771 (int) kbps, param.timing, &dsc_config); 772 773 return dsc_config.bits_per_pixel; 774 } 775 776 static int increase_dsc_bpp(struct drm_atomic_state *state, 777 struct drm_dp_mst_topology_state *mst_state, 778 struct dc_link *dc_link, 779 struct dsc_mst_fairness_params *params, 780 struct dsc_mst_fairness_vars *vars, 781 int count, 782 int k) 783 { 784 int i; 785 bool bpp_increased[MAX_PIPES]; 786 int initial_slack[MAX_PIPES]; 787 int min_initial_slack; 788 int next_index; 789 int remaining_to_increase = 0; 790 int link_timeslots_used; 791 int fair_pbn_alloc; 792 int ret = 0; 793 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 794 795 for (i = 0; i < count; i++) { 796 if (vars[i + k].dsc_enabled) { 797 initial_slack[i] = 798 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn; 799 bpp_increased[i] = false; 800 remaining_to_increase += 1; 801 } else { 802 initial_slack[i] = 0; 803 bpp_increased[i] = true; 804 } 805 } 806 807 while (remaining_to_increase) { 808 next_index = -1; 809 min_initial_slack = -1; 810 for (i = 0; i < count; i++) { 811 if (!bpp_increased[i]) { 812 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 813 min_initial_slack = initial_slack[i]; 814 next_index = i; 815 } 816 } 817 } 818 819 if (next_index == -1) 820 break; 821 822 link_timeslots_used = 0; 823 824 for (i = 0; i < count; i++) 825 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); 826 827 fair_pbn_alloc = 828 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; 829 830 if (initial_slack[next_index] > fair_pbn_alloc) { 831 vars[next_index].pbn += fair_pbn_alloc; 832 ret = drm_dp_atomic_find_time_slots(state, 833 params[next_index].port->mgr, 834 params[next_index].port, 835 vars[next_index].pbn); 836 if (ret < 0) 837 return ret; 838 839 ret = drm_dp_mst_atomic_check(state); 840 if (ret == 0) { 841 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 842 } else { 843 vars[next_index].pbn -= fair_pbn_alloc; 844 ret = drm_dp_atomic_find_time_slots(state, 845 params[next_index].port->mgr, 846 params[next_index].port, 847 vars[next_index].pbn); 848 if (ret < 0) 849 return ret; 850 } 851 } else { 852 vars[next_index].pbn += initial_slack[next_index]; 853 ret = drm_dp_atomic_find_time_slots(state, 854 params[next_index].port->mgr, 855 params[next_index].port, 856 vars[next_index].pbn); 857 if (ret < 0) 858 return ret; 859 860 ret = drm_dp_mst_atomic_check(state); 861 if (ret == 0) { 862 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 863 } else { 864 vars[next_index].pbn -= initial_slack[next_index]; 865 ret = drm_dp_atomic_find_time_slots(state, 866 params[next_index].port->mgr, 867 params[next_index].port, 868 vars[next_index].pbn); 869 if (ret < 0) 870 return ret; 871 } 872 } 873 874 bpp_increased[next_index] = true; 875 remaining_to_increase--; 876 } 877 return 0; 878 } 879 880 static int try_disable_dsc(struct drm_atomic_state *state, 881 struct dc_link *dc_link, 882 struct dsc_mst_fairness_params *params, 883 struct dsc_mst_fairness_vars *vars, 884 int count, 885 int k) 886 { 887 int i; 888 bool tried[MAX_PIPES]; 889 int kbps_increase[MAX_PIPES]; 890 int max_kbps_increase; 891 int next_index; 892 int remaining_to_try = 0; 893 int ret; 894 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 895 896 for (i = 0; i < count; i++) { 897 if (vars[i + k].dsc_enabled 898 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 899 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 900 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 901 tried[i] = false; 902 remaining_to_try += 1; 903 } else { 904 kbps_increase[i] = 0; 905 tried[i] = true; 906 } 907 } 908 909 while (remaining_to_try) { 910 next_index = -1; 911 max_kbps_increase = -1; 912 for (i = 0; i < count; i++) { 913 if (!tried[i]) { 914 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 915 max_kbps_increase = kbps_increase[i]; 916 next_index = i; 917 } 918 } 919 } 920 921 if (next_index == -1) 922 break; 923 924 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 925 ret = drm_dp_atomic_find_time_slots(state, 926 params[next_index].port->mgr, 927 params[next_index].port, 928 vars[next_index].pbn); 929 if (ret < 0) 930 return ret; 931 932 ret = drm_dp_mst_atomic_check(state); 933 if (ret == 0) { 934 vars[next_index].dsc_enabled = false; 935 vars[next_index].bpp_x16 = 0; 936 } else { 937 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); 938 ret = drm_dp_atomic_find_time_slots(state, 939 params[next_index].port->mgr, 940 params[next_index].port, 941 vars[next_index].pbn); 942 if (ret < 0) 943 return ret; 944 } 945 946 tried[next_index] = true; 947 remaining_to_try--; 948 } 949 return 0; 950 } 951 952 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 953 struct dc_state *dc_state, 954 struct dc_link *dc_link, 955 struct dsc_mst_fairness_vars *vars, 956 struct drm_dp_mst_topology_mgr *mgr, 957 int *link_vars_start_index) 958 { 959 struct dc_stream_state *stream; 960 struct dsc_mst_fairness_params params[MAX_PIPES]; 961 struct amdgpu_dm_connector *aconnector; 962 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 963 int count = 0; 964 int i, k, ret; 965 bool debugfs_overwrite = false; 966 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 967 968 memset(params, 0, sizeof(params)); 969 970 if (IS_ERR(mst_state)) 971 return PTR_ERR(mst_state); 972 973 /* Set up params */ 974 for (i = 0; i < dc_state->stream_count; i++) { 975 struct dc_dsc_policy dsc_policy = {0}; 976 977 stream = dc_state->streams[i]; 978 979 if (stream->link != dc_link) 980 continue; 981 982 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 983 if (!aconnector) 984 continue; 985 986 if (!aconnector->mst_output_port) 987 continue; 988 989 stream->timing.flags.DSC = 0; 990 991 params[count].timing = &stream->timing; 992 params[count].sink = stream->sink; 993 params[count].aconnector = aconnector; 994 params[count].port = aconnector->mst_output_port; 995 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 996 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 997 debugfs_overwrite = true; 998 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 999 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1000 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 1001 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 1002 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 1003 if (!dc_dsc_compute_bandwidth_range( 1004 stream->sink->ctx->dc->res_pool->dscs[0], 1005 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1006 dsc_policy.min_target_bpp * 16, 1007 dsc_policy.max_target_bpp * 16, 1008 &stream->sink->dsc_caps.dsc_dec_caps, 1009 &stream->timing, ¶ms[count].bw_range)) 1010 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); 1011 1012 count++; 1013 } 1014 1015 if (count == 0) { 1016 ASSERT(0); 1017 return 0; 1018 } 1019 1020 /* k is start index of vars for current phy link used by mst hub */ 1021 k = *link_vars_start_index; 1022 /* set vars start index for next mst hub phy link */ 1023 *link_vars_start_index += count; 1024 1025 /* Try no compression */ 1026 for (i = 0; i < count; i++) { 1027 vars[i + k].aconnector = params[i].aconnector; 1028 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1029 vars[i + k].dsc_enabled = false; 1030 vars[i + k].bpp_x16 = 0; 1031 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 1032 vars[i + k].pbn); 1033 if (ret < 0) 1034 return ret; 1035 } 1036 ret = drm_dp_mst_atomic_check(state); 1037 if (ret == 0 && !debugfs_overwrite) { 1038 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1039 return 0; 1040 } else if (ret != -ENOSPC) { 1041 return ret; 1042 } 1043 1044 /* Try max compression */ 1045 for (i = 0; i < count; i++) { 1046 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1047 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); 1048 vars[i + k].dsc_enabled = true; 1049 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1050 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1051 params[i].port, vars[i + k].pbn); 1052 if (ret < 0) 1053 return ret; 1054 } else { 1055 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1056 vars[i + k].dsc_enabled = false; 1057 vars[i + k].bpp_x16 = 0; 1058 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1059 params[i].port, vars[i + k].pbn); 1060 if (ret < 0) 1061 return ret; 1062 } 1063 } 1064 ret = drm_dp_mst_atomic_check(state); 1065 if (ret != 0) 1066 return ret; 1067 1068 /* Optimize degree of compression */ 1069 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1070 if (ret < 0) 1071 return ret; 1072 1073 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1074 if (ret < 0) 1075 return ret; 1076 1077 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1078 1079 return 0; 1080 } 1081 1082 static bool is_dsc_need_re_compute( 1083 struct drm_atomic_state *state, 1084 struct dc_state *dc_state, 1085 struct dc_link *dc_link) 1086 { 1087 int i, j; 1088 bool is_dsc_need_re_compute = false; 1089 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1090 int new_stream_on_link_num = 0; 1091 struct amdgpu_dm_connector *aconnector; 1092 struct dc_stream_state *stream; 1093 const struct dc *dc = dc_link->dc; 1094 1095 /* only check phy used by dsc mst branch */ 1096 if (dc_link->type != dc_connection_mst_branch) 1097 return false; 1098 1099 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1100 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1101 return false; 1102 1103 for (i = 0; i < MAX_PIPES; i++) 1104 stream_on_link[i] = NULL; 1105 1106 /* check if there is mode change in new request */ 1107 for (i = 0; i < dc_state->stream_count; i++) { 1108 struct drm_crtc_state *new_crtc_state; 1109 struct drm_connector_state *new_conn_state; 1110 1111 stream = dc_state->streams[i]; 1112 if (!stream) 1113 continue; 1114 1115 /* check if stream using the same link for mst */ 1116 if (stream->link != dc_link) 1117 continue; 1118 1119 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1120 if (!aconnector) 1121 continue; 1122 1123 stream_on_link[new_stream_on_link_num] = aconnector; 1124 new_stream_on_link_num++; 1125 1126 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1127 if (!new_conn_state) 1128 continue; 1129 1130 if (IS_ERR(new_conn_state)) 1131 continue; 1132 1133 if (!new_conn_state->crtc) 1134 continue; 1135 1136 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1137 if (!new_crtc_state) 1138 continue; 1139 1140 if (IS_ERR(new_crtc_state)) 1141 continue; 1142 1143 if (new_crtc_state->enable && new_crtc_state->active) { 1144 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1145 new_crtc_state->connectors_changed) 1146 return true; 1147 } 1148 } 1149 1150 /* check current_state if there stream on link but it is not in 1151 * new request state 1152 */ 1153 for (i = 0; i < dc->current_state->stream_count; i++) { 1154 stream = dc->current_state->streams[i]; 1155 /* only check stream on the mst hub */ 1156 if (stream->link != dc_link) 1157 continue; 1158 1159 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1160 if (!aconnector) 1161 continue; 1162 1163 for (j = 0; j < new_stream_on_link_num; j++) { 1164 if (stream_on_link[j]) { 1165 if (aconnector == stream_on_link[j]) 1166 break; 1167 } 1168 } 1169 1170 if (j == new_stream_on_link_num) { 1171 /* not in new state */ 1172 is_dsc_need_re_compute = true; 1173 break; 1174 } 1175 } 1176 1177 return is_dsc_need_re_compute; 1178 } 1179 1180 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1181 struct dc_state *dc_state, 1182 struct dsc_mst_fairness_vars *vars) 1183 { 1184 int i, j; 1185 struct dc_stream_state *stream; 1186 bool computed_streams[MAX_PIPES]; 1187 struct amdgpu_dm_connector *aconnector; 1188 struct drm_dp_mst_topology_mgr *mst_mgr; 1189 struct resource_pool *res_pool; 1190 int link_vars_start_index = 0; 1191 int ret = 0; 1192 1193 for (i = 0; i < dc_state->stream_count; i++) 1194 computed_streams[i] = false; 1195 1196 for (i = 0; i < dc_state->stream_count; i++) { 1197 stream = dc_state->streams[i]; 1198 res_pool = stream->ctx->dc->res_pool; 1199 1200 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1201 continue; 1202 1203 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1204 1205 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1206 continue; 1207 1208 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1209 continue; 1210 1211 if (computed_streams[i]) 1212 continue; 1213 1214 if (!res_pool->funcs->remove_stream_from_ctx || 1215 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1216 return -EINVAL; 1217 1218 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1219 continue; 1220 1221 mst_mgr = aconnector->mst_output_port->mgr; 1222 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1223 &link_vars_start_index); 1224 if (ret != 0) 1225 return ret; 1226 1227 for (j = 0; j < dc_state->stream_count; j++) { 1228 if (dc_state->streams[j]->link == stream->link) 1229 computed_streams[j] = true; 1230 } 1231 } 1232 1233 for (i = 0; i < dc_state->stream_count; i++) { 1234 stream = dc_state->streams[i]; 1235 1236 if (stream->timing.flags.DSC == 1) 1237 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1238 return -EINVAL; 1239 } 1240 1241 return ret; 1242 } 1243 1244 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1245 struct dc_state *dc_state, 1246 struct dsc_mst_fairness_vars *vars) 1247 { 1248 int i, j; 1249 struct dc_stream_state *stream; 1250 bool computed_streams[MAX_PIPES]; 1251 struct amdgpu_dm_connector *aconnector; 1252 struct drm_dp_mst_topology_mgr *mst_mgr; 1253 int link_vars_start_index = 0; 1254 int ret = 0; 1255 1256 for (i = 0; i < dc_state->stream_count; i++) 1257 computed_streams[i] = false; 1258 1259 for (i = 0; i < dc_state->stream_count; i++) { 1260 stream = dc_state->streams[i]; 1261 1262 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1263 continue; 1264 1265 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1266 1267 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1268 continue; 1269 1270 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1271 continue; 1272 1273 if (computed_streams[i]) 1274 continue; 1275 1276 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1277 continue; 1278 1279 mst_mgr = aconnector->mst_output_port->mgr; 1280 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1281 &link_vars_start_index); 1282 if (ret != 0) 1283 return ret; 1284 1285 for (j = 0; j < dc_state->stream_count; j++) { 1286 if (dc_state->streams[j]->link == stream->link) 1287 computed_streams[j] = true; 1288 } 1289 } 1290 1291 return ret; 1292 } 1293 1294 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1295 struct dc_stream_state *stream) 1296 { 1297 int i; 1298 struct drm_crtc *crtc; 1299 struct drm_crtc_state *new_state, *old_state; 1300 1301 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1302 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1303 1304 if (dm_state->stream == stream) 1305 return i; 1306 } 1307 return -1; 1308 } 1309 1310 static bool is_link_to_dschub(struct dc_link *dc_link) 1311 { 1312 union dpcd_dsc_basic_capabilities *dsc_caps = 1313 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1314 1315 /* only check phy used by dsc mst branch */ 1316 if (dc_link->type != dc_connection_mst_branch) 1317 return false; 1318 1319 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1320 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1321 return false; 1322 return true; 1323 } 1324 1325 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1326 { 1327 int i; 1328 struct drm_crtc *crtc; 1329 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1330 bool ret = false; 1331 1332 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1333 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1334 1335 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1336 ret = false; 1337 break; 1338 } 1339 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1340 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1341 ret = true; 1342 } 1343 return ret; 1344 } 1345 1346 int pre_validate_dsc(struct drm_atomic_state *state, 1347 struct dm_atomic_state **dm_state_ptr, 1348 struct dsc_mst_fairness_vars *vars) 1349 { 1350 int i; 1351 struct dm_atomic_state *dm_state; 1352 struct dc_state *local_dc_state = NULL; 1353 int ret = 0; 1354 1355 if (!is_dsc_precompute_needed(state)) { 1356 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1357 return 0; 1358 } 1359 ret = dm_atomic_get_state(state, dm_state_ptr); 1360 if (ret != 0) { 1361 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1362 return ret; 1363 } 1364 dm_state = *dm_state_ptr; 1365 1366 /* 1367 * create local vailable for dc_state. copy content of streams of dm_state->context 1368 * to local variable. make sure stream pointer of local variable not the same as stream 1369 * from dm_state->context. 1370 */ 1371 1372 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1373 if (!local_dc_state) 1374 return -ENOMEM; 1375 1376 for (i = 0; i < local_dc_state->stream_count; i++) { 1377 struct dc_stream_state *stream = dm_state->context->streams[i]; 1378 int ind = find_crtc_index_in_state_by_stream(state, stream); 1379 1380 if (ind >= 0) { 1381 struct amdgpu_dm_connector *aconnector; 1382 struct drm_connector_state *drm_new_conn_state; 1383 struct dm_connector_state *dm_new_conn_state; 1384 struct dm_crtc_state *dm_old_crtc_state; 1385 1386 aconnector = 1387 amdgpu_dm_find_first_crtc_matching_connector(state, 1388 state->crtcs[ind].ptr); 1389 drm_new_conn_state = 1390 drm_atomic_get_new_connector_state(state, 1391 &aconnector->base); 1392 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1393 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1394 1395 local_dc_state->streams[i] = 1396 create_validate_stream_for_sink(aconnector, 1397 &state->crtcs[ind].new_state->mode, 1398 dm_new_conn_state, 1399 dm_old_crtc_state->stream); 1400 if (local_dc_state->streams[i] == NULL) { 1401 ret = -EINVAL; 1402 break; 1403 } 1404 } 1405 } 1406 1407 if (ret != 0) 1408 goto clean_exit; 1409 1410 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1411 if (ret != 0) { 1412 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1413 ret = -EINVAL; 1414 goto clean_exit; 1415 } 1416 1417 /* 1418 * compare local_streams -> timing with dm_state->context, 1419 * if the same set crtc_state->mode-change = 0; 1420 */ 1421 for (i = 0; i < local_dc_state->stream_count; i++) { 1422 struct dc_stream_state *stream = dm_state->context->streams[i]; 1423 1424 if (local_dc_state->streams[i] && 1425 is_timing_changed(stream, local_dc_state->streams[i])) { 1426 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1427 } else { 1428 int ind = find_crtc_index_in_state_by_stream(state, stream); 1429 1430 if (ind >= 0) 1431 state->crtcs[ind].new_state->mode_changed = 0; 1432 } 1433 } 1434 clean_exit: 1435 for (i = 0; i < local_dc_state->stream_count; i++) { 1436 struct dc_stream_state *stream = dm_state->context->streams[i]; 1437 1438 if (local_dc_state->streams[i] != stream) 1439 dc_stream_release(local_dc_state->streams[i]); 1440 } 1441 1442 kfree(local_dc_state); 1443 1444 return ret; 1445 } 1446 1447 static unsigned int kbps_from_pbn(unsigned int pbn) 1448 { 1449 unsigned int kbps = pbn; 1450 1451 kbps *= (1000000 / PEAK_FACTOR_X1000); 1452 kbps *= 8; 1453 kbps *= 54; 1454 kbps /= 64; 1455 1456 return kbps; 1457 } 1458 1459 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1460 struct dc_dsc_bw_range *bw_range) 1461 { 1462 struct dc_dsc_policy dsc_policy = {0}; 1463 1464 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); 1465 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1466 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1467 dsc_policy.min_target_bpp * 16, 1468 dsc_policy.max_target_bpp * 16, 1469 &stream->sink->dsc_caps.dsc_dec_caps, 1470 &stream->timing, bw_range); 1471 1472 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1473 } 1474 1475 enum dc_status dm_dp_mst_is_port_support_mode( 1476 struct amdgpu_dm_connector *aconnector, 1477 struct dc_stream_state *stream) 1478 { 1479 int bpp, pbn, branch_max_throughput_mps = 0; 1480 struct dc_link_settings cur_link_settings; 1481 unsigned int end_to_end_bw_in_kbps = 0; 1482 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1483 unsigned int max_compressed_bw_in_kbps = 0; 1484 struct dc_dsc_bw_range bw_range = {0}; 1485 struct drm_dp_mst_topology_mgr *mst_mgr; 1486 1487 /* 1488 * check if the mode could be supported if DSC pass-through is supported 1489 * AND check if there enough bandwidth available to support the mode 1490 * with DSC enabled. 1491 */ 1492 if (is_dsc_common_config_possible(stream, &bw_range) && 1493 aconnector->mst_output_port->passthrough_aux) { 1494 mst_mgr = aconnector->mst_output_port->mgr; 1495 mutex_lock(&mst_mgr->lock); 1496 1497 cur_link_settings = stream->link->verified_link_cap; 1498 1499 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1500 &cur_link_settings 1501 ); 1502 down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn); 1503 1504 /* pick the bottleneck */ 1505 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, 1506 down_link_bw_in_kbps); 1507 1508 mutex_unlock(&mst_mgr->lock); 1509 1510 /* 1511 * use the maximum dsc compression bandwidth as the required 1512 * bandwidth for the mode 1513 */ 1514 max_compressed_bw_in_kbps = bw_range.min_kbps; 1515 1516 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) { 1517 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n"); 1518 return DC_FAIL_BANDWIDTH_VALIDATE; 1519 } 1520 } else { 1521 /* check if mode could be supported within full_pbn */ 1522 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1523 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false); 1524 1525 if (pbn > aconnector->mst_output_port->full_pbn) 1526 return DC_FAIL_BANDWIDTH_VALIDATE; 1527 } 1528 1529 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1530 switch (stream->timing.pixel_encoding) { 1531 case PIXEL_ENCODING_RGB: 1532 case PIXEL_ENCODING_YCBCR444: 1533 branch_max_throughput_mps = 1534 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1535 break; 1536 case PIXEL_ENCODING_YCBCR422: 1537 case PIXEL_ENCODING_YCBCR420: 1538 branch_max_throughput_mps = 1539 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1540 break; 1541 default: 1542 break; 1543 } 1544 1545 if (branch_max_throughput_mps != 0 && 1546 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1547 return DC_FAIL_BANDWIDTH_VALIDATE; 1548 1549 return DC_OK; 1550 } 1551