1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dp_helper.h> 27 #include <drm/display/drm_dp_mst_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include "dm_services.h" 31 #include "amdgpu.h" 32 #include "amdgpu_dm.h" 33 #include "amdgpu_dm_mst_types.h" 34 #include "amdgpu_dm_hdcp.h" 35 36 #include "dc.h" 37 #include "dm_helpers.h" 38 39 #include "ddc_service_types.h" 40 #include "dpcd_defs.h" 41 42 #include "dmub_cmd.h" 43 #if defined(CONFIG_DEBUG_FS) 44 #include "amdgpu_dm_debugfs.h" 45 #endif 46 47 #include "dc/dcn20/dcn20_resource.h" 48 49 #define PEAK_FACTOR_X1000 1006 50 51 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, 52 struct drm_dp_aux_msg *msg) 53 { 54 ssize_t result = 0; 55 struct aux_payload payload; 56 enum aux_return_code_type operation_result; 57 struct amdgpu_device *adev; 58 struct ddc_service *ddc; 59 60 if (WARN_ON(msg->size > 16)) 61 return -E2BIG; 62 63 payload.address = msg->address; 64 payload.data = msg->buffer; 65 payload.length = msg->size; 66 payload.reply = &msg->reply; 67 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0; 68 payload.write = (msg->request & DP_AUX_I2C_READ) == 0; 69 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0; 70 payload.write_status_update = 71 (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0; 72 payload.defer_delay = 0; 73 74 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload, 75 &operation_result); 76 77 /* 78 * w/a on certain intel platform where hpd is unexpected to pull low during 79 * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON 80 * aux transaction is succuess in such case, therefore bypass the error 81 */ 82 ddc = TO_DM_AUX(aux)->ddc_service; 83 adev = ddc->ctx->driver_context; 84 if (adev->dm.aux_hpd_discon_quirk) { 85 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE && 86 operation_result == AUX_RET_ERROR_HPD_DISCON) { 87 result = 0; 88 operation_result = AUX_RET_SUCCESS; 89 } 90 } 91 92 if (payload.write && result >= 0) 93 result = msg->size; 94 95 if (result < 0) 96 switch (operation_result) { 97 case AUX_RET_SUCCESS: 98 break; 99 case AUX_RET_ERROR_HPD_DISCON: 100 case AUX_RET_ERROR_UNKNOWN: 101 case AUX_RET_ERROR_INVALID_OPERATION: 102 case AUX_RET_ERROR_PROTOCOL_ERROR: 103 result = -EIO; 104 break; 105 case AUX_RET_ERROR_INVALID_REPLY: 106 case AUX_RET_ERROR_ENGINE_ACQUIRE: 107 result = -EBUSY; 108 break; 109 case AUX_RET_ERROR_TIMEOUT: 110 result = -ETIMEDOUT; 111 break; 112 } 113 114 return result; 115 } 116 117 static void 118 dm_dp_mst_connector_destroy(struct drm_connector *connector) 119 { 120 struct amdgpu_dm_connector *aconnector = 121 to_amdgpu_dm_connector(connector); 122 123 if (aconnector->dc_sink) { 124 dc_link_remove_remote_sink(aconnector->dc_link, 125 aconnector->dc_sink); 126 dc_sink_release(aconnector->dc_sink); 127 } 128 129 kfree(aconnector->edid); 130 131 drm_connector_cleanup(connector); 132 drm_dp_mst_put_port_malloc(aconnector->mst_output_port); 133 kfree(aconnector); 134 } 135 136 static int 137 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) 138 { 139 struct amdgpu_dm_connector *amdgpu_dm_connector = 140 to_amdgpu_dm_connector(connector); 141 int r; 142 143 r = drm_dp_mst_connector_late_register(connector, 144 amdgpu_dm_connector->mst_output_port); 145 if (r < 0) 146 return r; 147 148 #if defined(CONFIG_DEBUG_FS) 149 connector_debugfs_init(amdgpu_dm_connector); 150 #endif 151 152 return 0; 153 } 154 155 static void 156 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) 157 { 158 struct amdgpu_dm_connector *aconnector = 159 to_amdgpu_dm_connector(connector); 160 struct drm_dp_mst_port *port = aconnector->mst_output_port; 161 struct amdgpu_dm_connector *root = aconnector->mst_root; 162 struct dc_link *dc_link = aconnector->dc_link; 163 struct dc_sink *dc_sink = aconnector->dc_sink; 164 165 drm_dp_mst_connector_early_unregister(connector, port); 166 167 /* 168 * Release dc_sink for connector which its attached port is 169 * no longer in the mst topology 170 */ 171 drm_modeset_lock(&root->mst_mgr.base.lock, NULL); 172 if (dc_sink) { 173 if (dc_link->sink_count) 174 dc_link_remove_remote_sink(dc_link, dc_sink); 175 176 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 177 dc_sink, dc_link->sink_count); 178 179 dc_sink_release(dc_sink); 180 aconnector->dc_sink = NULL; 181 aconnector->edid = NULL; 182 } 183 184 aconnector->mst_status = MST_STATUS_DEFAULT; 185 drm_modeset_unlock(&root->mst_mgr.base.lock); 186 } 187 188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { 189 .fill_modes = drm_helper_probe_single_connector_modes, 190 .destroy = dm_dp_mst_connector_destroy, 191 .reset = amdgpu_dm_connector_funcs_reset, 192 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 193 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 194 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 195 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 196 .late_register = amdgpu_dm_mst_connector_late_register, 197 .early_unregister = amdgpu_dm_mst_connector_early_unregister, 198 }; 199 200 bool needs_dsc_aux_workaround(struct dc_link *link) 201 { 202 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 203 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) && 204 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2) 205 return true; 206 207 return false; 208 } 209 210 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port) 211 { 212 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F 213 214 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) { 215 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 216 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) { 217 DRM_INFO("Synaptics Cascaded MST hub\n"); 218 return true; 219 } 220 } 221 222 return false; 223 } 224 225 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) 226 { 227 struct dc_sink *dc_sink = aconnector->dc_sink; 228 struct drm_dp_mst_port *port = aconnector->mst_output_port; 229 u8 dsc_caps[16] = { 0 }; 230 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 231 u8 *dsc_branch_dec_caps = NULL; 232 233 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); 234 235 /* 236 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs 237 * because it only check the dsc/fec caps of the "port variable" and not the dock 238 * 239 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display 240 * 241 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux 242 * 243 */ 244 if (!aconnector->dsc_aux && !port->parent->port_parent && 245 needs_dsc_aux_workaround(aconnector->dc_link)) 246 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; 247 248 /* synaptics cascaded MST hub case */ 249 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port)) 250 aconnector->dsc_aux = port->mgr->aux; 251 252 if (!aconnector->dsc_aux) 253 return false; 254 255 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) 256 return false; 257 258 if (drm_dp_dpcd_read(aconnector->dsc_aux, 259 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3) 260 dsc_branch_dec_caps = dsc_branch_dec_caps_raw; 261 262 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 263 dsc_caps, dsc_branch_dec_caps, 264 &dc_sink->dsc_caps.dsc_dec_caps)) 265 return false; 266 267 return true; 268 } 269 270 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) 271 { 272 union dp_downstream_port_present ds_port_present; 273 274 if (!aconnector->dsc_aux) 275 return false; 276 277 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) { 278 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n"); 279 return false; 280 } 281 282 aconnector->mst_downstream_port_present = ds_port_present; 283 DRM_INFO("Downstream port present %d, type %d\n", 284 ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE); 285 286 return true; 287 } 288 289 static int dm_dp_mst_get_modes(struct drm_connector *connector) 290 { 291 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 292 int ret = 0; 293 294 if (!aconnector) 295 return drm_add_edid_modes(connector, NULL); 296 297 if (!aconnector->edid) { 298 struct edid *edid; 299 300 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); 301 302 if (!edid) { 303 amdgpu_dm_set_mst_status(&aconnector->mst_status, 304 MST_REMOTE_EDID, false); 305 306 drm_connector_update_edid_property( 307 &aconnector->base, 308 NULL); 309 310 DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); 311 if (!aconnector->dc_sink) { 312 struct dc_sink *dc_sink; 313 struct dc_sink_init_data init_params = { 314 .link = aconnector->dc_link, 315 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 316 317 dc_sink = dc_link_add_remote_sink( 318 aconnector->dc_link, 319 NULL, 320 0, 321 &init_params); 322 323 if (!dc_sink) { 324 DRM_ERROR("Unable to add a remote sink\n"); 325 return 0; 326 } 327 328 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 329 dc_sink, aconnector->dc_link->sink_count); 330 331 dc_sink->priv = aconnector; 332 aconnector->dc_sink = dc_sink; 333 } 334 335 return ret; 336 } 337 338 aconnector->edid = edid; 339 amdgpu_dm_set_mst_status(&aconnector->mst_status, 340 MST_REMOTE_EDID, true); 341 } 342 343 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) { 344 dc_sink_release(aconnector->dc_sink); 345 aconnector->dc_sink = NULL; 346 } 347 348 if (!aconnector->dc_sink) { 349 struct dc_sink *dc_sink; 350 struct dc_sink_init_data init_params = { 351 .link = aconnector->dc_link, 352 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; 353 dc_sink = dc_link_add_remote_sink( 354 aconnector->dc_link, 355 (uint8_t *)aconnector->edid, 356 (aconnector->edid->extensions + 1) * EDID_LENGTH, 357 &init_params); 358 359 if (!dc_sink) { 360 DRM_ERROR("Unable to add a remote sink\n"); 361 return 0; 362 } 363 364 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n", 365 dc_sink, aconnector->dc_link->sink_count); 366 367 dc_sink->priv = aconnector; 368 /* dc_link_add_remote_sink returns a new reference */ 369 aconnector->dc_sink = dc_sink; 370 371 /* when display is unplugged from mst hub, connctor will be 372 * destroyed within dm_dp_mst_connector_destroy. connector 373 * hdcp perperties, like type, undesired, desired, enabled, 374 * will be lost. So, save hdcp properties into hdcp_work within 375 * amdgpu_dm_atomic_commit_tail. if the same display is 376 * plugged back with same display index, its hdcp properties 377 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 378 */ 379 if (aconnector->dc_sink && connector->state) { 380 struct drm_device *dev = connector->dev; 381 struct amdgpu_device *adev = drm_to_adev(dev); 382 383 if (adev->dm.hdcp_workqueue) { 384 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 385 struct hdcp_workqueue *hdcp_w = 386 &hdcp_work[aconnector->dc_link->link_index]; 387 388 connector->state->hdcp_content_type = 389 hdcp_w->hdcp_content_type[connector->index]; 390 connector->state->content_protection = 391 hdcp_w->content_protection[connector->index]; 392 } 393 } 394 395 if (aconnector->dc_sink) { 396 amdgpu_dm_update_freesync_caps( 397 connector, aconnector->edid); 398 399 if (!validate_dsc_caps_on_connector(aconnector)) 400 memset(&aconnector->dc_sink->dsc_caps, 401 0, sizeof(aconnector->dc_sink->dsc_caps)); 402 403 if (!retrieve_downstream_port_device(aconnector)) 404 memset(&aconnector->mst_downstream_port_present, 405 0, sizeof(aconnector->mst_downstream_port_present)); 406 } 407 } 408 409 drm_connector_update_edid_property( 410 &aconnector->base, aconnector->edid); 411 412 ret = drm_add_edid_modes(connector, aconnector->edid); 413 414 return ret; 415 } 416 417 static struct drm_encoder * 418 dm_mst_atomic_best_encoder(struct drm_connector *connector, 419 struct drm_atomic_state *state) 420 { 421 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 422 connector); 423 struct drm_device *dev = connector->dev; 424 struct amdgpu_device *adev = drm_to_adev(dev); 425 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); 426 427 return &adev->dm.mst_encoders[acrtc->crtc_id].base; 428 } 429 430 static int 431 dm_dp_mst_detect(struct drm_connector *connector, 432 struct drm_modeset_acquire_ctx *ctx, bool force) 433 { 434 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 435 struct amdgpu_dm_connector *master = aconnector->mst_root; 436 struct drm_dp_mst_port *port = aconnector->mst_output_port; 437 int connection_status; 438 439 if (drm_connector_is_unregistered(connector)) 440 return connector_status_disconnected; 441 442 connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr, 443 aconnector->mst_output_port); 444 445 if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) { 446 uint8_t dpcd_rev; 447 int ret; 448 449 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev); 450 451 if (ret == 1) { 452 port->dpcd_rev = dpcd_rev; 453 454 /* Could be DP1.2 DP Rx case*/ 455 if (!dpcd_rev) { 456 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev); 457 458 if (ret == 1) 459 port->dpcd_rev = dpcd_rev; 460 } 461 462 if (!dpcd_rev) 463 DRM_DEBUG_KMS("Can't decide DPCD revision number!"); 464 } 465 466 /* 467 * Could be legacy sink, logical port etc on DP1.2. 468 * Will get Nack under these cases when issue remote 469 * DPCD read. 470 */ 471 if (ret != 1) 472 DRM_DEBUG_KMS("Can't access DPCD"); 473 } else if (port->pdt == DP_PEER_DEVICE_NONE) { 474 port->dpcd_rev = 0; 475 } 476 477 /* 478 * Release dc_sink for connector which unplug event is notified by CSN msg 479 */ 480 if (connection_status == connector_status_disconnected && aconnector->dc_sink) { 481 if (aconnector->dc_link->sink_count) 482 dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); 483 484 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n", 485 aconnector->dc_link, aconnector->dc_link->sink_count); 486 487 dc_sink_release(aconnector->dc_sink); 488 aconnector->dc_sink = NULL; 489 aconnector->edid = NULL; 490 491 amdgpu_dm_set_mst_status(&aconnector->mst_status, 492 MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, 493 false); 494 } 495 496 return connection_status; 497 } 498 499 static int dm_dp_mst_atomic_check(struct drm_connector *connector, 500 struct drm_atomic_state *state) 501 { 502 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 503 struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; 504 struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; 505 506 return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); 507 } 508 509 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { 510 .get_modes = dm_dp_mst_get_modes, 511 .mode_valid = amdgpu_dm_connector_mode_valid, 512 .atomic_best_encoder = dm_mst_atomic_best_encoder, 513 .detect_ctx = dm_dp_mst_detect, 514 .atomic_check = dm_dp_mst_atomic_check, 515 }; 516 517 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 518 { 519 drm_encoder_cleanup(encoder); 520 } 521 522 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 523 .destroy = amdgpu_dm_encoder_destroy, 524 }; 525 526 void 527 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev) 528 { 529 struct drm_device *dev = adev_to_drm(adev); 530 int i; 531 532 for (i = 0; i < adev->dm.display_indexes_num; i++) { 533 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i]; 534 struct drm_encoder *encoder = &amdgpu_encoder->base; 535 536 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 537 538 drm_encoder_init( 539 dev, 540 &amdgpu_encoder->base, 541 &amdgpu_dm_encoder_funcs, 542 DRM_MODE_ENCODER_DPMST, 543 NULL); 544 545 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs); 546 } 547 } 548 549 static struct drm_connector * 550 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 551 struct drm_dp_mst_port *port, 552 const char *pathprop) 553 { 554 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 555 struct drm_device *dev = master->base.dev; 556 struct amdgpu_device *adev = drm_to_adev(dev); 557 struct amdgpu_dm_connector *aconnector; 558 struct drm_connector *connector; 559 int i; 560 561 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 562 if (!aconnector) 563 return NULL; 564 565 connector = &aconnector->base; 566 aconnector->mst_output_port = port; 567 aconnector->mst_root = master; 568 amdgpu_dm_set_mst_status(&aconnector->mst_status, 569 MST_PROBE, true); 570 571 if (drm_connector_init( 572 dev, 573 connector, 574 &dm_dp_mst_connector_funcs, 575 DRM_MODE_CONNECTOR_DisplayPort)) { 576 kfree(aconnector); 577 return NULL; 578 } 579 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs); 580 581 amdgpu_dm_connector_init_helper( 582 &adev->dm, 583 aconnector, 584 DRM_MODE_CONNECTOR_DisplayPort, 585 master->dc_link, 586 master->connector_id); 587 588 for (i = 0; i < adev->dm.display_indexes_num; i++) { 589 drm_connector_attach_encoder(&aconnector->base, 590 &adev->dm.mst_encoders[i].base); 591 } 592 593 connector->max_bpc_property = master->base.max_bpc_property; 594 if (connector->max_bpc_property) 595 drm_connector_attach_max_bpc_property(connector, 8, 16); 596 597 connector->vrr_capable_property = master->base.vrr_capable_property; 598 if (connector->vrr_capable_property) 599 drm_connector_attach_vrr_capable_property(connector); 600 601 drm_object_attach_property( 602 &connector->base, 603 dev->mode_config.path_property, 604 0); 605 drm_object_attach_property( 606 &connector->base, 607 dev->mode_config.tile_property, 608 0); 609 connector->colorspace_property = master->base.colorspace_property; 610 if (connector->colorspace_property) 611 drm_connector_attach_colorspace_property(connector); 612 613 drm_connector_set_path_property(connector, pathprop); 614 615 /* 616 * Initialize connector state before adding the connectror to drm and 617 * framebuffer lists 618 */ 619 amdgpu_dm_connector_funcs_reset(connector); 620 621 drm_dp_mst_get_port_malloc(port); 622 623 return connector; 624 } 625 626 void dm_handle_mst_sideband_msg_ready_event( 627 struct drm_dp_mst_topology_mgr *mgr, 628 enum mst_msg_ready_type msg_rdy_type) 629 { 630 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; 631 uint8_t dret; 632 bool new_irq_handled = false; 633 int dpcd_addr; 634 uint8_t dpcd_bytes_to_read; 635 const uint8_t max_process_count = 30; 636 uint8_t process_count = 0; 637 u8 retry; 638 struct amdgpu_dm_connector *aconnector = 639 container_of(mgr, struct amdgpu_dm_connector, mst_mgr); 640 641 642 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); 643 644 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { 645 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; 646 /* DPCD 0x200 - 0x201 for downstream IRQ */ 647 dpcd_addr = DP_SINK_COUNT; 648 } else { 649 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; 650 /* DPCD 0x2002 - 0x2005 for downstream IRQ */ 651 dpcd_addr = DP_SINK_COUNT_ESI; 652 } 653 654 mutex_lock(&aconnector->handle_mst_msg_ready); 655 656 while (process_count < max_process_count) { 657 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {}; 658 659 process_count++; 660 661 dret = drm_dp_dpcd_read( 662 &aconnector->dm_dp_aux.aux, 663 dpcd_addr, 664 esi, 665 dpcd_bytes_to_read); 666 667 if (dret != dpcd_bytes_to_read) { 668 DRM_DEBUG_KMS("DPCD read and acked number is not as expected!"); 669 break; 670 } 671 672 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); 673 674 switch (msg_rdy_type) { 675 case DOWN_REP_MSG_RDY_EVENT: 676 /* Only handle DOWN_REP_MSG_RDY case*/ 677 esi[1] &= DP_DOWN_REP_MSG_RDY; 678 break; 679 case UP_REQ_MSG_RDY_EVENT: 680 /* Only handle UP_REQ_MSG_RDY case*/ 681 esi[1] &= DP_UP_REQ_MSG_RDY; 682 break; 683 default: 684 /* Handle both cases*/ 685 esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY); 686 break; 687 } 688 689 if (!esi[1]) 690 break; 691 692 /* handle MST irq */ 693 if (aconnector->mst_mgr.mst_state) 694 drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, 695 esi, 696 ack, 697 &new_irq_handled); 698 699 if (new_irq_handled) { 700 /* ACK at DPCD to notify down stream */ 701 for (retry = 0; retry < 3; retry++) { 702 ssize_t wret; 703 704 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux, 705 dpcd_addr + 1, 706 ack[1]); 707 if (wret == 1) 708 break; 709 } 710 711 if (retry == 3) { 712 DRM_ERROR("Failed to ack MST event.\n"); 713 break; 714 } 715 716 drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); 717 718 new_irq_handled = false; 719 } else { 720 break; 721 } 722 } 723 724 mutex_unlock(&aconnector->handle_mst_msg_ready); 725 726 if (process_count == max_process_count) 727 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); 728 } 729 730 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) 731 { 732 dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); 733 } 734 735 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { 736 .add_connector = dm_dp_add_mst_connector, 737 .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, 738 }; 739 740 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 741 struct amdgpu_dm_connector *aconnector, 742 int link_index) 743 { 744 struct dc_link_settings max_link_enc_cap = {0}; 745 746 aconnector->dm_dp_aux.aux.name = 747 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", 748 link_index); 749 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; 750 aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; 751 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; 752 753 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 754 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 755 &aconnector->base); 756 757 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 758 return; 759 760 dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); 761 aconnector->mst_mgr.cbs = &dm_mst_cbs; 762 drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), 763 &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); 764 765 drm_connector_attach_dp_subconnector_property(&aconnector->base); 766 } 767 768 int dm_mst_get_pbn_divider(struct dc_link *link) 769 { 770 if (!link) 771 return 0; 772 773 return dc_link_bandwidth_kbps(link, 774 dc_link_get_link_cap(link)) / (8 * 1000 * 54); 775 } 776 777 struct dsc_mst_fairness_params { 778 struct dc_crtc_timing *timing; 779 struct dc_sink *sink; 780 struct dc_dsc_bw_range bw_range; 781 bool compression_possible; 782 struct drm_dp_mst_port *port; 783 enum dsc_clock_force_state clock_force_enable; 784 uint32_t num_slices_h; 785 uint32_t num_slices_v; 786 uint32_t bpp_overwrite; 787 struct amdgpu_dm_connector *aconnector; 788 }; 789 790 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) 791 { 792 u8 link_coding_cap; 793 uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B; 794 795 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link); 796 if (link_coding_cap == DP_128b_132b_ENCODING) 797 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B; 798 799 return fec_overhead_multiplier_x1000; 800 } 801 802 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) 803 { 804 u64 peak_kbps = kbps; 805 806 peak_kbps *= 1006; 807 peak_kbps *= fec_overhead_multiplier_x1000; 808 peak_kbps = div_u64(peak_kbps, 1000 * 1000); 809 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 810 } 811 812 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, 813 struct dsc_mst_fairness_vars *vars, 814 int count, 815 int k) 816 { 817 struct drm_connector *drm_connector; 818 int i; 819 struct dc_dsc_config_options dsc_options = {0}; 820 821 for (i = 0; i < count; i++) { 822 drm_connector = ¶ms[i].aconnector->base; 823 824 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); 825 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 826 827 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); 828 if (vars[i + k].dsc_enabled && dc_dsc_compute_config( 829 params[i].sink->ctx->dc->res_pool->dscs[0], 830 ¶ms[i].sink->dsc_caps.dsc_dec_caps, 831 &dsc_options, 832 0, 833 params[i].timing, 834 dc_link_get_highest_encoding_format(params[i].aconnector->dc_link), 835 ¶ms[i].timing->dsc_cfg)) { 836 params[i].timing->flags.DSC = 1; 837 838 if (params[i].bpp_overwrite) 839 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; 840 else 841 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16; 842 843 if (params[i].num_slices_h) 844 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; 845 846 if (params[i].num_slices_v) 847 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; 848 } else { 849 params[i].timing->flags.DSC = 0; 850 } 851 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn; 852 } 853 854 for (i = 0; i < count; i++) { 855 if (params[i].sink) { 856 if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 857 params[i].sink->sink_signal != SIGNAL_TYPE_NONE) 858 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, 859 params[i].sink->edid_caps.display_name); 860 } 861 862 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", 863 params[i].timing->flags.DSC, 864 params[i].timing->dsc_cfg.bits_per_pixel, 865 vars[i + k].pbn); 866 } 867 } 868 869 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) 870 { 871 struct dc_dsc_config dsc_config; 872 u64 kbps; 873 874 struct drm_connector *drm_connector = ¶m.aconnector->base; 875 struct dc_dsc_config_options dsc_options = {0}; 876 877 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); 878 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 879 880 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 881 dc_dsc_compute_config( 882 param.sink->ctx->dc->res_pool->dscs[0], 883 ¶m.sink->dsc_caps.dsc_dec_caps, 884 &dsc_options, 885 (int) kbps, param.timing, 886 dc_link_get_highest_encoding_format(param.aconnector->dc_link), 887 &dsc_config); 888 889 return dsc_config.bits_per_pixel; 890 } 891 892 static int increase_dsc_bpp(struct drm_atomic_state *state, 893 struct drm_dp_mst_topology_state *mst_state, 894 struct dc_link *dc_link, 895 struct dsc_mst_fairness_params *params, 896 struct dsc_mst_fairness_vars *vars, 897 int count, 898 int k) 899 { 900 int i; 901 bool bpp_increased[MAX_PIPES]; 902 int initial_slack[MAX_PIPES]; 903 int min_initial_slack; 904 int next_index; 905 int remaining_to_increase = 0; 906 int link_timeslots_used; 907 int fair_pbn_alloc; 908 int ret = 0; 909 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 910 911 for (i = 0; i < count; i++) { 912 if (vars[i + k].dsc_enabled) { 913 initial_slack[i] = 914 kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn; 915 bpp_increased[i] = false; 916 remaining_to_increase += 1; 917 } else { 918 initial_slack[i] = 0; 919 bpp_increased[i] = true; 920 } 921 } 922 923 while (remaining_to_increase) { 924 next_index = -1; 925 min_initial_slack = -1; 926 for (i = 0; i < count; i++) { 927 if (!bpp_increased[i]) { 928 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { 929 min_initial_slack = initial_slack[i]; 930 next_index = i; 931 } 932 } 933 } 934 935 if (next_index == -1) 936 break; 937 938 link_timeslots_used = 0; 939 940 for (i = 0; i < count; i++) 941 link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div); 942 943 fair_pbn_alloc = 944 (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div; 945 946 if (initial_slack[next_index] > fair_pbn_alloc) { 947 vars[next_index].pbn += fair_pbn_alloc; 948 ret = drm_dp_atomic_find_time_slots(state, 949 params[next_index].port->mgr, 950 params[next_index].port, 951 vars[next_index].pbn); 952 if (ret < 0) 953 return ret; 954 955 ret = drm_dp_mst_atomic_check(state); 956 if (ret == 0) { 957 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); 958 } else { 959 vars[next_index].pbn -= fair_pbn_alloc; 960 ret = drm_dp_atomic_find_time_slots(state, 961 params[next_index].port->mgr, 962 params[next_index].port, 963 vars[next_index].pbn); 964 if (ret < 0) 965 return ret; 966 } 967 } else { 968 vars[next_index].pbn += initial_slack[next_index]; 969 ret = drm_dp_atomic_find_time_slots(state, 970 params[next_index].port->mgr, 971 params[next_index].port, 972 vars[next_index].pbn); 973 if (ret < 0) 974 return ret; 975 976 ret = drm_dp_mst_atomic_check(state); 977 if (ret == 0) { 978 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; 979 } else { 980 vars[next_index].pbn -= initial_slack[next_index]; 981 ret = drm_dp_atomic_find_time_slots(state, 982 params[next_index].port->mgr, 983 params[next_index].port, 984 vars[next_index].pbn); 985 if (ret < 0) 986 return ret; 987 } 988 } 989 990 bpp_increased[next_index] = true; 991 remaining_to_increase--; 992 } 993 return 0; 994 } 995 996 static int try_disable_dsc(struct drm_atomic_state *state, 997 struct dc_link *dc_link, 998 struct dsc_mst_fairness_params *params, 999 struct dsc_mst_fairness_vars *vars, 1000 int count, 1001 int k) 1002 { 1003 int i; 1004 bool tried[MAX_PIPES]; 1005 int kbps_increase[MAX_PIPES]; 1006 int max_kbps_increase; 1007 int next_index; 1008 int remaining_to_try = 0; 1009 int ret; 1010 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1011 1012 for (i = 0; i < count; i++) { 1013 if (vars[i + k].dsc_enabled 1014 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16 1015 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) { 1016 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; 1017 tried[i] = false; 1018 remaining_to_try += 1; 1019 } else { 1020 kbps_increase[i] = 0; 1021 tried[i] = true; 1022 } 1023 } 1024 1025 while (remaining_to_try) { 1026 next_index = -1; 1027 max_kbps_increase = -1; 1028 for (i = 0; i < count; i++) { 1029 if (!tried[i]) { 1030 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { 1031 max_kbps_increase = kbps_increase[i]; 1032 next_index = i; 1033 } 1034 } 1035 } 1036 1037 if (next_index == -1) 1038 break; 1039 1040 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1041 ret = drm_dp_atomic_find_time_slots(state, 1042 params[next_index].port->mgr, 1043 params[next_index].port, 1044 vars[next_index].pbn); 1045 if (ret < 0) 1046 return ret; 1047 1048 ret = drm_dp_mst_atomic_check(state); 1049 if (ret == 0) { 1050 vars[next_index].dsc_enabled = false; 1051 vars[next_index].bpp_x16 = 0; 1052 } else { 1053 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); 1054 ret = drm_dp_atomic_find_time_slots(state, 1055 params[next_index].port->mgr, 1056 params[next_index].port, 1057 vars[next_index].pbn); 1058 if (ret < 0) 1059 return ret; 1060 } 1061 1062 tried[next_index] = true; 1063 remaining_to_try--; 1064 } 1065 return 0; 1066 } 1067 1068 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, 1069 struct dc_state *dc_state, 1070 struct dc_link *dc_link, 1071 struct dsc_mst_fairness_vars *vars, 1072 struct drm_dp_mst_topology_mgr *mgr, 1073 int *link_vars_start_index) 1074 { 1075 struct dc_stream_state *stream; 1076 struct dsc_mst_fairness_params params[MAX_PIPES]; 1077 struct amdgpu_dm_connector *aconnector; 1078 struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr); 1079 int count = 0; 1080 int i, k, ret; 1081 bool debugfs_overwrite = false; 1082 uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1083 1084 memset(params, 0, sizeof(params)); 1085 1086 if (IS_ERR(mst_state)) 1087 return PTR_ERR(mst_state); 1088 1089 /* Set up params */ 1090 for (i = 0; i < dc_state->stream_count; i++) { 1091 struct dc_dsc_policy dsc_policy = {0}; 1092 1093 stream = dc_state->streams[i]; 1094 1095 if (stream->link != dc_link) 1096 continue; 1097 1098 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1099 if (!aconnector) 1100 continue; 1101 1102 if (!aconnector->mst_output_port) 1103 continue; 1104 1105 stream->timing.flags.DSC = 0; 1106 1107 params[count].timing = &stream->timing; 1108 params[count].sink = stream->sink; 1109 params[count].aconnector = aconnector; 1110 params[count].port = aconnector->mst_output_port; 1111 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable; 1112 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE) 1113 debugfs_overwrite = true; 1114 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 1115 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 1116 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; 1117 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; 1118 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); 1119 if (!dc_dsc_compute_bandwidth_range( 1120 stream->sink->ctx->dc->res_pool->dscs[0], 1121 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1122 dsc_policy.min_target_bpp * 16, 1123 dsc_policy.max_target_bpp * 16, 1124 &stream->sink->dsc_caps.dsc_dec_caps, 1125 &stream->timing, 1126 dc_link_get_highest_encoding_format(dc_link), 1127 ¶ms[count].bw_range)) 1128 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 1129 dc_link_get_highest_encoding_format(dc_link)); 1130 1131 count++; 1132 } 1133 1134 if (count == 0) { 1135 ASSERT(0); 1136 return 0; 1137 } 1138 1139 /* k is start index of vars for current phy link used by mst hub */ 1140 k = *link_vars_start_index; 1141 /* set vars start index for next mst hub phy link */ 1142 *link_vars_start_index += count; 1143 1144 /* Try no compression */ 1145 for (i = 0; i < count; i++) { 1146 vars[i + k].aconnector = params[i].aconnector; 1147 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1148 vars[i + k].dsc_enabled = false; 1149 vars[i + k].bpp_x16 = 0; 1150 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, 1151 vars[i + k].pbn); 1152 if (ret < 0) 1153 return ret; 1154 } 1155 ret = drm_dp_mst_atomic_check(state); 1156 if (ret == 0 && !debugfs_overwrite) { 1157 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1158 return 0; 1159 } else if (ret != -ENOSPC) { 1160 return ret; 1161 } 1162 1163 /* Try max compression */ 1164 for (i = 0; i < count; i++) { 1165 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1166 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); 1167 vars[i + k].dsc_enabled = true; 1168 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1169 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1170 params[i].port, vars[i + k].pbn); 1171 if (ret < 0) 1172 return ret; 1173 } else { 1174 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1175 vars[i + k].dsc_enabled = false; 1176 vars[i + k].bpp_x16 = 0; 1177 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, 1178 params[i].port, vars[i + k].pbn); 1179 if (ret < 0) 1180 return ret; 1181 } 1182 } 1183 ret = drm_dp_mst_atomic_check(state); 1184 if (ret != 0) 1185 return ret; 1186 1187 /* Optimize degree of compression */ 1188 ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); 1189 if (ret < 0) 1190 return ret; 1191 1192 ret = try_disable_dsc(state, dc_link, params, vars, count, k); 1193 if (ret < 0) 1194 return ret; 1195 1196 set_dsc_configs_from_fairness_vars(params, vars, count, k); 1197 1198 return 0; 1199 } 1200 1201 static bool is_dsc_need_re_compute( 1202 struct drm_atomic_state *state, 1203 struct dc_state *dc_state, 1204 struct dc_link *dc_link) 1205 { 1206 int i, j; 1207 bool is_dsc_need_re_compute = false; 1208 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; 1209 int new_stream_on_link_num = 0; 1210 struct amdgpu_dm_connector *aconnector; 1211 struct dc_stream_state *stream; 1212 const struct dc *dc = dc_link->dc; 1213 1214 /* only check phy used by dsc mst branch */ 1215 if (dc_link->type != dc_connection_mst_branch) 1216 return false; 1217 1218 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || 1219 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1220 return false; 1221 1222 for (i = 0; i < MAX_PIPES; i++) 1223 stream_on_link[i] = NULL; 1224 1225 /* check if there is mode change in new request */ 1226 for (i = 0; i < dc_state->stream_count; i++) { 1227 struct drm_crtc_state *new_crtc_state; 1228 struct drm_connector_state *new_conn_state; 1229 1230 stream = dc_state->streams[i]; 1231 if (!stream) 1232 continue; 1233 1234 /* check if stream using the same link for mst */ 1235 if (stream->link != dc_link) 1236 continue; 1237 1238 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; 1239 if (!aconnector) 1240 continue; 1241 1242 stream_on_link[new_stream_on_link_num] = aconnector; 1243 new_stream_on_link_num++; 1244 1245 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); 1246 if (!new_conn_state) 1247 continue; 1248 1249 if (IS_ERR(new_conn_state)) 1250 continue; 1251 1252 if (!new_conn_state->crtc) 1253 continue; 1254 1255 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 1256 if (!new_crtc_state) 1257 continue; 1258 1259 if (IS_ERR(new_crtc_state)) 1260 continue; 1261 1262 if (new_crtc_state->enable && new_crtc_state->active) { 1263 if (new_crtc_state->mode_changed || new_crtc_state->active_changed || 1264 new_crtc_state->connectors_changed) 1265 return true; 1266 } 1267 } 1268 1269 /* check current_state if there stream on link but it is not in 1270 * new request state 1271 */ 1272 for (i = 0; i < dc->current_state->stream_count; i++) { 1273 stream = dc->current_state->streams[i]; 1274 /* only check stream on the mst hub */ 1275 if (stream->link != dc_link) 1276 continue; 1277 1278 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1279 if (!aconnector) 1280 continue; 1281 1282 for (j = 0; j < new_stream_on_link_num; j++) { 1283 if (stream_on_link[j]) { 1284 if (aconnector == stream_on_link[j]) 1285 break; 1286 } 1287 } 1288 1289 if (j == new_stream_on_link_num) { 1290 /* not in new state */ 1291 is_dsc_need_re_compute = true; 1292 break; 1293 } 1294 } 1295 1296 return is_dsc_need_re_compute; 1297 } 1298 1299 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1300 struct dc_state *dc_state, 1301 struct dsc_mst_fairness_vars *vars) 1302 { 1303 int i, j; 1304 struct dc_stream_state *stream; 1305 bool computed_streams[MAX_PIPES]; 1306 struct amdgpu_dm_connector *aconnector; 1307 struct drm_dp_mst_topology_mgr *mst_mgr; 1308 struct resource_pool *res_pool; 1309 int link_vars_start_index = 0; 1310 int ret = 0; 1311 1312 for (i = 0; i < dc_state->stream_count; i++) 1313 computed_streams[i] = false; 1314 1315 for (i = 0; i < dc_state->stream_count; i++) { 1316 stream = dc_state->streams[i]; 1317 res_pool = stream->ctx->dc->res_pool; 1318 1319 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1320 continue; 1321 1322 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1323 1324 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1325 continue; 1326 1327 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1328 continue; 1329 1330 if (computed_streams[i]) 1331 continue; 1332 1333 if (res_pool->funcs->remove_stream_from_ctx && 1334 res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK) 1335 return -EINVAL; 1336 1337 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1338 continue; 1339 1340 mst_mgr = aconnector->mst_output_port->mgr; 1341 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1342 &link_vars_start_index); 1343 if (ret != 0) 1344 return ret; 1345 1346 for (j = 0; j < dc_state->stream_count; j++) { 1347 if (dc_state->streams[j]->link == stream->link) 1348 computed_streams[j] = true; 1349 } 1350 } 1351 1352 for (i = 0; i < dc_state->stream_count; i++) { 1353 stream = dc_state->streams[i]; 1354 1355 if (stream->timing.flags.DSC == 1) 1356 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) 1357 return -EINVAL; 1358 } 1359 1360 return ret; 1361 } 1362 1363 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 1364 struct dc_state *dc_state, 1365 struct dsc_mst_fairness_vars *vars) 1366 { 1367 int i, j; 1368 struct dc_stream_state *stream; 1369 bool computed_streams[MAX_PIPES]; 1370 struct amdgpu_dm_connector *aconnector; 1371 struct drm_dp_mst_topology_mgr *mst_mgr; 1372 int link_vars_start_index = 0; 1373 int ret = 0; 1374 1375 for (i = 0; i < dc_state->stream_count; i++) 1376 computed_streams[i] = false; 1377 1378 for (i = 0; i < dc_state->stream_count; i++) { 1379 stream = dc_state->streams[i]; 1380 1381 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) 1382 continue; 1383 1384 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 1385 1386 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) 1387 continue; 1388 1389 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported) 1390 continue; 1391 1392 if (computed_streams[i]) 1393 continue; 1394 1395 if (!is_dsc_need_re_compute(state, dc_state, stream->link)) 1396 continue; 1397 1398 mst_mgr = aconnector->mst_output_port->mgr; 1399 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr, 1400 &link_vars_start_index); 1401 if (ret != 0) 1402 return ret; 1403 1404 for (j = 0; j < dc_state->stream_count; j++) { 1405 if (dc_state->streams[j]->link == stream->link) 1406 computed_streams[j] = true; 1407 } 1408 } 1409 1410 return ret; 1411 } 1412 1413 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state, 1414 struct dc_stream_state *stream) 1415 { 1416 int i; 1417 struct drm_crtc *crtc; 1418 struct drm_crtc_state *new_state, *old_state; 1419 1420 for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) { 1421 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state); 1422 1423 if (dm_state->stream == stream) 1424 return i; 1425 } 1426 return -1; 1427 } 1428 1429 static bool is_link_to_dschub(struct dc_link *dc_link) 1430 { 1431 union dpcd_dsc_basic_capabilities *dsc_caps = 1432 &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps; 1433 1434 /* only check phy used by dsc mst branch */ 1435 if (dc_link->type != dc_connection_mst_branch) 1436 return false; 1437 1438 if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT || 1439 dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)) 1440 return false; 1441 return true; 1442 } 1443 1444 static bool is_dsc_precompute_needed(struct drm_atomic_state *state) 1445 { 1446 int i; 1447 struct drm_crtc *crtc; 1448 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 1449 bool ret = false; 1450 1451 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1452 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state); 1453 1454 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) { 1455 ret = false; 1456 break; 1457 } 1458 if (dm_crtc_state->stream && dm_crtc_state->stream->link) 1459 if (is_link_to_dschub(dm_crtc_state->stream->link)) 1460 ret = true; 1461 } 1462 return ret; 1463 } 1464 1465 int pre_validate_dsc(struct drm_atomic_state *state, 1466 struct dm_atomic_state **dm_state_ptr, 1467 struct dsc_mst_fairness_vars *vars) 1468 { 1469 int i; 1470 struct dm_atomic_state *dm_state; 1471 struct dc_state *local_dc_state = NULL; 1472 int ret = 0; 1473 1474 if (!is_dsc_precompute_needed(state)) { 1475 DRM_INFO_ONCE("DSC precompute is not needed.\n"); 1476 return 0; 1477 } 1478 ret = dm_atomic_get_state(state, dm_state_ptr); 1479 if (ret != 0) { 1480 DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); 1481 return ret; 1482 } 1483 dm_state = *dm_state_ptr; 1484 1485 /* 1486 * create local vailable for dc_state. copy content of streams of dm_state->context 1487 * to local variable. make sure stream pointer of local variable not the same as stream 1488 * from dm_state->context. 1489 */ 1490 1491 local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL); 1492 if (!local_dc_state) 1493 return -ENOMEM; 1494 1495 for (i = 0; i < local_dc_state->stream_count; i++) { 1496 struct dc_stream_state *stream = dm_state->context->streams[i]; 1497 int ind = find_crtc_index_in_state_by_stream(state, stream); 1498 1499 if (ind >= 0) { 1500 struct amdgpu_dm_connector *aconnector; 1501 struct drm_connector_state *drm_new_conn_state; 1502 struct dm_connector_state *dm_new_conn_state; 1503 struct dm_crtc_state *dm_old_crtc_state; 1504 1505 aconnector = 1506 amdgpu_dm_find_first_crtc_matching_connector(state, 1507 state->crtcs[ind].ptr); 1508 drm_new_conn_state = 1509 drm_atomic_get_new_connector_state(state, 1510 &aconnector->base); 1511 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 1512 dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state); 1513 1514 local_dc_state->streams[i] = 1515 create_validate_stream_for_sink(aconnector, 1516 &state->crtcs[ind].new_state->mode, 1517 dm_new_conn_state, 1518 dm_old_crtc_state->stream); 1519 if (local_dc_state->streams[i] == NULL) { 1520 ret = -EINVAL; 1521 break; 1522 } 1523 } 1524 } 1525 1526 if (ret != 0) 1527 goto clean_exit; 1528 1529 ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); 1530 if (ret != 0) { 1531 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); 1532 ret = -EINVAL; 1533 goto clean_exit; 1534 } 1535 1536 /* 1537 * compare local_streams -> timing with dm_state->context, 1538 * if the same set crtc_state->mode-change = 0; 1539 */ 1540 for (i = 0; i < local_dc_state->stream_count; i++) { 1541 struct dc_stream_state *stream = dm_state->context->streams[i]; 1542 1543 if (local_dc_state->streams[i] && 1544 dc_is_timing_changed(stream, local_dc_state->streams[i])) { 1545 DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); 1546 } else { 1547 int ind = find_crtc_index_in_state_by_stream(state, stream); 1548 1549 if (ind >= 0) 1550 state->crtcs[ind].new_state->mode_changed = 0; 1551 } 1552 } 1553 clean_exit: 1554 for (i = 0; i < local_dc_state->stream_count; i++) { 1555 struct dc_stream_state *stream = dm_state->context->streams[i]; 1556 1557 if (local_dc_state->streams[i] != stream) 1558 dc_stream_release(local_dc_state->streams[i]); 1559 } 1560 1561 kfree(local_dc_state); 1562 1563 return ret; 1564 } 1565 1566 static unsigned int kbps_from_pbn(unsigned int pbn) 1567 { 1568 unsigned int kbps = pbn; 1569 1570 kbps *= (1000000 / PEAK_FACTOR_X1000); 1571 kbps *= 8; 1572 kbps *= 54; 1573 kbps /= 64; 1574 1575 return kbps; 1576 } 1577 1578 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1579 struct dc_dsc_bw_range *bw_range) 1580 { 1581 struct dc_dsc_policy dsc_policy = {0}; 1582 1583 dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); 1584 dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], 1585 stream->sink->ctx->dc->debug.dsc_min_slice_height_override, 1586 dsc_policy.min_target_bpp * 16, 1587 dsc_policy.max_target_bpp * 16, 1588 &stream->sink->dsc_caps.dsc_dec_caps, 1589 &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range); 1590 1591 return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; 1592 } 1593 1594 enum dc_status dm_dp_mst_is_port_support_mode( 1595 struct amdgpu_dm_connector *aconnector, 1596 struct dc_stream_state *stream) 1597 { 1598 int bpp, pbn, branch_max_throughput_mps = 0; 1599 struct dc_link_settings cur_link_settings; 1600 unsigned int end_to_end_bw_in_kbps = 0; 1601 unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0; 1602 unsigned int max_compressed_bw_in_kbps = 0; 1603 struct dc_dsc_bw_range bw_range = {0}; 1604 uint16_t full_pbn = aconnector->mst_output_port->full_pbn; 1605 1606 /* 1607 * Consider the case with the depth of the mst topology tree is equal or less than 2 1608 * A. When dsc bitstream can be transmitted along the entire path 1609 * 1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND 1610 * 2. dsc passthrough supported at MST branch, or 1611 * 3. dsc decoding supported at leaf MST device 1612 * Use maximum dsc compression as bw constraint 1613 * B. When dsc bitstream cannot be transmitted along the entire path 1614 * Use native bw as bw constraint 1615 */ 1616 if (is_dsc_common_config_possible(stream, &bw_range) && 1617 (aconnector->mst_output_port->passthrough_aux || 1618 aconnector->dsc_aux == &aconnector->mst_output_port->aux)) { 1619 cur_link_settings = stream->link->verified_link_cap; 1620 1621 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 1622 &cur_link_settings); 1623 down_link_bw_in_kbps = kbps_from_pbn(full_pbn); 1624 1625 /* pick the bottleneck */ 1626 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, 1627 down_link_bw_in_kbps); 1628 1629 /* 1630 * use the maximum dsc compression bandwidth as the required 1631 * bandwidth for the mode 1632 */ 1633 max_compressed_bw_in_kbps = bw_range.min_kbps; 1634 1635 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) { 1636 DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n"); 1637 return DC_FAIL_BANDWIDTH_VALIDATE; 1638 } 1639 } else { 1640 /* check if mode could be supported within full_pbn */ 1641 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3; 1642 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4); 1643 if (pbn > full_pbn) 1644 return DC_FAIL_BANDWIDTH_VALIDATE; 1645 } 1646 1647 /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */ 1648 switch (stream->timing.pixel_encoding) { 1649 case PIXEL_ENCODING_RGB: 1650 case PIXEL_ENCODING_YCBCR444: 1651 branch_max_throughput_mps = 1652 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps; 1653 break; 1654 case PIXEL_ENCODING_YCBCR422: 1655 case PIXEL_ENCODING_YCBCR420: 1656 branch_max_throughput_mps = 1657 aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps; 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 if (branch_max_throughput_mps != 0 && 1664 ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) 1665 return DC_FAIL_BANDWIDTH_VALIDATE; 1666 1667 return DC_OK; 1668 } 1669