14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland */ 234562236bSHarry Wentland 244562236bSHarry Wentland #ifndef __AMDGPU_DM_IRQ_H__ 254562236bSHarry Wentland #define __AMDGPU_DM_IRQ_H__ 264562236bSHarry Wentland 274562236bSHarry Wentland #include "irq_types.h" /* DAL irq definitions */ 284562236bSHarry Wentland 294562236bSHarry Wentland /* 304562236bSHarry Wentland * Display Manager IRQ-related interfaces (for use by DAL). 314562236bSHarry Wentland */ 324562236bSHarry Wentland 334562236bSHarry Wentland /** 344562236bSHarry Wentland * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'. 354562236bSHarry Wentland * 364562236bSHarry Wentland * This function should be called exactly once - during DM initialization. 374562236bSHarry Wentland * 384562236bSHarry Wentland * Returns: 394562236bSHarry Wentland * 0 - success 404562236bSHarry Wentland * non-zero - error 414562236bSHarry Wentland */ 42e6375256SAlex Deucher int amdgpu_dm_irq_init(struct amdgpu_device *adev); 434562236bSHarry Wentland 444562236bSHarry Wentland /** 454562236bSHarry Wentland * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'. 464562236bSHarry Wentland * 474562236bSHarry Wentland * This function should be called exactly once - during DM destruction. 484562236bSHarry Wentland * 494562236bSHarry Wentland */ 50e6375256SAlex Deucher void amdgpu_dm_irq_fini(struct amdgpu_device *adev); 514562236bSHarry Wentland 524562236bSHarry Wentland /** 534562236bSHarry Wentland * amdgpu_dm_irq_register_interrupt - register irq handler for Display block. 544562236bSHarry Wentland * 554562236bSHarry Wentland * @adev: AMD DRM device 564562236bSHarry Wentland * @int_params: parameters for the irq 574562236bSHarry Wentland * @ih: pointer to the irq hander function 584562236bSHarry Wentland * @handler_args: arguments which will be passed to ih 594562236bSHarry Wentland * 604562236bSHarry Wentland * Returns: 614562236bSHarry Wentland * IRQ Handler Index on success. 624562236bSHarry Wentland * NULL on failure. 634562236bSHarry Wentland * 644562236bSHarry Wentland * Cannot be called from an interrupt handler. 654562236bSHarry Wentland */ 66e6375256SAlex Deucher void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev, 674562236bSHarry Wentland struct dc_interrupt_params *int_params, 684562236bSHarry Wentland void (*ih)(void *), 694562236bSHarry Wentland void *handler_args); 704562236bSHarry Wentland 714562236bSHarry Wentland /** 724562236bSHarry Wentland * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered 734562236bSHarry Wentland * by amdgpu_dm_irq_register_interrupt(). 744562236bSHarry Wentland * 754562236bSHarry Wentland * @adev: AMD DRM device. 764562236bSHarry Wentland * @ih_index: irq handler index which was returned by 774562236bSHarry Wentland * amdgpu_dm_irq_register_interrupt 784562236bSHarry Wentland */ 79e6375256SAlex Deucher void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, 804562236bSHarry Wentland enum dc_irq_source irq_source, 814562236bSHarry Wentland void *ih_index); 824562236bSHarry Wentland 834562236bSHarry Wentland void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev); 844562236bSHarry Wentland 85*81927e28SJude Shih void amdgpu_dm_outbox_init(struct amdgpu_device *adev); 864562236bSHarry Wentland void amdgpu_dm_hpd_init(struct amdgpu_device *adev); 874562236bSHarry Wentland void amdgpu_dm_hpd_fini(struct amdgpu_device *adev); 884562236bSHarry Wentland 894562236bSHarry Wentland /** 904562236bSHarry Wentland * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend. 914562236bSHarry Wentland * 924562236bSHarry Wentland */ 934562236bSHarry Wentland int amdgpu_dm_irq_suspend(struct amdgpu_device *adev); 944562236bSHarry Wentland 954562236bSHarry Wentland /** 964562236bSHarry Wentland * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume. 974562236bSHarry Wentland * amdgpu_dm_irq_resume - enable ASIC interrupt during resume. 984562236bSHarry Wentland * 994562236bSHarry Wentland */ 1004562236bSHarry Wentland int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev); 1019faa4237SAndrey Grodzovsky int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev); 1024562236bSHarry Wentland 1034562236bSHarry Wentland #endif /* __AMDGPU_DM_IRQ_H__ */ 104