1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string.h> 27 #include <linux/acpi.h> 28 #include <linux/i2c.h> 29 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/amdgpu_drm.h> 33 #include <drm/drm_edid.h> 34 35 #include "dm_services.h" 36 #include "amdgpu.h" 37 #include "dc.h" 38 #include "amdgpu_dm.h" 39 #include "amdgpu_dm_irq.h" 40 #include "amdgpu_dm_mst_types.h" 41 42 #include "dm_helpers.h" 43 #include "ddc_service_types.h" 44 45 /* dm_helpers_parse_edid_caps 46 * 47 * Parse edid caps 48 * 49 * @edid: [in] pointer to edid 50 * edid_caps: [in] pointer to edid caps 51 * @return 52 * void 53 * */ 54 enum dc_edid_status dm_helpers_parse_edid_caps( 55 struct dc_link *link, 56 const struct dc_edid *edid, 57 struct dc_edid_caps *edid_caps) 58 { 59 struct amdgpu_dm_connector *aconnector = link->priv; 60 struct drm_connector *connector = &aconnector->base; 61 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL; 62 struct cea_sad *sads; 63 int sad_count = -1; 64 int sadb_count = -1; 65 int i = 0; 66 uint8_t *sadb = NULL; 67 68 enum dc_edid_status result = EDID_OK; 69 70 if (!edid_caps || !edid) 71 return EDID_BAD_INPUT; 72 73 if (!drm_edid_is_valid(edid_buf)) 74 result = EDID_BAD_CHECKSUM; 75 76 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] | 77 ((uint16_t) edid_buf->mfg_id[1])<<8; 78 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] | 79 ((uint16_t) edid_buf->prod_code[1])<<8; 80 edid_caps->serial_number = edid_buf->serial; 81 edid_caps->manufacture_week = edid_buf->mfg_week; 82 edid_caps->manufacture_year = edid_buf->mfg_year; 83 84 drm_edid_get_monitor_name(edid_buf, 85 edid_caps->display_name, 86 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 87 88 edid_caps->edid_hdmi = connector->display_info.is_hdmi; 89 90 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads); 91 if (sad_count <= 0) 92 return result; 93 94 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT; 95 for (i = 0; i < edid_caps->audio_mode_count; ++i) { 96 struct cea_sad *sad = &sads[i]; 97 98 edid_caps->audio_modes[i].format_code = sad->format; 99 edid_caps->audio_modes[i].channel_count = sad->channels + 1; 100 edid_caps->audio_modes[i].sample_rate = sad->freq; 101 edid_caps->audio_modes[i].sample_size = sad->byte2; 102 } 103 104 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb); 105 106 if (sadb_count < 0) { 107 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count); 108 sadb_count = 0; 109 } 110 111 if (sadb_count) 112 edid_caps->speaker_flags = sadb[0]; 113 else 114 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION; 115 116 kfree(sads); 117 kfree(sadb); 118 119 return result; 120 } 121 122 static void 123 fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state, 124 struct amdgpu_dm_connector *aconnector, 125 struct dc_dp_mst_stream_allocation_table *table) 126 { 127 struct dc_dp_mst_stream_allocation_table new_table = { 0 }; 128 struct dc_dp_mst_stream_allocation *sa; 129 struct drm_dp_mst_atomic_payload *payload; 130 131 /* Fill payload info*/ 132 list_for_each_entry(payload, &mst_state->payloads, next) { 133 if (payload->delete) 134 continue; 135 136 sa = &new_table.stream_allocations[new_table.stream_count]; 137 sa->slot_count = payload->time_slots; 138 sa->vcp_id = payload->vcpi; 139 new_table.stream_count++; 140 } 141 142 /* Overwrite the old table */ 143 *table = new_table; 144 } 145 146 void dm_helpers_dp_update_branch_info( 147 struct dc_context *ctx, 148 const struct dc_link *link) 149 {} 150 151 /* 152 * Writes payload allocation table in immediate downstream device. 153 */ 154 bool dm_helpers_dp_mst_write_payload_allocation_table( 155 struct dc_context *ctx, 156 const struct dc_stream_state *stream, 157 struct dc_dp_mst_stream_allocation_table *proposed_table, 158 bool enable) 159 { 160 struct amdgpu_dm_connector *aconnector; 161 struct drm_dp_mst_topology_state *mst_state; 162 struct drm_dp_mst_atomic_payload *payload; 163 struct drm_dp_mst_topology_mgr *mst_mgr; 164 165 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 166 /* Accessing the connector state is required for vcpi_slots allocation 167 * and directly relies on behaviour in commit check 168 * that blocks before commit guaranteeing that the state 169 * is not gonna be swapped while still in use in commit tail */ 170 171 if (!aconnector || !aconnector->mst_port) 172 return false; 173 174 mst_mgr = &aconnector->mst_port->mst_mgr; 175 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 176 177 /* It's OK for this to fail */ 178 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); 179 if (enable) 180 drm_dp_add_payload_part1(mst_mgr, mst_state, payload); 181 else 182 drm_dp_remove_payload(mst_mgr, mst_state, payload); 183 184 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or 185 * AUX message. The sequence is slot 1-63 allocated sequence for each 186 * stream. AMD ASIC stream slot allocation should follow the same 187 * sequence. copy DRM MST allocation to dc */ 188 fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table); 189 190 return true; 191 } 192 193 /* 194 * poll pending down reply 195 */ 196 void dm_helpers_dp_mst_poll_pending_down_reply( 197 struct dc_context *ctx, 198 const struct dc_link *link) 199 {} 200 201 /* 202 * Clear payload allocation table before enable MST DP link. 203 */ 204 void dm_helpers_dp_mst_clear_payload_allocation_table( 205 struct dc_context *ctx, 206 const struct dc_link *link) 207 {} 208 209 /* 210 * Polls for ACT (allocation change trigger) handled and sends 211 * ALLOCATE_PAYLOAD message. 212 */ 213 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger( 214 struct dc_context *ctx, 215 const struct dc_stream_state *stream) 216 { 217 struct amdgpu_dm_connector *aconnector; 218 struct drm_dp_mst_topology_mgr *mst_mgr; 219 int ret; 220 221 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 222 223 if (!aconnector || !aconnector->mst_port) 224 return ACT_FAILED; 225 226 mst_mgr = &aconnector->mst_port->mst_mgr; 227 228 if (!mst_mgr->mst_state) 229 return ACT_FAILED; 230 231 ret = drm_dp_check_act_status(mst_mgr); 232 233 if (ret) 234 return ACT_FAILED; 235 236 return ACT_SUCCESS; 237 } 238 239 bool dm_helpers_dp_mst_send_payload_allocation( 240 struct dc_context *ctx, 241 const struct dc_stream_state *stream, 242 bool enable) 243 { 244 struct amdgpu_dm_connector *aconnector; 245 struct drm_dp_mst_topology_state *mst_state; 246 struct drm_dp_mst_topology_mgr *mst_mgr; 247 struct drm_dp_mst_atomic_payload *payload; 248 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; 249 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 250 251 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 252 253 if (!aconnector || !aconnector->mst_port) 254 return false; 255 256 mst_mgr = &aconnector->mst_port->mst_mgr; 257 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); 258 259 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port); 260 if (!enable) { 261 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; 262 clr_flag = MST_ALLOCATE_NEW_PAYLOAD; 263 } 264 265 if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) { 266 amdgpu_dm_set_mst_status(&aconnector->mst_status, 267 set_flag, false); 268 } else { 269 amdgpu_dm_set_mst_status(&aconnector->mst_status, 270 set_flag, true); 271 amdgpu_dm_set_mst_status(&aconnector->mst_status, 272 clr_flag, false); 273 } 274 275 return true; 276 } 277 278 void dm_dtn_log_begin(struct dc_context *ctx, 279 struct dc_log_buffer_ctx *log_ctx) 280 { 281 static const char msg[] = "[dtn begin]\n"; 282 283 if (!log_ctx) { 284 pr_info("%s", msg); 285 return; 286 } 287 288 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 289 } 290 291 __printf(3, 4) 292 void dm_dtn_log_append_v(struct dc_context *ctx, 293 struct dc_log_buffer_ctx *log_ctx, 294 const char *msg, ...) 295 { 296 va_list args; 297 size_t total; 298 int n; 299 300 if (!log_ctx) { 301 /* No context, redirect to dmesg. */ 302 struct va_format vaf; 303 304 vaf.fmt = msg; 305 vaf.va = &args; 306 307 va_start(args, msg); 308 pr_info("%pV", &vaf); 309 va_end(args); 310 311 return; 312 } 313 314 /* Measure the output. */ 315 va_start(args, msg); 316 n = vsnprintf(NULL, 0, msg, args); 317 va_end(args); 318 319 if (n <= 0) 320 return; 321 322 /* Reallocate the string buffer as needed. */ 323 total = log_ctx->pos + n + 1; 324 325 if (total > log_ctx->size) { 326 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL); 327 328 if (buf) { 329 memcpy(buf, log_ctx->buf, log_ctx->pos); 330 kfree(log_ctx->buf); 331 332 log_ctx->buf = buf; 333 log_ctx->size = total; 334 } 335 } 336 337 if (!log_ctx->buf) 338 return; 339 340 /* Write the formatted string to the log buffer. */ 341 va_start(args, msg); 342 n = vscnprintf( 343 log_ctx->buf + log_ctx->pos, 344 log_ctx->size - log_ctx->pos, 345 msg, 346 args); 347 va_end(args); 348 349 if (n > 0) 350 log_ctx->pos += n; 351 } 352 353 void dm_dtn_log_end(struct dc_context *ctx, 354 struct dc_log_buffer_ctx *log_ctx) 355 { 356 static const char msg[] = "[dtn end]\n"; 357 358 if (!log_ctx) { 359 pr_info("%s", msg); 360 return; 361 } 362 363 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg); 364 } 365 366 bool dm_helpers_dp_mst_start_top_mgr( 367 struct dc_context *ctx, 368 const struct dc_link *link, 369 bool boot) 370 { 371 struct amdgpu_dm_connector *aconnector = link->priv; 372 373 if (!aconnector) { 374 DRM_ERROR("Failed to find connector for link!"); 375 return false; 376 } 377 378 if (boot) { 379 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n", 380 aconnector, aconnector->base.base.id); 381 return true; 382 } 383 384 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", 385 aconnector, aconnector->base.base.id); 386 387 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0); 388 } 389 390 bool dm_helpers_dp_mst_stop_top_mgr( 391 struct dc_context *ctx, 392 struct dc_link *link) 393 { 394 struct amdgpu_dm_connector *aconnector = link->priv; 395 396 if (!aconnector) { 397 DRM_ERROR("Failed to find connector for link!"); 398 return false; 399 } 400 401 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n", 402 aconnector, aconnector->base.base.id); 403 404 if (aconnector->mst_mgr.mst_state == true) { 405 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false); 406 link->cur_link_settings.lane_count = 0; 407 } 408 409 return false; 410 } 411 412 bool dm_helpers_dp_read_dpcd( 413 struct dc_context *ctx, 414 const struct dc_link *link, 415 uint32_t address, 416 uint8_t *data, 417 uint32_t size) 418 { 419 420 struct amdgpu_dm_connector *aconnector = link->priv; 421 422 if (!aconnector) { 423 DC_LOG_DC("Failed to find connector for link!\n"); 424 return false; 425 } 426 427 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address, 428 data, size) > 0; 429 } 430 431 bool dm_helpers_dp_write_dpcd( 432 struct dc_context *ctx, 433 const struct dc_link *link, 434 uint32_t address, 435 const uint8_t *data, 436 uint32_t size) 437 { 438 struct amdgpu_dm_connector *aconnector = link->priv; 439 440 if (!aconnector) { 441 DRM_ERROR("Failed to find connector for link!"); 442 return false; 443 } 444 445 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux, 446 address, (uint8_t *)data, size) > 0; 447 } 448 449 bool dm_helpers_submit_i2c( 450 struct dc_context *ctx, 451 const struct dc_link *link, 452 struct i2c_command *cmd) 453 { 454 struct amdgpu_dm_connector *aconnector = link->priv; 455 struct i2c_msg *msgs; 456 int i = 0; 457 int num = cmd->number_of_payloads; 458 bool result; 459 460 if (!aconnector) { 461 DRM_ERROR("Failed to find connector for link!"); 462 return false; 463 } 464 465 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL); 466 467 if (!msgs) 468 return false; 469 470 for (i = 0; i < num; i++) { 471 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD; 472 msgs[i].addr = cmd->payloads[i].address; 473 msgs[i].len = cmd->payloads[i].length; 474 msgs[i].buf = cmd->payloads[i].data; 475 } 476 477 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num; 478 479 kfree(msgs); 480 481 return result; 482 } 483 484 #if defined(CONFIG_DRM_AMD_DC_DCN) 485 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, 486 bool is_write_cmd, 487 unsigned char cmd, 488 unsigned int length, 489 unsigned int offset, 490 unsigned char *data) 491 { 492 bool success = false; 493 unsigned char rc_data[16] = {0}; 494 unsigned char rc_offset[4] = {0}; 495 unsigned char rc_length[2] = {0}; 496 unsigned char rc_cmd = 0; 497 unsigned char rc_result = 0xFF; 498 unsigned char i = 0; 499 int ret; 500 501 if (is_write_cmd) { 502 // write rc data 503 memmove(rc_data, data, length); 504 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data)); 505 } 506 507 // write rc offset 508 rc_offset[0] = (unsigned char) offset & 0xFF; 509 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF; 510 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF; 511 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF; 512 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset)); 513 514 // write rc length 515 rc_length[0] = (unsigned char) length & 0xFF; 516 rc_length[1] = (unsigned char) (length >> 8) & 0xFF; 517 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length)); 518 519 // write rc cmd 520 rc_cmd = cmd | 0x80; 521 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 522 523 if (ret < 0) { 524 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret); 525 return false; 526 } 527 528 // poll until active is 0 529 for (i = 0; i < 10; i++) { 530 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd)); 531 if (rc_cmd == cmd) 532 // active is 0 533 break; 534 msleep(10); 535 } 536 537 // read rc result 538 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result)); 539 success = (rc_result == 0); 540 541 if (success && !is_write_cmd) { 542 // read rc data 543 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); 544 } 545 546 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success); 547 548 return success; 549 } 550 551 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) 552 { 553 unsigned char data[16] = {0}; 554 555 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n"); 556 557 // Step 2 558 data[0] = 'P'; 559 data[1] = 'R'; 560 data[2] = 'I'; 561 data[3] = 'U'; 562 data[4] = 'S'; 563 564 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data)) 565 return; 566 567 // Step 3 and 4 568 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 569 return; 570 571 data[0] &= (~(1 << 1)); // set bit 1 to 0 572 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 573 return; 574 575 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 576 return; 577 578 data[0] &= (~(1 << 1)); // set bit 1 to 0 579 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data)) 580 return; 581 582 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 583 return; 584 585 data[0] &= (~(1 << 1)); // set bit 1 to 0 586 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 587 return; 588 589 // Step 3 and 5 590 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data)) 591 return; 592 593 data[0] |= (1 << 1); // set bit 1 to 1 594 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data)) 595 return; 596 597 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data)) 598 return; 599 600 data[0] |= (1 << 1); // set bit 1 to 1 601 return; 602 603 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data)) 604 return; 605 606 data[0] |= (1 << 1); // set bit 1 to 1 607 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data)) 608 return; 609 610 // Step 6 611 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) 612 return; 613 614 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n"); 615 } 616 617 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( 618 struct drm_dp_aux *aux, 619 const struct dc_stream_state *stream, 620 bool enable) 621 { 622 uint8_t ret = 0; 623 624 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n"); 625 626 if (enable) { 627 /* When DSC is enabled on previous boot and reboot with the hub, 628 * there is a chance that Synaptics hub gets stuck during reboot sequence. 629 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream 630 */ 631 if (!stream->link->link_status.link_active && 632 memcmp(stream->link->dpcd_caps.branch_dev_name, 633 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0) 634 apply_synaptics_fifo_reset_wa(aux); 635 636 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 637 DRM_INFO("Send DSC enable to synaptics\n"); 638 639 } else { 640 /* Synaptics hub not support virtual dpcd, 641 * external monitor occur garbage while disable DSC, 642 * Disable DSC only when entire link status turn to false, 643 */ 644 if (!stream->link->link_status.link_active) { 645 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); 646 DRM_INFO("Send DSC disable to synaptics\n"); 647 } 648 } 649 650 return ret; 651 } 652 #endif 653 654 bool dm_helpers_dp_write_dsc_enable( 655 struct dc_context *ctx, 656 const struct dc_stream_state *stream, 657 bool enable) 658 { 659 static const uint8_t DSC_DISABLE; 660 static const uint8_t DSC_DECODING = 0x01; 661 static const uint8_t DSC_PASSTHROUGH = 0x02; 662 663 struct amdgpu_dm_connector *aconnector; 664 struct drm_dp_mst_port *port; 665 uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; 666 uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; 667 uint8_t ret = 0; 668 669 if (!stream) 670 return false; 671 672 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 673 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 674 675 if (!aconnector->dsc_aux) 676 return false; 677 678 #if defined(CONFIG_DRM_AMD_DC_DCN) 679 // apply w/a to synaptics 680 if (needs_dsc_aux_workaround(aconnector->dc_link) && 681 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3) 682 return write_dsc_enable_synaptics_non_virtual_dpcd_mst( 683 aconnector->dsc_aux, stream, enable_dsc); 684 #endif 685 686 port = aconnector->port; 687 688 if (enable) { 689 if (port->passthrough_aux) { 690 ret = drm_dp_dpcd_write(port->passthrough_aux, 691 DP_DSC_ENABLE, 692 &enable_passthrough, 1); 693 DC_LOG_DC("Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", 694 ret); 695 } 696 697 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 698 DP_DSC_ENABLE, &enable_dsc, 1); 699 DC_LOG_DC("Sent DSC decoding enable to %s port, ret = %u\n", 700 (port->passthrough_aux) ? "remote RX" : 701 "virtual dpcd", 702 ret); 703 } else { 704 ret = drm_dp_dpcd_write(aconnector->dsc_aux, 705 DP_DSC_ENABLE, &enable_dsc, 1); 706 DC_LOG_DC("Sent DSC decoding disable to %s port, ret = %u\n", 707 (port->passthrough_aux) ? "remote RX" : 708 "virtual dpcd", 709 ret); 710 711 if (port->passthrough_aux) { 712 ret = drm_dp_dpcd_write(port->passthrough_aux, 713 DP_DSC_ENABLE, 714 &enable_passthrough, 1); 715 DC_LOG_DC("Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", 716 ret); 717 } 718 } 719 } 720 721 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { 722 #if defined(CONFIG_DRM_AMD_DC_DCN) 723 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 724 #endif 725 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 726 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); 727 #if defined(CONFIG_DRM_AMD_DC_DCN) 728 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 729 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); 730 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); 731 } 732 #endif 733 } 734 735 return ret; 736 } 737 738 bool dm_helpers_is_dp_sink_present(struct dc_link *link) 739 { 740 bool dp_sink_present; 741 struct amdgpu_dm_connector *aconnector = link->priv; 742 743 if (!aconnector) { 744 BUG_ON("Failed to find connector for link!"); 745 return true; 746 } 747 748 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex); 749 dp_sink_present = dc_link_is_dp_sink_present(link); 750 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex); 751 return dp_sink_present; 752 } 753 754 enum dc_edid_status dm_helpers_read_local_edid( 755 struct dc_context *ctx, 756 struct dc_link *link, 757 struct dc_sink *sink) 758 { 759 struct amdgpu_dm_connector *aconnector = link->priv; 760 struct drm_connector *connector = &aconnector->base; 761 struct i2c_adapter *ddc; 762 int retry = 3; 763 enum dc_edid_status edid_status; 764 struct edid *edid; 765 766 if (link->aux_mode) 767 ddc = &aconnector->dm_dp_aux.aux.ddc; 768 else 769 ddc = &aconnector->i2c->base; 770 771 /* some dongles read edid incorrectly the first time, 772 * do check sum and retry to make sure read correct edid. 773 */ 774 do { 775 776 edid = drm_get_edid(&aconnector->base, ddc); 777 778 /* DP Compliance Test 4.2.2.6 */ 779 if (link->aux_mode && connector->edid_corrupt) 780 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); 781 782 if (!edid && connector->edid_corrupt) { 783 connector->edid_corrupt = false; 784 return EDID_BAD_CHECKSUM; 785 } 786 787 if (!edid) 788 return EDID_NO_RESPONSE; 789 790 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1); 791 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); 792 793 /* We don't need the original edid anymore */ 794 kfree(edid); 795 796 edid_status = dm_helpers_parse_edid_caps( 797 link, 798 &sink->dc_edid, 799 &sink->edid_caps); 800 801 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0); 802 803 if (edid_status != EDID_OK) 804 DRM_ERROR("EDID err: %d, on connector: %s", 805 edid_status, 806 aconnector->base.name); 807 808 /* DP Compliance Test 4.2.2.3 */ 809 if (link->aux_mode) 810 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]); 811 812 return edid_status; 813 } 814 int dm_helper_dmub_aux_transfer_sync( 815 struct dc_context *ctx, 816 const struct dc_link *link, 817 struct aux_payload *payload, 818 enum aux_return_code_type *operation_result) 819 { 820 return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, 821 operation_result); 822 } 823 824 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx, 825 const struct dc_link *link, 826 struct set_config_cmd_payload *payload, 827 enum set_config_status *operation_result) 828 { 829 return amdgpu_dm_process_dmub_set_config_sync(ctx, link->link_index, payload, 830 operation_result); 831 } 832 833 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) 834 { 835 /* TODO: something */ 836 } 837 838 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) 839 { 840 // TODO: 841 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); 842 } 843 844 void dm_helpers_init_panel_settings( 845 struct dc_context *ctx, 846 struct dc_panel_config *panel_config, 847 struct dc_sink *sink) 848 { 849 // Extra Panel Power Sequence 850 panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms; 851 panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms; 852 panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off; 853 panel_config->pps.extra_post_t7_ms = 0; 854 panel_config->pps.extra_pre_t11_ms = 0; 855 panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms; 856 panel_config->pps.extra_post_OUI_ms = 0; 857 // Feature DSC 858 panel_config->dsc.disable_dsc_edp = false; 859 panel_config->dsc.force_dsc_edp_policy = 0; 860 } 861 862 void dm_helpers_override_panel_settings( 863 struct dc_context *ctx, 864 struct dc_panel_config *panel_config) 865 { 866 // Feature DSC 867 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) { 868 panel_config->dsc.disable_dsc_edp = true; 869 } 870 } 871 872 void *dm_helpers_allocate_gpu_mem( 873 struct dc_context *ctx, 874 enum dc_gpu_mem_alloc_type type, 875 size_t size, 876 long long *addr) 877 { 878 struct amdgpu_device *adev = ctx->driver_context; 879 struct dal_allocation *da; 880 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 881 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 882 int ret; 883 884 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 885 if (!da) 886 return NULL; 887 888 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 889 domain, &da->bo, 890 &da->gpu_addr, &da->cpu_ptr); 891 892 *addr = da->gpu_addr; 893 894 if (ret) { 895 kfree(da); 896 return NULL; 897 } 898 899 /* add da to list in dm */ 900 list_add(&da->list, &adev->dm.da_list); 901 902 return da->cpu_ptr; 903 } 904 905 void dm_helpers_free_gpu_mem( 906 struct dc_context *ctx, 907 enum dc_gpu_mem_alloc_type type, 908 void *pvMem) 909 { 910 struct amdgpu_device *adev = ctx->driver_context; 911 struct dal_allocation *da; 912 913 /* walk the da list in DM */ 914 list_for_each_entry(da, &adev->dm.da_list, list) { 915 if (pvMem == da->cpu_ptr) { 916 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 917 list_del(&da->list); 918 kfree(da); 919 break; 920 } 921 } 922 } 923 924 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) 925 { 926 enum dc_irq_source irq_source; 927 bool ret; 928 929 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX; 930 931 ret = dc_interrupt_set(ctx->dc, irq_source, enable); 932 933 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n", 934 enable ? "en" : "dis", ret); 935 return ret; 936 } 937 938 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream) 939 { 940 /* TODO: virtual DPCD */ 941 struct dc_link *link = stream->link; 942 union down_spread_ctrl old_downspread; 943 union down_spread_ctrl new_downspread; 944 945 if (link->aux_access_disabled) 946 return; 947 948 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 949 &old_downspread.raw, 950 sizeof(old_downspread))) 951 return; 952 953 new_downspread.raw = old_downspread.raw; 954 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 955 (stream->ignore_msa_timing_param) ? 1 : 0; 956 957 if (new_downspread.raw != old_downspread.raw) 958 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL, 959 &new_downspread.raw, 960 sizeof(new_downspread)); 961 } 962 963 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 964 { 965 // TODO 966 } 967 968 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable) 969 { 970 /* TODO: add periodic detection implementation */ 971 } 972 973 void dm_helpers_dp_mst_update_branch_bandwidth( 974 struct dc_context *ctx, 975 struct dc_link *link) 976 { 977 // TODO 978 } 979 980