1a193ed20SBhawanpreet Lakha /* 2a193ed20SBhawanpreet Lakha * Copyright 2019 Advanced Micro Devices, Inc. 3a193ed20SBhawanpreet Lakha * 4a193ed20SBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5a193ed20SBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6a193ed20SBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7a193ed20SBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a193ed20SBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9a193ed20SBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10a193ed20SBhawanpreet Lakha * 11a193ed20SBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12a193ed20SBhawanpreet Lakha * all copies or substantial portions of the Software. 13a193ed20SBhawanpreet Lakha * 14a193ed20SBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a193ed20SBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a193ed20SBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a193ed20SBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a193ed20SBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a193ed20SBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a193ed20SBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21a193ed20SBhawanpreet Lakha * 22a193ed20SBhawanpreet Lakha * Authors: AMD 23a193ed20SBhawanpreet Lakha * 24a193ed20SBhawanpreet Lakha */ 25a193ed20SBhawanpreet Lakha 26a193ed20SBhawanpreet Lakha #ifndef AMDGPU_DM_AMDGPU_DM_HDCP_H_ 27a193ed20SBhawanpreet Lakha #define AMDGPU_DM_AMDGPU_DM_HDCP_H_ 28a193ed20SBhawanpreet Lakha 29a193ed20SBhawanpreet Lakha #include "mod_hdcp.h" 30a193ed20SBhawanpreet Lakha #include "hdcp.h" 31a193ed20SBhawanpreet Lakha #include "dc.h" 32a193ed20SBhawanpreet Lakha #include "dm_cp_psp.h" 33e50dc171SBhawanpreet Lakha #include "amdgpu.h" 34a193ed20SBhawanpreet Lakha 35a193ed20SBhawanpreet Lakha struct mod_hdcp; 36a193ed20SBhawanpreet Lakha struct mod_hdcp_link; 37a193ed20SBhawanpreet Lakha struct mod_hdcp_display; 38a193ed20SBhawanpreet Lakha struct cp_psp; 39a193ed20SBhawanpreet Lakha 40a193ed20SBhawanpreet Lakha struct hdcp_workqueue { 41a193ed20SBhawanpreet Lakha struct work_struct cpirq_work; 42da3fd7acSBhawanpreet Lakha struct work_struct property_update_work; 43a193ed20SBhawanpreet Lakha struct delayed_work callback_dwork; 44a193ed20SBhawanpreet Lakha struct delayed_work watchdog_timer_dwork; 45da3fd7acSBhawanpreet Lakha struct delayed_work property_validate_dwork; 46*aa9fdd5dShersen wu struct amdgpu_dm_connector *aconnector[AMDGPU_DM_MAX_DISPLAY_INDEX]; 47a193ed20SBhawanpreet Lakha struct mutex mutex; 48a193ed20SBhawanpreet Lakha 49a193ed20SBhawanpreet Lakha struct mod_hdcp hdcp; 50a193ed20SBhawanpreet Lakha struct mod_hdcp_output output; 51a193ed20SBhawanpreet Lakha struct mod_hdcp_display display; 52a193ed20SBhawanpreet Lakha struct mod_hdcp_link link; 53a193ed20SBhawanpreet Lakha 54*aa9fdd5dShersen wu enum mod_hdcp_encryption_status encryption_status[AMDGPU_DM_MAX_DISPLAY_INDEX]; 5582986fd6Shersen wu /* when display is unplugged from mst hub, connctor will be 5682986fd6Shersen wu * destroyed within dm_dp_mst_connector_destroy. connector 5782986fd6Shersen wu * hdcp perperties, like type, undesired, desired, enabled, 5882986fd6Shersen wu * will be lost. So, save hdcp properties into hdcp_work within 5982986fd6Shersen wu * amdgpu_dm_atomic_commit_tail. if the same display is 6082986fd6Shersen wu * plugged back with same display index, its hdcp properties 6182986fd6Shersen wu * will be retrieved from hdcp_work within dm_dp_mst_get_modes 6282986fd6Shersen wu */ 6382986fd6Shersen wu /* un-desired, desired, enabled */ 6482986fd6Shersen wu unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX]; 6582986fd6Shersen wu /* hdcp1.x, hdcp2.x */ 6682986fd6Shersen wu unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX]; 6782986fd6Shersen wu 68a193ed20SBhawanpreet Lakha uint8_t max_link; 699037246bSBhawanpreet Lakha 709037246bSBhawanpreet Lakha uint8_t *srm; 719037246bSBhawanpreet Lakha uint8_t *srm_temp; 729037246bSBhawanpreet Lakha uint32_t srm_version; 739037246bSBhawanpreet Lakha uint32_t srm_size; 749037246bSBhawanpreet Lakha struct bin_attribute attr; 75a193ed20SBhawanpreet Lakha }; 76a193ed20SBhawanpreet Lakha 77b1abe558SBhawanpreet Lakha void hdcp_update_display(struct hdcp_workqueue *hdcp_work, 78b1abe558SBhawanpreet Lakha unsigned int link_index, 79b1abe558SBhawanpreet Lakha struct amdgpu_dm_connector *aconnector, 8023eb4191SBhawanpreet Lakha uint8_t content_type, 81b1abe558SBhawanpreet Lakha bool enable_encryption); 82b1abe558SBhawanpreet Lakha 83a193ed20SBhawanpreet Lakha void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index); 84a193ed20SBhawanpreet Lakha void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index); 85e96b1b29SNirmoy Das void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *work); 86a193ed20SBhawanpreet Lakha 87e50dc171SBhawanpreet Lakha struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc); 88a193ed20SBhawanpreet Lakha 89a193ed20SBhawanpreet Lakha #endif /* AMDGPU_DM_AMDGPU_DM_HDCP_H_ */ 90