1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42 #include "amdgpu_dm_psr.h" 43 #endif 44 45 struct dmub_debugfs_trace_header { 46 uint32_t entry_count; 47 uint32_t reserved[3]; 48 }; 49 50 struct dmub_debugfs_trace_entry { 51 uint32_t trace_code; 52 uint32_t tick_count; 53 uint32_t param0; 54 uint32_t param1; 55 }; 56 57 static const char *const mst_progress_status[] = { 58 "probe", 59 "remote_edid", 60 "allocate_new_payload", 61 "clear_allocated_payload", 62 }; 63 64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 65 * 66 * Function takes in attributes passed to debugfs write entry 67 * and writes into param array. 68 * The user passes max_param_num to identify maximum number of 69 * parameters that could be parsed. 70 * 71 */ 72 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 73 long *param, const char __user *buf, 74 int max_param_num, 75 uint8_t *param_nums) 76 { 77 char *wr_buf_ptr = NULL; 78 uint32_t wr_buf_count = 0; 79 int r; 80 char *sub_str = NULL; 81 const char delimiter[3] = {' ', '\n', '\0'}; 82 uint8_t param_index = 0; 83 84 *param_nums = 0; 85 86 wr_buf_ptr = wr_buf; 87 88 /* r is bytes not be copied */ 89 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 90 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 91 return -EFAULT; 92 } 93 94 /* check number of parameters. isspace could not differ space and \n */ 95 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 96 /* skip space*/ 97 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 98 wr_buf_ptr++; 99 wr_buf_count++; 100 } 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 105 /* skip non-space*/ 106 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 107 wr_buf_ptr++; 108 wr_buf_count++; 109 } 110 111 (*param_nums)++; 112 113 if (wr_buf_count == wr_buf_size) 114 break; 115 } 116 117 if (*param_nums > max_param_num) 118 *param_nums = max_param_num; 119 120 wr_buf_ptr = wr_buf; /* reset buf pointer */ 121 wr_buf_count = 0; /* number of char already checked */ 122 123 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 124 wr_buf_ptr++; 125 wr_buf_count++; 126 } 127 128 while (param_index < *param_nums) { 129 /* after strsep, wr_buf_ptr will be moved to after space */ 130 sub_str = strsep(&wr_buf_ptr, delimiter); 131 132 r = kstrtol(sub_str, 16, &(param[param_index])); 133 134 if (r) 135 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 136 137 param_index++; 138 } 139 140 return 0; 141 } 142 143 /* function description 144 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 145 * 146 * valid lane count value: 1, 2, 4 147 * valid link rate value: 148 * 06h = 1.62Gbps per lane 149 * 0Ah = 2.7Gbps per lane 150 * 0Ch = 3.24Gbps per lane 151 * 14h = 5.4Gbps per lane 152 * 1Eh = 8.1Gbps per lane 153 * 154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 155 * 156 * --- to get dp configuration 157 * 158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 159 * 160 * It will list current, verified, reported, preferred dp configuration. 161 * current -- for current video mode 162 * verified --- maximum configuration which pass link training 163 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 164 * preferred --- user force settings 165 * 166 * --- set (or force) dp configuration 167 * 168 * echo <lane_count> <link_rate> > link_settings 169 * 170 * for example, to force to 2 lane, 2.7GHz, 171 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 172 * 173 * spread_spectrum could not be changed dynamically. 174 * 175 * in case invalid lane count, link rate are force, no hw programming will be 176 * done. please check link settings after force operation to see if HW get 177 * programming. 178 * 179 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 180 * 181 * check current and preferred settings. 182 * 183 */ 184 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 185 size_t size, loff_t *pos) 186 { 187 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 188 struct dc_link *link = connector->dc_link; 189 char *rd_buf = NULL; 190 char *rd_buf_ptr = NULL; 191 const uint32_t rd_buf_size = 100; 192 uint32_t result = 0; 193 uint8_t str_len = 0; 194 int r; 195 196 if (*pos & 3 || size & 3) 197 return -EINVAL; 198 199 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 200 if (!rd_buf) 201 return 0; 202 203 rd_buf_ptr = rd_buf; 204 205 str_len = strlen("Current: %d 0x%x %d "); 206 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 207 link->cur_link_settings.lane_count, 208 link->cur_link_settings.link_rate, 209 link->cur_link_settings.link_spread); 210 rd_buf_ptr += str_len; 211 212 str_len = strlen("Verified: %d 0x%x %d "); 213 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 214 link->verified_link_cap.lane_count, 215 link->verified_link_cap.link_rate, 216 link->verified_link_cap.link_spread); 217 rd_buf_ptr += str_len; 218 219 str_len = strlen("Reported: %d 0x%x %d "); 220 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 221 link->reported_link_cap.lane_count, 222 link->reported_link_cap.link_rate, 223 link->reported_link_cap.link_spread); 224 rd_buf_ptr += str_len; 225 226 str_len = strlen("Preferred: %d 0x%x %d "); 227 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 228 link->preferred_link_setting.lane_count, 229 link->preferred_link_setting.link_rate, 230 link->preferred_link_setting.link_spread); 231 232 while (size) { 233 if (*pos >= rd_buf_size) 234 break; 235 236 r = put_user(*(rd_buf + result), buf); 237 if (r) { 238 kfree(rd_buf); 239 return r; /* r = -EFAULT */ 240 } 241 242 buf += 1; 243 size -= 1; 244 *pos += 1; 245 result += 1; 246 } 247 248 kfree(rd_buf); 249 return result; 250 } 251 252 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 253 size_t size, loff_t *pos) 254 { 255 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 256 struct dc_link *link = connector->dc_link; 257 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 258 struct dc *dc = (struct dc *)link->dc; 259 struct dc_link_settings prefer_link_settings; 260 char *wr_buf = NULL; 261 const uint32_t wr_buf_size = 40; 262 /* 0: lane_count; 1: link_rate */ 263 int max_param_num = 2; 264 uint8_t param_nums = 0; 265 long param[2]; 266 bool valid_input = true; 267 268 if (size == 0) 269 return -EINVAL; 270 271 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 272 if (!wr_buf) 273 return -ENOSPC; 274 275 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 276 (long *)param, buf, 277 max_param_num, 278 ¶m_nums)) { 279 kfree(wr_buf); 280 return -EINVAL; 281 } 282 283 if (param_nums <= 0) { 284 kfree(wr_buf); 285 DRM_DEBUG_DRIVER("user data not be read\n"); 286 return -EINVAL; 287 } 288 289 switch (param[0]) { 290 case LANE_COUNT_ONE: 291 case LANE_COUNT_TWO: 292 case LANE_COUNT_FOUR: 293 break; 294 default: 295 valid_input = false; 296 break; 297 } 298 299 switch (param[1]) { 300 case LINK_RATE_LOW: 301 case LINK_RATE_HIGH: 302 case LINK_RATE_RBR2: 303 case LINK_RATE_HIGH2: 304 case LINK_RATE_HIGH3: 305 case LINK_RATE_UHBR10: 306 case LINK_RATE_UHBR13_5: 307 case LINK_RATE_UHBR20: 308 break; 309 default: 310 valid_input = false; 311 break; 312 } 313 314 if (!valid_input) { 315 kfree(wr_buf); 316 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 317 mutex_lock(&adev->dm.dc_lock); 318 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 319 mutex_unlock(&adev->dm.dc_lock); 320 return size; 321 } 322 323 /* save user force lane_count, link_rate to preferred settings 324 * spread spectrum will not be changed 325 */ 326 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 327 prefer_link_settings.use_link_rate_set = false; 328 prefer_link_settings.lane_count = param[0]; 329 prefer_link_settings.link_rate = param[1]; 330 331 mutex_lock(&adev->dm.dc_lock); 332 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 333 mutex_unlock(&adev->dm.dc_lock); 334 335 kfree(wr_buf); 336 return size; 337 } 338 339 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 340 * post-cursor2 (defined by VESA DP specification) 341 * 342 * valid values 343 * voltage swing: 0,1,2,3 344 * pre-emphasis : 0,1,2,3 345 * post cursor2 : 0,1,2,3 346 * 347 * 348 * how to use this debugfs 349 * 350 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 351 * 352 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 353 * 354 * To figure out which DP-x is the display for DP to be check, 355 * cd DP-x 356 * ls -ll 357 * There should be debugfs file, like link_settings, phy_settings. 358 * cat link_settings 359 * from lane_count, link_rate to figure which DP-x is for display to be worked 360 * on 361 * 362 * To get current DP PHY settings, 363 * cat phy_settings 364 * 365 * To change DP PHY settings, 366 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 367 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 368 * 0, 369 * echo 2 3 0 > phy_settings 370 * 371 * To check if change be applied, get current phy settings by 372 * cat phy_settings 373 * 374 * In case invalid values are set by user, like 375 * echo 1 4 0 > phy_settings 376 * 377 * HW will NOT be programmed by these settings. 378 * cat phy_settings will show the previous valid settings. 379 */ 380 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 381 size_t size, loff_t *pos) 382 { 383 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 384 struct dc_link *link = connector->dc_link; 385 char *rd_buf = NULL; 386 const uint32_t rd_buf_size = 20; 387 uint32_t result = 0; 388 int r; 389 390 if (*pos & 3 || size & 3) 391 return -EINVAL; 392 393 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 394 if (!rd_buf) 395 return -EINVAL; 396 397 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 398 link->cur_lane_setting[0].VOLTAGE_SWING, 399 link->cur_lane_setting[0].PRE_EMPHASIS, 400 link->cur_lane_setting[0].POST_CURSOR2); 401 402 while (size) { 403 if (*pos >= rd_buf_size) 404 break; 405 406 r = put_user((*(rd_buf + result)), buf); 407 if (r) { 408 kfree(rd_buf); 409 return r; /* r = -EFAULT */ 410 } 411 412 buf += 1; 413 size -= 1; 414 *pos += 1; 415 result += 1; 416 } 417 418 kfree(rd_buf); 419 return result; 420 } 421 422 static int dp_lttpr_status_show(struct seq_file *m, void *d) 423 { 424 char *data; 425 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 426 struct dc_link *link = connector->dc_link; 427 uint32_t read_size = 1; 428 uint8_t repeater_count = 0; 429 430 data = kzalloc(read_size, GFP_KERNEL); 431 if (!data) 432 return 0; 433 434 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 435 436 switch ((uint8_t)*data) { 437 case 0x80: 438 repeater_count = 1; 439 break; 440 case 0x40: 441 repeater_count = 2; 442 break; 443 case 0x20: 444 repeater_count = 3; 445 break; 446 case 0x10: 447 repeater_count = 4; 448 break; 449 case 0x8: 450 repeater_count = 5; 451 break; 452 case 0x4: 453 repeater_count = 6; 454 break; 455 case 0x2: 456 repeater_count = 7; 457 break; 458 case 0x1: 459 repeater_count = 8; 460 break; 461 case 0x0: 462 repeater_count = 0; 463 break; 464 default: 465 repeater_count = (uint8_t)*data; 466 break; 467 } 468 469 seq_printf(m, "phy repeater count: %d\n", repeater_count); 470 471 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 472 473 if ((uint8_t)*data == 0x55) 474 seq_printf(m, "phy repeater mode: transparent\n"); 475 else if ((uint8_t)*data == 0xAA) 476 seq_printf(m, "phy repeater mode: non-transparent\n"); 477 else if ((uint8_t)*data == 0x00) 478 seq_printf(m, "phy repeater mode: non lttpr\n"); 479 else 480 seq_printf(m, "phy repeater mode: read error\n"); 481 482 kfree(data); 483 return 0; 484 } 485 486 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 487 size_t size, loff_t *pos) 488 { 489 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 490 struct dc_link *link = connector->dc_link; 491 struct dc *dc = (struct dc *)link->dc; 492 char *wr_buf = NULL; 493 uint32_t wr_buf_size = 40; 494 long param[3]; 495 bool use_prefer_link_setting; 496 struct link_training_settings link_lane_settings; 497 int max_param_num = 3; 498 uint8_t param_nums = 0; 499 int r = 0; 500 501 502 if (size == 0) 503 return -EINVAL; 504 505 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 506 if (!wr_buf) 507 return -ENOSPC; 508 509 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 510 (long *)param, buf, 511 max_param_num, 512 ¶m_nums)) { 513 kfree(wr_buf); 514 return -EINVAL; 515 } 516 517 if (param_nums <= 0) { 518 kfree(wr_buf); 519 DRM_DEBUG_DRIVER("user data not be read\n"); 520 return -EINVAL; 521 } 522 523 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 524 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 525 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 526 kfree(wr_buf); 527 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 528 return size; 529 } 530 531 /* get link settings: lane count, link rate */ 532 use_prefer_link_setting = 533 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 534 (link->test_pattern_enabled)); 535 536 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 537 538 if (use_prefer_link_setting) { 539 link_lane_settings.link_settings.lane_count = 540 link->preferred_link_setting.lane_count; 541 link_lane_settings.link_settings.link_rate = 542 link->preferred_link_setting.link_rate; 543 link_lane_settings.link_settings.link_spread = 544 link->preferred_link_setting.link_spread; 545 } else { 546 link_lane_settings.link_settings.lane_count = 547 link->cur_link_settings.lane_count; 548 link_lane_settings.link_settings.link_rate = 549 link->cur_link_settings.link_rate; 550 link_lane_settings.link_settings.link_spread = 551 link->cur_link_settings.link_spread; 552 } 553 554 /* apply phy settings from user */ 555 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 556 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 557 (enum dc_voltage_swing) (param[0]); 558 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 559 (enum dc_pre_emphasis) (param[1]); 560 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 561 (enum dc_post_cursor2) (param[2]); 562 } 563 564 /* program ASIC registers and DPCD registers */ 565 dc_link_set_drive_settings(dc, &link_lane_settings, link); 566 567 kfree(wr_buf); 568 return size; 569 } 570 571 /* function description 572 * 573 * set PHY layer or Link layer test pattern 574 * PHY test pattern is used for PHY SI check. 575 * Link layer test will not affect PHY SI. 576 * 577 * Reset Test Pattern: 578 * 0 = DP_TEST_PATTERN_VIDEO_MODE 579 * 580 * PHY test pattern supported: 581 * 1 = DP_TEST_PATTERN_D102 582 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 583 * 3 = DP_TEST_PATTERN_PRBS7 584 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 585 * 5 = DP_TEST_PATTERN_CP2520_1 586 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 587 * 7 = DP_TEST_PATTERN_CP2520_3 588 * 589 * DP PHY Link Training Patterns 590 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 591 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 592 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 593 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 594 * 595 * DP Link Layer Test pattern 596 * c = DP_TEST_PATTERN_COLOR_SQUARES 597 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 598 * e = DP_TEST_PATTERN_VERTICAL_BARS 599 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 600 * 10= DP_TEST_PATTERN_COLOR_RAMP 601 * 602 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 603 * 604 * --- set test pattern 605 * echo <test pattern #> > test_pattern 606 * 607 * If test pattern # is not supported, NO HW programming will be done. 608 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 609 * for the user pattern. input 10 bytes data are separated by space 610 * 611 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 612 * 613 * --- reset test pattern 614 * echo 0 > test_pattern 615 * 616 * --- HPD detection is disabled when set PHY test pattern 617 * 618 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 619 * is disable. User could unplug DP display from DP connected and plug scope to 620 * check test pattern PHY SI. 621 * If there is need unplug scope and plug DP display back, do steps below: 622 * echo 0 > phy_test_pattern 623 * unplug scope 624 * plug DP display. 625 * 626 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 627 * driver could detect "unplug scope" and "plug DP display" 628 */ 629 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 630 size_t size, loff_t *pos) 631 { 632 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 633 struct dc_link *link = connector->dc_link; 634 char *wr_buf = NULL; 635 uint32_t wr_buf_size = 100; 636 long param[11] = {0x0}; 637 int max_param_num = 11; 638 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 639 bool disable_hpd = false; 640 bool valid_test_pattern = false; 641 uint8_t param_nums = 0; 642 /* init with default 80bit custom pattern */ 643 uint8_t custom_pattern[10] = { 644 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 645 0x1f, 0x7c, 0xf0, 0xc1, 0x07 646 }; 647 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 648 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 649 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 650 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 651 struct link_training_settings link_training_settings; 652 int i; 653 654 if (size == 0) 655 return -EINVAL; 656 657 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 658 if (!wr_buf) 659 return -ENOSPC; 660 661 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 662 (long *)param, buf, 663 max_param_num, 664 ¶m_nums)) { 665 kfree(wr_buf); 666 return -EINVAL; 667 } 668 669 if (param_nums <= 0) { 670 kfree(wr_buf); 671 DRM_DEBUG_DRIVER("user data not be read\n"); 672 return -EINVAL; 673 } 674 675 676 test_pattern = param[0]; 677 678 switch (test_pattern) { 679 case DP_TEST_PATTERN_VIDEO_MODE: 680 case DP_TEST_PATTERN_COLOR_SQUARES: 681 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 682 case DP_TEST_PATTERN_VERTICAL_BARS: 683 case DP_TEST_PATTERN_HORIZONTAL_BARS: 684 case DP_TEST_PATTERN_COLOR_RAMP: 685 valid_test_pattern = true; 686 break; 687 688 case DP_TEST_PATTERN_D102: 689 case DP_TEST_PATTERN_SYMBOL_ERROR: 690 case DP_TEST_PATTERN_PRBS7: 691 case DP_TEST_PATTERN_80BIT_CUSTOM: 692 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 693 case DP_TEST_PATTERN_TRAINING_PATTERN4: 694 disable_hpd = true; 695 valid_test_pattern = true; 696 break; 697 698 default: 699 valid_test_pattern = false; 700 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 701 break; 702 } 703 704 if (!valid_test_pattern) { 705 kfree(wr_buf); 706 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 707 return size; 708 } 709 710 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 711 for (i = 0; i < 10; i++) { 712 if ((uint8_t) param[i + 1] != 0x0) 713 break; 714 } 715 716 if (i < 10) { 717 /* not use default value */ 718 for (i = 0; i < 10; i++) 719 custom_pattern[i] = (uint8_t) param[i + 1]; 720 } 721 } 722 723 /* Usage: set DP physical test pattern using debugfs with normal DP 724 * panel. Then plug out DP panel and connect a scope to measure 725 * For normal video mode and test pattern generated from CRCT, 726 * they are visibile to user. So do not disable HPD. 727 * Video Mode is also set to clear the test pattern, so enable HPD 728 * because it might have been disabled after a test pattern was set. 729 * AUX depends on HPD * sequence dependent, do not move! 730 */ 731 if (!disable_hpd) 732 dc_link_enable_hpd(link); 733 734 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 735 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 736 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 737 738 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 739 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 740 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 741 742 link_training_settings.link_settings = cur_link_settings; 743 744 745 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 746 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 747 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 748 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 749 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 750 link_training_settings.link_settings = prefer_link_settings; 751 } 752 753 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 754 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 755 756 dc_link_set_test_pattern( 757 link, 758 test_pattern, 759 DP_TEST_PATTERN_COLOR_SPACE_RGB, 760 &link_training_settings, 761 custom_pattern, 762 10); 763 764 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 765 * Then plug out DP panel and connect a scope to measure DP PHY signal. 766 * Need disable interrupt to avoid SW driver disable DP output. This is 767 * done after the test pattern is set. 768 */ 769 if (valid_test_pattern && disable_hpd) 770 dc_link_disable_hpd(link); 771 772 kfree(wr_buf); 773 774 return size; 775 } 776 777 /* 778 * Returns the DMCUB tracebuffer contents. 779 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 780 */ 781 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 782 { 783 struct amdgpu_device *adev = m->private; 784 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 785 struct dmub_debugfs_trace_entry *entries; 786 uint8_t *tbuf_base; 787 uint32_t tbuf_size, max_entries, num_entries, i; 788 789 if (!fb_info) 790 return 0; 791 792 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 793 if (!tbuf_base) 794 return 0; 795 796 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 797 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 798 sizeof(struct dmub_debugfs_trace_entry); 799 800 num_entries = 801 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 802 803 num_entries = min(num_entries, max_entries); 804 805 entries = (struct dmub_debugfs_trace_entry 806 *)(tbuf_base + 807 sizeof(struct dmub_debugfs_trace_header)); 808 809 for (i = 0; i < num_entries; ++i) { 810 struct dmub_debugfs_trace_entry *entry = &entries[i]; 811 812 seq_printf(m, 813 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 814 entry->trace_code, entry->tick_count, entry->param0, 815 entry->param1); 816 } 817 818 return 0; 819 } 820 821 /* 822 * Returns the DMCUB firmware state contents. 823 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 824 */ 825 static int dmub_fw_state_show(struct seq_file *m, void *data) 826 { 827 struct amdgpu_device *adev = m->private; 828 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 829 uint8_t *state_base; 830 uint32_t state_size; 831 832 if (!fb_info) 833 return 0; 834 835 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 836 if (!state_base) 837 return 0; 838 839 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 840 841 return seq_write(m, state_base, state_size); 842 } 843 844 /* psr_capability_show() - show eDP panel PSR capability 845 * 846 * The read function: sink_psr_capability_show 847 * Shows if sink has PSR capability or not. 848 * If yes - the PSR version is appended 849 * 850 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 851 * 852 * Expected output: 853 * "Sink support: no\n" - if panel doesn't support PSR 854 * "Sink support: yes [0x01]\n" - if panel supports PSR1 855 * "Driver support: no\n" - if driver doesn't support PSR 856 * "Driver support: yes [0x01]\n" - if driver supports PSR1 857 */ 858 static int psr_capability_show(struct seq_file *m, void *data) 859 { 860 struct drm_connector *connector = m->private; 861 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 862 struct dc_link *link = aconnector->dc_link; 863 864 if (!link) 865 return -ENODEV; 866 867 if (link->type == dc_connection_none) 868 return -ENODEV; 869 870 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 871 return -ENODEV; 872 873 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 874 if (link->dpcd_caps.psr_info.psr_version) 875 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 876 seq_puts(m, "\n"); 877 878 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 879 if (link->psr_settings.psr_version) 880 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 881 seq_puts(m, "\n"); 882 883 return 0; 884 } 885 886 /* 887 * Returns the current bpc for the crtc. 888 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 889 */ 890 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 891 { 892 struct drm_crtc *crtc = m->private; 893 struct drm_device *dev = crtc->dev; 894 struct dm_crtc_state *dm_crtc_state = NULL; 895 int res = -ENODEV; 896 unsigned int bpc; 897 898 mutex_lock(&dev->mode_config.mutex); 899 drm_modeset_lock(&crtc->mutex, NULL); 900 if (crtc->state == NULL) 901 goto unlock; 902 903 dm_crtc_state = to_dm_crtc_state(crtc->state); 904 if (dm_crtc_state->stream == NULL) 905 goto unlock; 906 907 switch (dm_crtc_state->stream->timing.display_color_depth) { 908 case COLOR_DEPTH_666: 909 bpc = 6; 910 break; 911 case COLOR_DEPTH_888: 912 bpc = 8; 913 break; 914 case COLOR_DEPTH_101010: 915 bpc = 10; 916 break; 917 case COLOR_DEPTH_121212: 918 bpc = 12; 919 break; 920 case COLOR_DEPTH_161616: 921 bpc = 16; 922 break; 923 default: 924 goto unlock; 925 } 926 927 seq_printf(m, "Current: %u\n", bpc); 928 res = 0; 929 930 unlock: 931 drm_modeset_unlock(&crtc->mutex); 932 mutex_unlock(&dev->mode_config.mutex); 933 934 return res; 935 } 936 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 937 938 /* 939 * Example usage: 940 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 941 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 942 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 943 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 944 */ 945 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 946 size_t size, loff_t *pos) 947 { 948 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 949 char *wr_buf = NULL; 950 uint32_t wr_buf_size = 42; 951 int max_param_num = 1; 952 long param; 953 uint8_t param_nums = 0; 954 955 if (size == 0) 956 return -EINVAL; 957 958 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 959 960 if (!wr_buf) { 961 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 962 return -ENOSPC; 963 } 964 965 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 966 ¶m, buf, 967 max_param_num, 968 ¶m_nums)) { 969 kfree(wr_buf); 970 return -EINVAL; 971 } 972 973 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 974 975 kfree(wr_buf); 976 return 0; 977 } 978 979 #ifdef CONFIG_DRM_AMD_DC_HDCP 980 /* 981 * Returns the HDCP capability of the Display (1.4 for now). 982 * 983 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 984 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 985 * 986 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 987 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 988 */ 989 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 990 { 991 struct drm_connector *connector = m->private; 992 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 993 bool hdcp_cap, hdcp2_cap; 994 995 if (connector->status != connector_status_connected) 996 return -ENODEV; 997 998 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 999 1000 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1001 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1002 1003 1004 if (hdcp_cap) 1005 seq_printf(m, "%s ", "HDCP1.4"); 1006 if (hdcp2_cap) 1007 seq_printf(m, "%s ", "HDCP2.2"); 1008 1009 if (!hdcp_cap && !hdcp2_cap) 1010 seq_printf(m, "%s ", "None"); 1011 1012 seq_puts(m, "\n"); 1013 1014 return 0; 1015 } 1016 #endif 1017 1018 /* 1019 * Returns whether the connected display is internal and not hotpluggable. 1020 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1021 */ 1022 static int internal_display_show(struct seq_file *m, void *data) 1023 { 1024 struct drm_connector *connector = m->private; 1025 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1026 struct dc_link *link = aconnector->dc_link; 1027 1028 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1029 1030 return 0; 1031 } 1032 1033 /* function description 1034 * 1035 * generic SDP message access for testing 1036 * 1037 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1038 * 1039 * SDP header 1040 * Hb0 : Secondary-Data Packet ID 1041 * Hb1 : Secondary-Data Packet type 1042 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1043 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1044 * 1045 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1046 */ 1047 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1048 size_t size, loff_t *pos) 1049 { 1050 int r; 1051 uint8_t data[36]; 1052 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1053 struct dm_crtc_state *acrtc_state; 1054 uint32_t write_size = 36; 1055 1056 if (connector->base.status != connector_status_connected) 1057 return -ENODEV; 1058 1059 if (size == 0) 1060 return 0; 1061 1062 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1063 1064 r = copy_from_user(data, buf, write_size); 1065 1066 write_size -= r; 1067 1068 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1069 1070 return write_size; 1071 } 1072 1073 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1074 size_t size, loff_t *pos) 1075 { 1076 int r; 1077 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1078 1079 if (size < sizeof(connector->debugfs_dpcd_address)) 1080 return -EINVAL; 1081 1082 r = copy_from_user(&connector->debugfs_dpcd_address, 1083 buf, sizeof(connector->debugfs_dpcd_address)); 1084 1085 return size - r; 1086 } 1087 1088 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1089 size_t size, loff_t *pos) 1090 { 1091 int r; 1092 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1093 1094 if (size < sizeof(connector->debugfs_dpcd_size)) 1095 return -EINVAL; 1096 1097 r = copy_from_user(&connector->debugfs_dpcd_size, 1098 buf, sizeof(connector->debugfs_dpcd_size)); 1099 1100 if (connector->debugfs_dpcd_size > 256) 1101 connector->debugfs_dpcd_size = 0; 1102 1103 return size - r; 1104 } 1105 1106 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1107 size_t size, loff_t *pos) 1108 { 1109 int r; 1110 char *data; 1111 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1112 struct dc_link *link = connector->dc_link; 1113 uint32_t write_size = connector->debugfs_dpcd_size; 1114 1115 if (!write_size || size < write_size) 1116 return -EINVAL; 1117 1118 data = kzalloc(write_size, GFP_KERNEL); 1119 if (!data) 1120 return 0; 1121 1122 r = copy_from_user(data, buf, write_size); 1123 1124 dm_helpers_dp_write_dpcd(link->ctx, link, 1125 connector->debugfs_dpcd_address, data, write_size - r); 1126 kfree(data); 1127 return write_size - r; 1128 } 1129 1130 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1131 size_t size, loff_t *pos) 1132 { 1133 int r; 1134 char *data; 1135 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1136 struct dc_link *link = connector->dc_link; 1137 uint32_t read_size = connector->debugfs_dpcd_size; 1138 1139 if (!read_size || size < read_size) 1140 return 0; 1141 1142 data = kzalloc(read_size, GFP_KERNEL); 1143 if (!data) 1144 return 0; 1145 1146 dm_helpers_dp_read_dpcd(link->ctx, link, 1147 connector->debugfs_dpcd_address, data, read_size); 1148 1149 r = copy_to_user(buf, data, read_size); 1150 1151 kfree(data); 1152 return read_size - r; 1153 } 1154 1155 /* function: Read link's DSC & FEC capabilities 1156 * 1157 * 1158 * Access it with the following command (you need to specify 1159 * connector like DP-1): 1160 * 1161 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1162 * 1163 */ 1164 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1165 { 1166 struct drm_connector *connector = m->private; 1167 struct drm_modeset_acquire_ctx ctx; 1168 struct drm_device *dev = connector->dev; 1169 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1170 int ret = 0; 1171 bool try_again = false; 1172 bool is_fec_supported = false; 1173 bool is_dsc_supported = false; 1174 struct dpcd_caps dpcd_caps; 1175 1176 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1177 do { 1178 try_again = false; 1179 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1180 if (ret) { 1181 if (ret == -EDEADLK) { 1182 ret = drm_modeset_backoff(&ctx); 1183 if (!ret) { 1184 try_again = true; 1185 continue; 1186 } 1187 } 1188 break; 1189 } 1190 if (connector->status != connector_status_connected) { 1191 ret = -ENODEV; 1192 break; 1193 } 1194 dpcd_caps = aconnector->dc_link->dpcd_caps; 1195 if (aconnector->port) { 1196 /* aconnector sets dsc_aux during get_modes call 1197 * if MST connector has it means it can either 1198 * enable DSC on the sink device or on MST branch 1199 * its connected to. 1200 */ 1201 if (aconnector->dsc_aux) { 1202 is_fec_supported = true; 1203 is_dsc_supported = true; 1204 } 1205 } else { 1206 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1207 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1208 } 1209 } while (try_again); 1210 1211 drm_modeset_drop_locks(&ctx); 1212 drm_modeset_acquire_fini(&ctx); 1213 1214 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1215 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1216 1217 return ret; 1218 } 1219 1220 /* function: Trigger virtual HPD redetection on connector 1221 * 1222 * This function will perform link rediscovery, link disable 1223 * and enable, and dm connector state update. 1224 * 1225 * Retrigger HPD on an existing connector by echoing 1 into 1226 * its respectful "trigger_hotplug" debugfs entry: 1227 * 1228 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1229 * 1230 * This function can perform HPD unplug: 1231 * 1232 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1233 * 1234 */ 1235 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1236 size_t size, loff_t *pos) 1237 { 1238 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1239 struct drm_connector *connector = &aconnector->base; 1240 struct dc_link *link = NULL; 1241 struct drm_device *dev = connector->dev; 1242 struct amdgpu_device *adev = drm_to_adev(dev); 1243 enum dc_connection_type new_connection_type = dc_connection_none; 1244 char *wr_buf = NULL; 1245 uint32_t wr_buf_size = 42; 1246 int max_param_num = 1; 1247 long param[1] = {0}; 1248 uint8_t param_nums = 0; 1249 bool ret = false; 1250 1251 if (!aconnector || !aconnector->dc_link) 1252 return -EINVAL; 1253 1254 if (size == 0) 1255 return -EINVAL; 1256 1257 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1258 1259 if (!wr_buf) { 1260 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1261 return -ENOSPC; 1262 } 1263 1264 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1265 (long *)param, buf, 1266 max_param_num, 1267 ¶m_nums)) { 1268 kfree(wr_buf); 1269 return -EINVAL; 1270 } 1271 1272 kfree(wr_buf); 1273 1274 if (param_nums <= 0) { 1275 DRM_DEBUG_DRIVER("user data not be read\n"); 1276 return -EINVAL; 1277 } 1278 1279 mutex_lock(&aconnector->hpd_lock); 1280 1281 /* Don't support for mst end device*/ 1282 if (aconnector->mst_port) { 1283 mutex_unlock(&aconnector->hpd_lock); 1284 return -EINVAL; 1285 } 1286 1287 if (param[0] == 1) { 1288 1289 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1290 new_connection_type != dc_connection_none) 1291 goto unlock; 1292 1293 mutex_lock(&adev->dm.dc_lock); 1294 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1295 mutex_unlock(&adev->dm.dc_lock); 1296 1297 if (!ret) 1298 goto unlock; 1299 1300 amdgpu_dm_update_connector_after_detect(aconnector); 1301 1302 drm_modeset_lock_all(dev); 1303 dm_restore_drm_connector_state(dev, connector); 1304 drm_modeset_unlock_all(dev); 1305 1306 drm_kms_helper_connector_hotplug_event(connector); 1307 } else if (param[0] == 0) { 1308 if (!aconnector->dc_link) 1309 goto unlock; 1310 1311 link = aconnector->dc_link; 1312 1313 if (link->local_sink) { 1314 dc_sink_release(link->local_sink); 1315 link->local_sink = NULL; 1316 } 1317 1318 link->dpcd_sink_count = 0; 1319 link->type = dc_connection_none; 1320 link->dongle_max_pix_clk = 0; 1321 1322 amdgpu_dm_update_connector_after_detect(aconnector); 1323 1324 /* If the aconnector is the root node in mst topology */ 1325 if (aconnector->mst_mgr.mst_state == true) 1326 reset_cur_dp_mst_topology(link); 1327 1328 drm_modeset_lock_all(dev); 1329 dm_restore_drm_connector_state(dev, connector); 1330 drm_modeset_unlock_all(dev); 1331 1332 drm_kms_helper_connector_hotplug_event(connector); 1333 } 1334 1335 unlock: 1336 mutex_unlock(&aconnector->hpd_lock); 1337 1338 return size; 1339 } 1340 1341 /* function: read DSC status on the connector 1342 * 1343 * The read function: dp_dsc_clock_en_read 1344 * returns current status of DSC clock on the connector. 1345 * The return is a boolean flag: 1 or 0. 1346 * 1347 * Access it with the following command (you need to specify 1348 * connector like DP-1): 1349 * 1350 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1351 * 1352 * Expected output: 1353 * 1 - means that DSC is currently enabled 1354 * 0 - means that DSC is disabled 1355 */ 1356 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1357 size_t size, loff_t *pos) 1358 { 1359 char *rd_buf = NULL; 1360 char *rd_buf_ptr = NULL; 1361 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1362 struct display_stream_compressor *dsc; 1363 struct dcn_dsc_state dsc_state = {0}; 1364 const uint32_t rd_buf_size = 10; 1365 struct pipe_ctx *pipe_ctx; 1366 ssize_t result = 0; 1367 int i, r, str_len = 30; 1368 1369 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1370 1371 if (!rd_buf) 1372 return -ENOMEM; 1373 1374 rd_buf_ptr = rd_buf; 1375 1376 for (i = 0; i < MAX_PIPES; i++) { 1377 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1378 if (pipe_ctx && pipe_ctx->stream && 1379 pipe_ctx->stream->link == aconnector->dc_link) 1380 break; 1381 } 1382 1383 if (!pipe_ctx) { 1384 kfree(rd_buf); 1385 return -ENXIO; 1386 } 1387 1388 dsc = pipe_ctx->stream_res.dsc; 1389 if (dsc) 1390 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1391 1392 snprintf(rd_buf_ptr, str_len, 1393 "%d\n", 1394 dsc_state.dsc_clock_en); 1395 rd_buf_ptr += str_len; 1396 1397 while (size) { 1398 if (*pos >= rd_buf_size) 1399 break; 1400 1401 r = put_user(*(rd_buf + result), buf); 1402 if (r) { 1403 kfree(rd_buf); 1404 return r; /* r = -EFAULT */ 1405 } 1406 1407 buf += 1; 1408 size -= 1; 1409 *pos += 1; 1410 result += 1; 1411 } 1412 1413 kfree(rd_buf); 1414 return result; 1415 } 1416 1417 /* function: write force DSC on the connector 1418 * 1419 * The write function: dp_dsc_clock_en_write 1420 * enables to force DSC on the connector. 1421 * User can write to either force enable or force disable DSC 1422 * on the next modeset or set it to driver default 1423 * 1424 * Accepted inputs: 1425 * 0 - default DSC enablement policy 1426 * 1 - force enable DSC on the connector 1427 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1428 * 1429 * Writing DSC settings is done with the following command: 1430 * - To force enable DSC (you need to specify 1431 * connector like DP-1): 1432 * 1433 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1434 * 1435 * - To return to default state set the flag to zero and 1436 * let driver deal with DSC automatically 1437 * (you need to specify connector like DP-1): 1438 * 1439 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1440 * 1441 */ 1442 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1443 size_t size, loff_t *pos) 1444 { 1445 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1446 struct drm_connector *connector = &aconnector->base; 1447 struct drm_device *dev = connector->dev; 1448 struct drm_crtc *crtc = NULL; 1449 struct dm_crtc_state *dm_crtc_state = NULL; 1450 struct pipe_ctx *pipe_ctx; 1451 int i; 1452 char *wr_buf = NULL; 1453 uint32_t wr_buf_size = 42; 1454 int max_param_num = 1; 1455 long param[1] = {0}; 1456 uint8_t param_nums = 0; 1457 1458 if (size == 0) 1459 return -EINVAL; 1460 1461 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1462 1463 if (!wr_buf) { 1464 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1465 return -ENOSPC; 1466 } 1467 1468 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1469 (long *)param, buf, 1470 max_param_num, 1471 ¶m_nums)) { 1472 kfree(wr_buf); 1473 return -EINVAL; 1474 } 1475 1476 if (param_nums <= 0) { 1477 DRM_DEBUG_DRIVER("user data not be read\n"); 1478 kfree(wr_buf); 1479 return -EINVAL; 1480 } 1481 1482 for (i = 0; i < MAX_PIPES; i++) { 1483 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1484 if (pipe_ctx && pipe_ctx->stream && 1485 pipe_ctx->stream->link == aconnector->dc_link) 1486 break; 1487 } 1488 1489 if (!pipe_ctx || !pipe_ctx->stream) 1490 goto done; 1491 1492 // Get CRTC state 1493 mutex_lock(&dev->mode_config.mutex); 1494 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1495 1496 if (connector->state == NULL) 1497 goto unlock; 1498 1499 crtc = connector->state->crtc; 1500 if (crtc == NULL) 1501 goto unlock; 1502 1503 drm_modeset_lock(&crtc->mutex, NULL); 1504 if (crtc->state == NULL) 1505 goto unlock; 1506 1507 dm_crtc_state = to_dm_crtc_state(crtc->state); 1508 if (dm_crtc_state->stream == NULL) 1509 goto unlock; 1510 1511 if (param[0] == 1) 1512 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1513 else if (param[0] == 2) 1514 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1515 else 1516 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1517 1518 dm_crtc_state->dsc_force_changed = true; 1519 1520 unlock: 1521 if (crtc) 1522 drm_modeset_unlock(&crtc->mutex); 1523 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1524 mutex_unlock(&dev->mode_config.mutex); 1525 1526 done: 1527 kfree(wr_buf); 1528 return size; 1529 } 1530 1531 /* function: read DSC slice width parameter on the connector 1532 * 1533 * The read function: dp_dsc_slice_width_read 1534 * returns dsc slice width used in the current configuration 1535 * The return is an integer: 0 or other positive number 1536 * 1537 * Access the status with the following command: 1538 * 1539 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1540 * 1541 * 0 - means that DSC is disabled 1542 * 1543 * Any other number more than zero represents the 1544 * slice width currently used by DSC in pixels 1545 * 1546 */ 1547 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1548 size_t size, loff_t *pos) 1549 { 1550 char *rd_buf = NULL; 1551 char *rd_buf_ptr = NULL; 1552 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1553 struct display_stream_compressor *dsc; 1554 struct dcn_dsc_state dsc_state = {0}; 1555 const uint32_t rd_buf_size = 100; 1556 struct pipe_ctx *pipe_ctx; 1557 ssize_t result = 0; 1558 int i, r, str_len = 30; 1559 1560 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1561 1562 if (!rd_buf) 1563 return -ENOMEM; 1564 1565 rd_buf_ptr = rd_buf; 1566 1567 for (i = 0; i < MAX_PIPES; i++) { 1568 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1569 if (pipe_ctx && pipe_ctx->stream && 1570 pipe_ctx->stream->link == aconnector->dc_link) 1571 break; 1572 } 1573 1574 if (!pipe_ctx) { 1575 kfree(rd_buf); 1576 return -ENXIO; 1577 } 1578 1579 dsc = pipe_ctx->stream_res.dsc; 1580 if (dsc) 1581 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1582 1583 snprintf(rd_buf_ptr, str_len, 1584 "%d\n", 1585 dsc_state.dsc_slice_width); 1586 rd_buf_ptr += str_len; 1587 1588 while (size) { 1589 if (*pos >= rd_buf_size) 1590 break; 1591 1592 r = put_user(*(rd_buf + result), buf); 1593 if (r) { 1594 kfree(rd_buf); 1595 return r; /* r = -EFAULT */ 1596 } 1597 1598 buf += 1; 1599 size -= 1; 1600 *pos += 1; 1601 result += 1; 1602 } 1603 1604 kfree(rd_buf); 1605 return result; 1606 } 1607 1608 /* function: write DSC slice width parameter 1609 * 1610 * The write function: dp_dsc_slice_width_write 1611 * overwrites automatically generated DSC configuration 1612 * of slice width. 1613 * 1614 * The user has to write the slice width divisible by the 1615 * picture width. 1616 * 1617 * Also the user has to write width in hexidecimal 1618 * rather than in decimal. 1619 * 1620 * Writing DSC settings is done with the following command: 1621 * - To force overwrite slice width: (example sets to 1920 pixels) 1622 * 1623 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1624 * 1625 * - To stop overwriting and let driver find the optimal size, 1626 * set the width to zero: 1627 * 1628 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1629 * 1630 */ 1631 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1632 size_t size, loff_t *pos) 1633 { 1634 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1635 struct pipe_ctx *pipe_ctx; 1636 struct drm_connector *connector = &aconnector->base; 1637 struct drm_device *dev = connector->dev; 1638 struct drm_crtc *crtc = NULL; 1639 struct dm_crtc_state *dm_crtc_state = NULL; 1640 int i; 1641 char *wr_buf = NULL; 1642 uint32_t wr_buf_size = 42; 1643 int max_param_num = 1; 1644 long param[1] = {0}; 1645 uint8_t param_nums = 0; 1646 1647 if (size == 0) 1648 return -EINVAL; 1649 1650 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1651 1652 if (!wr_buf) { 1653 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1654 return -ENOSPC; 1655 } 1656 1657 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1658 (long *)param, buf, 1659 max_param_num, 1660 ¶m_nums)) { 1661 kfree(wr_buf); 1662 return -EINVAL; 1663 } 1664 1665 if (param_nums <= 0) { 1666 DRM_DEBUG_DRIVER("user data not be read\n"); 1667 kfree(wr_buf); 1668 return -EINVAL; 1669 } 1670 1671 for (i = 0; i < MAX_PIPES; i++) { 1672 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1673 if (pipe_ctx && pipe_ctx->stream && 1674 pipe_ctx->stream->link == aconnector->dc_link) 1675 break; 1676 } 1677 1678 if (!pipe_ctx || !pipe_ctx->stream) 1679 goto done; 1680 1681 // Safely get CRTC state 1682 mutex_lock(&dev->mode_config.mutex); 1683 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1684 1685 if (connector->state == NULL) 1686 goto unlock; 1687 1688 crtc = connector->state->crtc; 1689 if (crtc == NULL) 1690 goto unlock; 1691 1692 drm_modeset_lock(&crtc->mutex, NULL); 1693 if (crtc->state == NULL) 1694 goto unlock; 1695 1696 dm_crtc_state = to_dm_crtc_state(crtc->state); 1697 if (dm_crtc_state->stream == NULL) 1698 goto unlock; 1699 1700 if (param[0] > 0) 1701 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1702 pipe_ctx->stream->timing.h_addressable, 1703 param[0]); 1704 else 1705 aconnector->dsc_settings.dsc_num_slices_h = 0; 1706 1707 dm_crtc_state->dsc_force_changed = true; 1708 1709 unlock: 1710 if (crtc) 1711 drm_modeset_unlock(&crtc->mutex); 1712 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1713 mutex_unlock(&dev->mode_config.mutex); 1714 1715 done: 1716 kfree(wr_buf); 1717 return size; 1718 } 1719 1720 /* function: read DSC slice height parameter on the connector 1721 * 1722 * The read function: dp_dsc_slice_height_read 1723 * returns dsc slice height used in the current configuration 1724 * The return is an integer: 0 or other positive number 1725 * 1726 * Access the status with the following command: 1727 * 1728 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1729 * 1730 * 0 - means that DSC is disabled 1731 * 1732 * Any other number more than zero represents the 1733 * slice height currently used by DSC in pixels 1734 * 1735 */ 1736 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1737 size_t size, loff_t *pos) 1738 { 1739 char *rd_buf = NULL; 1740 char *rd_buf_ptr = NULL; 1741 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1742 struct display_stream_compressor *dsc; 1743 struct dcn_dsc_state dsc_state = {0}; 1744 const uint32_t rd_buf_size = 100; 1745 struct pipe_ctx *pipe_ctx; 1746 ssize_t result = 0; 1747 int i, r, str_len = 30; 1748 1749 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1750 1751 if (!rd_buf) 1752 return -ENOMEM; 1753 1754 rd_buf_ptr = rd_buf; 1755 1756 for (i = 0; i < MAX_PIPES; i++) { 1757 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1758 if (pipe_ctx && pipe_ctx->stream && 1759 pipe_ctx->stream->link == aconnector->dc_link) 1760 break; 1761 } 1762 1763 if (!pipe_ctx) { 1764 kfree(rd_buf); 1765 return -ENXIO; 1766 } 1767 1768 dsc = pipe_ctx->stream_res.dsc; 1769 if (dsc) 1770 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1771 1772 snprintf(rd_buf_ptr, str_len, 1773 "%d\n", 1774 dsc_state.dsc_slice_height); 1775 rd_buf_ptr += str_len; 1776 1777 while (size) { 1778 if (*pos >= rd_buf_size) 1779 break; 1780 1781 r = put_user(*(rd_buf + result), buf); 1782 if (r) { 1783 kfree(rd_buf); 1784 return r; /* r = -EFAULT */ 1785 } 1786 1787 buf += 1; 1788 size -= 1; 1789 *pos += 1; 1790 result += 1; 1791 } 1792 1793 kfree(rd_buf); 1794 return result; 1795 } 1796 1797 /* function: write DSC slice height parameter 1798 * 1799 * The write function: dp_dsc_slice_height_write 1800 * overwrites automatically generated DSC configuration 1801 * of slice height. 1802 * 1803 * The user has to write the slice height divisible by the 1804 * picture height. 1805 * 1806 * Also the user has to write height in hexidecimal 1807 * rather than in decimal. 1808 * 1809 * Writing DSC settings is done with the following command: 1810 * - To force overwrite slice height (example sets to 128 pixels): 1811 * 1812 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1813 * 1814 * - To stop overwriting and let driver find the optimal size, 1815 * set the height to zero: 1816 * 1817 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1818 * 1819 */ 1820 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1821 size_t size, loff_t *pos) 1822 { 1823 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1824 struct drm_connector *connector = &aconnector->base; 1825 struct drm_device *dev = connector->dev; 1826 struct drm_crtc *crtc = NULL; 1827 struct dm_crtc_state *dm_crtc_state = NULL; 1828 struct pipe_ctx *pipe_ctx; 1829 int i; 1830 char *wr_buf = NULL; 1831 uint32_t wr_buf_size = 42; 1832 int max_param_num = 1; 1833 uint8_t param_nums = 0; 1834 long param[1] = {0}; 1835 1836 if (size == 0) 1837 return -EINVAL; 1838 1839 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1840 1841 if (!wr_buf) { 1842 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1843 return -ENOSPC; 1844 } 1845 1846 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1847 (long *)param, buf, 1848 max_param_num, 1849 ¶m_nums)) { 1850 kfree(wr_buf); 1851 return -EINVAL; 1852 } 1853 1854 if (param_nums <= 0) { 1855 DRM_DEBUG_DRIVER("user data not be read\n"); 1856 kfree(wr_buf); 1857 return -EINVAL; 1858 } 1859 1860 for (i = 0; i < MAX_PIPES; i++) { 1861 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1862 if (pipe_ctx && pipe_ctx->stream && 1863 pipe_ctx->stream->link == aconnector->dc_link) 1864 break; 1865 } 1866 1867 if (!pipe_ctx || !pipe_ctx->stream) 1868 goto done; 1869 1870 // Get CRTC state 1871 mutex_lock(&dev->mode_config.mutex); 1872 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1873 1874 if (connector->state == NULL) 1875 goto unlock; 1876 1877 crtc = connector->state->crtc; 1878 if (crtc == NULL) 1879 goto unlock; 1880 1881 drm_modeset_lock(&crtc->mutex, NULL); 1882 if (crtc->state == NULL) 1883 goto unlock; 1884 1885 dm_crtc_state = to_dm_crtc_state(crtc->state); 1886 if (dm_crtc_state->stream == NULL) 1887 goto unlock; 1888 1889 if (param[0] > 0) 1890 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1891 pipe_ctx->stream->timing.v_addressable, 1892 param[0]); 1893 else 1894 aconnector->dsc_settings.dsc_num_slices_v = 0; 1895 1896 dm_crtc_state->dsc_force_changed = true; 1897 1898 unlock: 1899 if (crtc) 1900 drm_modeset_unlock(&crtc->mutex); 1901 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1902 mutex_unlock(&dev->mode_config.mutex); 1903 1904 done: 1905 kfree(wr_buf); 1906 return size; 1907 } 1908 1909 /* function: read DSC target rate on the connector in bits per pixel 1910 * 1911 * The read function: dp_dsc_bits_per_pixel_read 1912 * returns target rate of compression in bits per pixel 1913 * The return is an integer: 0 or other positive integer 1914 * 1915 * Access it with the following command: 1916 * 1917 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1918 * 1919 * 0 - means that DSC is disabled 1920 */ 1921 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1922 size_t size, loff_t *pos) 1923 { 1924 char *rd_buf = NULL; 1925 char *rd_buf_ptr = NULL; 1926 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1927 struct display_stream_compressor *dsc; 1928 struct dcn_dsc_state dsc_state = {0}; 1929 const uint32_t rd_buf_size = 100; 1930 struct pipe_ctx *pipe_ctx; 1931 ssize_t result = 0; 1932 int i, r, str_len = 30; 1933 1934 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1935 1936 if (!rd_buf) 1937 return -ENOMEM; 1938 1939 rd_buf_ptr = rd_buf; 1940 1941 for (i = 0; i < MAX_PIPES; i++) { 1942 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1943 if (pipe_ctx && pipe_ctx->stream && 1944 pipe_ctx->stream->link == aconnector->dc_link) 1945 break; 1946 } 1947 1948 if (!pipe_ctx) { 1949 kfree(rd_buf); 1950 return -ENXIO; 1951 } 1952 1953 dsc = pipe_ctx->stream_res.dsc; 1954 if (dsc) 1955 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1956 1957 snprintf(rd_buf_ptr, str_len, 1958 "%d\n", 1959 dsc_state.dsc_bits_per_pixel); 1960 rd_buf_ptr += str_len; 1961 1962 while (size) { 1963 if (*pos >= rd_buf_size) 1964 break; 1965 1966 r = put_user(*(rd_buf + result), buf); 1967 if (r) { 1968 kfree(rd_buf); 1969 return r; /* r = -EFAULT */ 1970 } 1971 1972 buf += 1; 1973 size -= 1; 1974 *pos += 1; 1975 result += 1; 1976 } 1977 1978 kfree(rd_buf); 1979 return result; 1980 } 1981 1982 /* function: write DSC target rate in bits per pixel 1983 * 1984 * The write function: dp_dsc_bits_per_pixel_write 1985 * overwrites automatically generated DSC configuration 1986 * of DSC target bit rate. 1987 * 1988 * Also the user has to write bpp in hexidecimal 1989 * rather than in decimal. 1990 * 1991 * Writing DSC settings is done with the following command: 1992 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1993 * 1994 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1995 * 1996 * - To stop overwriting and let driver find the optimal rate, 1997 * set the rate to zero: 1998 * 1999 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2000 * 2001 */ 2002 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2003 size_t size, loff_t *pos) 2004 { 2005 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2006 struct drm_connector *connector = &aconnector->base; 2007 struct drm_device *dev = connector->dev; 2008 struct drm_crtc *crtc = NULL; 2009 struct dm_crtc_state *dm_crtc_state = NULL; 2010 struct pipe_ctx *pipe_ctx; 2011 int i; 2012 char *wr_buf = NULL; 2013 uint32_t wr_buf_size = 42; 2014 int max_param_num = 1; 2015 uint8_t param_nums = 0; 2016 long param[1] = {0}; 2017 2018 if (size == 0) 2019 return -EINVAL; 2020 2021 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2022 2023 if (!wr_buf) { 2024 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2025 return -ENOSPC; 2026 } 2027 2028 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2029 (long *)param, buf, 2030 max_param_num, 2031 ¶m_nums)) { 2032 kfree(wr_buf); 2033 return -EINVAL; 2034 } 2035 2036 if (param_nums <= 0) { 2037 DRM_DEBUG_DRIVER("user data not be read\n"); 2038 kfree(wr_buf); 2039 return -EINVAL; 2040 } 2041 2042 for (i = 0; i < MAX_PIPES; i++) { 2043 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2044 if (pipe_ctx && pipe_ctx->stream && 2045 pipe_ctx->stream->link == aconnector->dc_link) 2046 break; 2047 } 2048 2049 if (!pipe_ctx || !pipe_ctx->stream) 2050 goto done; 2051 2052 // Get CRTC state 2053 mutex_lock(&dev->mode_config.mutex); 2054 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2055 2056 if (connector->state == NULL) 2057 goto unlock; 2058 2059 crtc = connector->state->crtc; 2060 if (crtc == NULL) 2061 goto unlock; 2062 2063 drm_modeset_lock(&crtc->mutex, NULL); 2064 if (crtc->state == NULL) 2065 goto unlock; 2066 2067 dm_crtc_state = to_dm_crtc_state(crtc->state); 2068 if (dm_crtc_state->stream == NULL) 2069 goto unlock; 2070 2071 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2072 2073 dm_crtc_state->dsc_force_changed = true; 2074 2075 unlock: 2076 if (crtc) 2077 drm_modeset_unlock(&crtc->mutex); 2078 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2079 mutex_unlock(&dev->mode_config.mutex); 2080 2081 done: 2082 kfree(wr_buf); 2083 return size; 2084 } 2085 2086 /* function: read DSC picture width parameter on the connector 2087 * 2088 * The read function: dp_dsc_pic_width_read 2089 * returns dsc picture width used in the current configuration 2090 * It is the same as h_addressable of the current 2091 * display's timing 2092 * The return is an integer: 0 or other positive integer 2093 * If 0 then DSC is disabled. 2094 * 2095 * Access it with the following command: 2096 * 2097 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2098 * 2099 * 0 - means that DSC is disabled 2100 */ 2101 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2102 size_t size, loff_t *pos) 2103 { 2104 char *rd_buf = NULL; 2105 char *rd_buf_ptr = NULL; 2106 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2107 struct display_stream_compressor *dsc; 2108 struct dcn_dsc_state dsc_state = {0}; 2109 const uint32_t rd_buf_size = 100; 2110 struct pipe_ctx *pipe_ctx; 2111 ssize_t result = 0; 2112 int i, r, str_len = 30; 2113 2114 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2115 2116 if (!rd_buf) 2117 return -ENOMEM; 2118 2119 rd_buf_ptr = rd_buf; 2120 2121 for (i = 0; i < MAX_PIPES; i++) { 2122 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2123 if (pipe_ctx && pipe_ctx->stream && 2124 pipe_ctx->stream->link == aconnector->dc_link) 2125 break; 2126 } 2127 2128 if (!pipe_ctx) { 2129 kfree(rd_buf); 2130 return -ENXIO; 2131 } 2132 2133 dsc = pipe_ctx->stream_res.dsc; 2134 if (dsc) 2135 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2136 2137 snprintf(rd_buf_ptr, str_len, 2138 "%d\n", 2139 dsc_state.dsc_pic_width); 2140 rd_buf_ptr += str_len; 2141 2142 while (size) { 2143 if (*pos >= rd_buf_size) 2144 break; 2145 2146 r = put_user(*(rd_buf + result), buf); 2147 if (r) { 2148 kfree(rd_buf); 2149 return r; /* r = -EFAULT */ 2150 } 2151 2152 buf += 1; 2153 size -= 1; 2154 *pos += 1; 2155 result += 1; 2156 } 2157 2158 kfree(rd_buf); 2159 return result; 2160 } 2161 2162 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2163 size_t size, loff_t *pos) 2164 { 2165 char *rd_buf = NULL; 2166 char *rd_buf_ptr = NULL; 2167 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2168 struct display_stream_compressor *dsc; 2169 struct dcn_dsc_state dsc_state = {0}; 2170 const uint32_t rd_buf_size = 100; 2171 struct pipe_ctx *pipe_ctx; 2172 ssize_t result = 0; 2173 int i, r, str_len = 30; 2174 2175 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2176 2177 if (!rd_buf) 2178 return -ENOMEM; 2179 2180 rd_buf_ptr = rd_buf; 2181 2182 for (i = 0; i < MAX_PIPES; i++) { 2183 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2184 if (pipe_ctx && pipe_ctx->stream && 2185 pipe_ctx->stream->link == aconnector->dc_link) 2186 break; 2187 } 2188 2189 if (!pipe_ctx) { 2190 kfree(rd_buf); 2191 return -ENXIO; 2192 } 2193 2194 dsc = pipe_ctx->stream_res.dsc; 2195 if (dsc) 2196 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2197 2198 snprintf(rd_buf_ptr, str_len, 2199 "%d\n", 2200 dsc_state.dsc_pic_height); 2201 rd_buf_ptr += str_len; 2202 2203 while (size) { 2204 if (*pos >= rd_buf_size) 2205 break; 2206 2207 r = put_user(*(rd_buf + result), buf); 2208 if (r) { 2209 kfree(rd_buf); 2210 return r; /* r = -EFAULT */ 2211 } 2212 2213 buf += 1; 2214 size -= 1; 2215 *pos += 1; 2216 result += 1; 2217 } 2218 2219 kfree(rd_buf); 2220 return result; 2221 } 2222 2223 /* function: read DSC chunk size parameter on the connector 2224 * 2225 * The read function: dp_dsc_chunk_size_read 2226 * returns dsc chunk size set in the current configuration 2227 * The value is calculated automatically by DSC code 2228 * and depends on slice parameters and bpp target rate 2229 * The return is an integer: 0 or other positive integer 2230 * If 0 then DSC is disabled. 2231 * 2232 * Access it with the following command: 2233 * 2234 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2235 * 2236 * 0 - means that DSC is disabled 2237 */ 2238 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2239 size_t size, loff_t *pos) 2240 { 2241 char *rd_buf = NULL; 2242 char *rd_buf_ptr = NULL; 2243 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2244 struct display_stream_compressor *dsc; 2245 struct dcn_dsc_state dsc_state = {0}; 2246 const uint32_t rd_buf_size = 100; 2247 struct pipe_ctx *pipe_ctx; 2248 ssize_t result = 0; 2249 int i, r, str_len = 30; 2250 2251 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2252 2253 if (!rd_buf) 2254 return -ENOMEM; 2255 2256 rd_buf_ptr = rd_buf; 2257 2258 for (i = 0; i < MAX_PIPES; i++) { 2259 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2260 if (pipe_ctx && pipe_ctx->stream && 2261 pipe_ctx->stream->link == aconnector->dc_link) 2262 break; 2263 } 2264 2265 if (!pipe_ctx) { 2266 kfree(rd_buf); 2267 return -ENXIO; 2268 } 2269 2270 dsc = pipe_ctx->stream_res.dsc; 2271 if (dsc) 2272 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2273 2274 snprintf(rd_buf_ptr, str_len, 2275 "%d\n", 2276 dsc_state.dsc_chunk_size); 2277 rd_buf_ptr += str_len; 2278 2279 while (size) { 2280 if (*pos >= rd_buf_size) 2281 break; 2282 2283 r = put_user(*(rd_buf + result), buf); 2284 if (r) { 2285 kfree(rd_buf); 2286 return r; /* r = -EFAULT */ 2287 } 2288 2289 buf += 1; 2290 size -= 1; 2291 *pos += 1; 2292 result += 1; 2293 } 2294 2295 kfree(rd_buf); 2296 return result; 2297 } 2298 2299 /* function: read DSC slice bpg offset on the connector 2300 * 2301 * The read function: dp_dsc_slice_bpg_offset_read 2302 * returns dsc bpg slice offset set in the current configuration 2303 * The value is calculated automatically by DSC code 2304 * and depends on slice parameters and bpp target rate 2305 * The return is an integer: 0 or other positive integer 2306 * If 0 then DSC is disabled. 2307 * 2308 * Access it with the following command: 2309 * 2310 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2311 * 2312 * 0 - means that DSC is disabled 2313 */ 2314 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2315 size_t size, loff_t *pos) 2316 { 2317 char *rd_buf = NULL; 2318 char *rd_buf_ptr = NULL; 2319 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2320 struct display_stream_compressor *dsc; 2321 struct dcn_dsc_state dsc_state = {0}; 2322 const uint32_t rd_buf_size = 100; 2323 struct pipe_ctx *pipe_ctx; 2324 ssize_t result = 0; 2325 int i, r, str_len = 30; 2326 2327 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2328 2329 if (!rd_buf) 2330 return -ENOMEM; 2331 2332 rd_buf_ptr = rd_buf; 2333 2334 for (i = 0; i < MAX_PIPES; i++) { 2335 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2336 if (pipe_ctx && pipe_ctx->stream && 2337 pipe_ctx->stream->link == aconnector->dc_link) 2338 break; 2339 } 2340 2341 if (!pipe_ctx) { 2342 kfree(rd_buf); 2343 return -ENXIO; 2344 } 2345 2346 dsc = pipe_ctx->stream_res.dsc; 2347 if (dsc) 2348 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2349 2350 snprintf(rd_buf_ptr, str_len, 2351 "%d\n", 2352 dsc_state.dsc_slice_bpg_offset); 2353 rd_buf_ptr += str_len; 2354 2355 while (size) { 2356 if (*pos >= rd_buf_size) 2357 break; 2358 2359 r = put_user(*(rd_buf + result), buf); 2360 if (r) { 2361 kfree(rd_buf); 2362 return r; /* r = -EFAULT */ 2363 } 2364 2365 buf += 1; 2366 size -= 1; 2367 *pos += 1; 2368 result += 1; 2369 } 2370 2371 kfree(rd_buf); 2372 return result; 2373 } 2374 2375 2376 /* 2377 * function description: Read max_requested_bpc property from the connector 2378 * 2379 * Access it with the following command: 2380 * 2381 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2382 * 2383 */ 2384 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2385 size_t size, loff_t *pos) 2386 { 2387 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2388 struct drm_connector *connector = &aconnector->base; 2389 struct drm_device *dev = connector->dev; 2390 struct dm_connector_state *state; 2391 ssize_t result = 0; 2392 char *rd_buf = NULL; 2393 char *rd_buf_ptr = NULL; 2394 const uint32_t rd_buf_size = 10; 2395 int r; 2396 2397 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2398 2399 if (!rd_buf) 2400 return -ENOMEM; 2401 2402 mutex_lock(&dev->mode_config.mutex); 2403 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2404 2405 if (connector->state == NULL) 2406 goto unlock; 2407 2408 state = to_dm_connector_state(connector->state); 2409 2410 rd_buf_ptr = rd_buf; 2411 snprintf(rd_buf_ptr, rd_buf_size, 2412 "%u\n", 2413 state->base.max_requested_bpc); 2414 2415 while (size) { 2416 if (*pos >= rd_buf_size) 2417 break; 2418 2419 r = put_user(*(rd_buf + result), buf); 2420 if (r) { 2421 result = r; /* r = -EFAULT */ 2422 goto unlock; 2423 } 2424 buf += 1; 2425 size -= 1; 2426 *pos += 1; 2427 result += 1; 2428 } 2429 unlock: 2430 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2431 mutex_unlock(&dev->mode_config.mutex); 2432 kfree(rd_buf); 2433 return result; 2434 } 2435 2436 2437 /* 2438 * function description: Set max_requested_bpc property on the connector 2439 * 2440 * This function will not force the input BPC on connector, it will only 2441 * change the max value. This is equivalent to setting max_bpc through 2442 * xrandr. 2443 * 2444 * The BPC value written must be >= 6 and <= 16. Values outside of this 2445 * range will result in errors. 2446 * 2447 * BPC values: 2448 * 0x6 - 6 BPC 2449 * 0x8 - 8 BPC 2450 * 0xa - 10 BPC 2451 * 0xc - 12 BPC 2452 * 0x10 - 16 BPC 2453 * 2454 * Write the max_bpc in the following way: 2455 * 2456 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2457 * 2458 */ 2459 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2460 size_t size, loff_t *pos) 2461 { 2462 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2463 struct drm_connector *connector = &aconnector->base; 2464 struct dm_connector_state *state; 2465 struct drm_device *dev = connector->dev; 2466 char *wr_buf = NULL; 2467 uint32_t wr_buf_size = 42; 2468 int max_param_num = 1; 2469 long param[1] = {0}; 2470 uint8_t param_nums = 0; 2471 2472 if (size == 0) 2473 return -EINVAL; 2474 2475 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2476 2477 if (!wr_buf) { 2478 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2479 return -ENOSPC; 2480 } 2481 2482 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2483 (long *)param, buf, 2484 max_param_num, 2485 ¶m_nums)) { 2486 kfree(wr_buf); 2487 return -EINVAL; 2488 } 2489 2490 if (param_nums <= 0) { 2491 DRM_DEBUG_DRIVER("user data not be read\n"); 2492 kfree(wr_buf); 2493 return -EINVAL; 2494 } 2495 2496 if (param[0] < 6 || param[0] > 16) { 2497 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2498 kfree(wr_buf); 2499 return -EINVAL; 2500 } 2501 2502 mutex_lock(&dev->mode_config.mutex); 2503 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2504 2505 if (connector->state == NULL) 2506 goto unlock; 2507 2508 state = to_dm_connector_state(connector->state); 2509 state->base.max_requested_bpc = param[0]; 2510 unlock: 2511 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2512 mutex_unlock(&dev->mode_config.mutex); 2513 2514 kfree(wr_buf); 2515 return size; 2516 } 2517 2518 /* 2519 * Backlight at this moment. Read only. 2520 * As written to display, taking ABM and backlight lut into account. 2521 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2522 * 2523 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2524 */ 2525 static int current_backlight_show(struct seq_file *m, void *unused) 2526 { 2527 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2528 struct dc_link *link = aconnector->dc_link; 2529 unsigned int backlight; 2530 2531 backlight = dc_link_get_backlight_level(link); 2532 seq_printf(m, "0x%x\n", backlight); 2533 2534 return 0; 2535 } 2536 2537 /* 2538 * Backlight value that is being approached. Read only. 2539 * As written to display, taking ABM and backlight lut into account. 2540 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2541 * 2542 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2543 */ 2544 static int target_backlight_show(struct seq_file *m, void *unused) 2545 { 2546 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2547 struct dc_link *link = aconnector->dc_link; 2548 unsigned int backlight; 2549 2550 backlight = dc_link_get_target_backlight_pwm(link); 2551 seq_printf(m, "0x%x\n", backlight); 2552 2553 return 0; 2554 } 2555 2556 /* 2557 * function description: Determine if the connector is mst connector 2558 * 2559 * This function helps to determine whether a connector is a mst connector. 2560 * - "root" stands for the root connector of the topology 2561 * - "branch" stands for branch device of the topology 2562 * - "end" stands for leaf node connector of the topology 2563 * - "no" stands for the connector is not a device of a mst topology 2564 * Access it with the following command: 2565 * 2566 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2567 * 2568 */ 2569 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2570 { 2571 struct drm_connector *connector = m->private; 2572 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2573 struct drm_dp_mst_topology_mgr *mgr = NULL; 2574 struct drm_dp_mst_port *port = NULL; 2575 char *role = NULL; 2576 2577 mutex_lock(&aconnector->hpd_lock); 2578 2579 if (aconnector->mst_mgr.mst_state) { 2580 role = "root"; 2581 } else if (aconnector->mst_port && 2582 aconnector->mst_port->mst_mgr.mst_state) { 2583 2584 role = "end"; 2585 2586 mgr = &aconnector->mst_port->mst_mgr; 2587 port = aconnector->port; 2588 2589 drm_modeset_lock(&mgr->base.lock, NULL); 2590 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2591 port->mcs) 2592 role = "branch"; 2593 drm_modeset_unlock(&mgr->base.lock); 2594 2595 } else { 2596 role = "no"; 2597 } 2598 2599 seq_printf(m, "%s\n", role); 2600 2601 mutex_unlock(&aconnector->hpd_lock); 2602 2603 return 0; 2604 } 2605 2606 /* 2607 * function description: Read out the mst progress status 2608 * 2609 * This function helps to determine the mst progress status of 2610 * a mst connector. 2611 * 2612 * Access it with the following command: 2613 * 2614 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2615 * 2616 */ 2617 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2618 { 2619 struct drm_connector *connector = m->private; 2620 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2621 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2622 int i; 2623 2624 mutex_lock(&aconnector->hpd_lock); 2625 mutex_lock(&adev->dm.dc_lock); 2626 2627 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2628 seq_puts(m, "disabled\n"); 2629 } else { 2630 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2631 seq_printf(m, "%s:%s\n", 2632 mst_progress_status[i], 2633 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2634 } 2635 2636 mutex_unlock(&adev->dm.dc_lock); 2637 mutex_unlock(&aconnector->hpd_lock); 2638 2639 return 0; 2640 } 2641 2642 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2643 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2644 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2645 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2646 #ifdef CONFIG_DRM_AMD_DC_HDCP 2647 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2648 #endif 2649 DEFINE_SHOW_ATTRIBUTE(internal_display); 2650 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2651 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2652 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2653 2654 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2655 .owner = THIS_MODULE, 2656 .read = dp_dsc_clock_en_read, 2657 .write = dp_dsc_clock_en_write, 2658 .llseek = default_llseek 2659 }; 2660 2661 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2662 .owner = THIS_MODULE, 2663 .read = dp_dsc_slice_width_read, 2664 .write = dp_dsc_slice_width_write, 2665 .llseek = default_llseek 2666 }; 2667 2668 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2669 .owner = THIS_MODULE, 2670 .read = dp_dsc_slice_height_read, 2671 .write = dp_dsc_slice_height_write, 2672 .llseek = default_llseek 2673 }; 2674 2675 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2676 .owner = THIS_MODULE, 2677 .read = dp_dsc_bits_per_pixel_read, 2678 .write = dp_dsc_bits_per_pixel_write, 2679 .llseek = default_llseek 2680 }; 2681 2682 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2683 .owner = THIS_MODULE, 2684 .read = dp_dsc_pic_width_read, 2685 .llseek = default_llseek 2686 }; 2687 2688 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2689 .owner = THIS_MODULE, 2690 .read = dp_dsc_pic_height_read, 2691 .llseek = default_llseek 2692 }; 2693 2694 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2695 .owner = THIS_MODULE, 2696 .read = dp_dsc_chunk_size_read, 2697 .llseek = default_llseek 2698 }; 2699 2700 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2701 .owner = THIS_MODULE, 2702 .read = dp_dsc_slice_bpg_offset_read, 2703 .llseek = default_llseek 2704 }; 2705 2706 static const struct file_operations trigger_hotplug_debugfs_fops = { 2707 .owner = THIS_MODULE, 2708 .write = trigger_hotplug, 2709 .llseek = default_llseek 2710 }; 2711 2712 static const struct file_operations dp_link_settings_debugfs_fops = { 2713 .owner = THIS_MODULE, 2714 .read = dp_link_settings_read, 2715 .write = dp_link_settings_write, 2716 .llseek = default_llseek 2717 }; 2718 2719 static const struct file_operations dp_phy_settings_debugfs_fop = { 2720 .owner = THIS_MODULE, 2721 .read = dp_phy_settings_read, 2722 .write = dp_phy_settings_write, 2723 .llseek = default_llseek 2724 }; 2725 2726 static const struct file_operations dp_phy_test_pattern_fops = { 2727 .owner = THIS_MODULE, 2728 .write = dp_phy_test_pattern_debugfs_write, 2729 .llseek = default_llseek 2730 }; 2731 2732 static const struct file_operations sdp_message_fops = { 2733 .owner = THIS_MODULE, 2734 .write = dp_sdp_message_debugfs_write, 2735 .llseek = default_llseek 2736 }; 2737 2738 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2739 .owner = THIS_MODULE, 2740 .write = dp_dpcd_address_write, 2741 .llseek = default_llseek 2742 }; 2743 2744 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2745 .owner = THIS_MODULE, 2746 .write = dp_dpcd_size_write, 2747 .llseek = default_llseek 2748 }; 2749 2750 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2751 .owner = THIS_MODULE, 2752 .read = dp_dpcd_data_read, 2753 .write = dp_dpcd_data_write, 2754 .llseek = default_llseek 2755 }; 2756 2757 static const struct file_operations dp_max_bpc_debugfs_fops = { 2758 .owner = THIS_MODULE, 2759 .read = dp_max_bpc_read, 2760 .write = dp_max_bpc_write, 2761 .llseek = default_llseek 2762 }; 2763 2764 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2765 .owner = THIS_MODULE, 2766 .write = dp_dsc_passthrough_set, 2767 .llseek = default_llseek 2768 }; 2769 2770 static const struct { 2771 char *name; 2772 const struct file_operations *fops; 2773 } dp_debugfs_entries[] = { 2774 {"link_settings", &dp_link_settings_debugfs_fops}, 2775 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2776 {"lttpr_status", &dp_lttpr_status_fops}, 2777 {"test_pattern", &dp_phy_test_pattern_fops}, 2778 #ifdef CONFIG_DRM_AMD_DC_HDCP 2779 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2780 #endif 2781 {"sdp_message", &sdp_message_fops}, 2782 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2783 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2784 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2785 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2786 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2787 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2788 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2789 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2790 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2791 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2792 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2793 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2794 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2795 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2796 {"is_mst_connector", &dp_is_mst_connector_fops}, 2797 {"mst_progress_status", &dp_mst_progress_status_fops} 2798 }; 2799 2800 #ifdef CONFIG_DRM_AMD_DC_HDCP 2801 static const struct { 2802 char *name; 2803 const struct file_operations *fops; 2804 } hdmi_debugfs_entries[] = { 2805 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2806 }; 2807 #endif 2808 /* 2809 * Force YUV420 output if available from the given mode 2810 */ 2811 static int force_yuv420_output_set(void *data, u64 val) 2812 { 2813 struct amdgpu_dm_connector *connector = data; 2814 2815 connector->force_yuv420_output = (bool)val; 2816 2817 return 0; 2818 } 2819 2820 /* 2821 * Check if YUV420 is forced when available from the given mode 2822 */ 2823 static int force_yuv420_output_get(void *data, u64 *val) 2824 { 2825 struct amdgpu_dm_connector *connector = data; 2826 2827 *val = connector->force_yuv420_output; 2828 2829 return 0; 2830 } 2831 2832 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2833 force_yuv420_output_set, "%llu\n"); 2834 2835 /* 2836 * Read PSR state 2837 */ 2838 static int psr_get(void *data, u64 *val) 2839 { 2840 struct amdgpu_dm_connector *connector = data; 2841 struct dc_link *link = connector->dc_link; 2842 enum dc_psr_state state = PSR_STATE0; 2843 2844 dc_link_get_psr_state(link, &state); 2845 2846 *val = state; 2847 2848 return 0; 2849 } 2850 2851 /* 2852 * Set dmcub trace event IRQ enable or disable. 2853 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2854 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2855 */ 2856 static int dmcub_trace_event_state_set(void *data, u64 val) 2857 { 2858 struct amdgpu_device *adev = data; 2859 2860 if (val == 1 || val == 0) { 2861 dc_dmub_trace_event_control(adev->dm.dc, val); 2862 adev->dm.dmcub_trace_event_en = (bool)val; 2863 } else 2864 return 0; 2865 2866 return 0; 2867 } 2868 2869 /* 2870 * The interface doesn't need get function, so it will return the 2871 * value of zero 2872 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2873 */ 2874 static int dmcub_trace_event_state_get(void *data, u64 *val) 2875 { 2876 struct amdgpu_device *adev = data; 2877 2878 *val = adev->dm.dmcub_trace_event_en; 2879 return 0; 2880 } 2881 2882 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2883 dmcub_trace_event_state_set, "%llu\n"); 2884 2885 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2886 2887 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2888 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2889 2890 static const struct { 2891 char *name; 2892 const struct file_operations *fops; 2893 } connector_debugfs_entries[] = { 2894 {"force_yuv420_output", &force_yuv420_output_fops}, 2895 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2896 {"internal_display", &internal_display_fops} 2897 }; 2898 2899 /* 2900 * Returns supported customized link rates by this eDP panel. 2901 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2902 */ 2903 static int edp_ilr_show(struct seq_file *m, void *unused) 2904 { 2905 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2906 struct dc_link *link = aconnector->dc_link; 2907 uint8_t supported_link_rates[16]; 2908 uint32_t link_rate_in_khz; 2909 uint32_t entry = 0; 2910 uint8_t dpcd_rev; 2911 2912 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2913 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2914 supported_link_rates, sizeof(supported_link_rates)); 2915 2916 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2917 2918 if (dpcd_rev >= DP_DPCD_REV_13 && 2919 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2920 2921 for (entry = 0; entry < 16; entry += 2) { 2922 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2923 supported_link_rates[entry]) * 200; 2924 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2925 } 2926 } else { 2927 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2928 } 2929 2930 return 0; 2931 } 2932 2933 /* 2934 * Set supported customized link rate to eDP panel. 2935 * 2936 * echo <lane_count> <link_rate option> > ilr_setting 2937 * 2938 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2939 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2940 * to set 4 lanes and 2.16 GHz 2941 */ 2942 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2943 size_t size, loff_t *pos) 2944 { 2945 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2946 struct dc_link *link = connector->dc_link; 2947 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2948 struct dc *dc = (struct dc *)link->dc; 2949 struct dc_link_settings prefer_link_settings; 2950 char *wr_buf = NULL; 2951 const uint32_t wr_buf_size = 40; 2952 /* 0: lane_count; 1: link_rate */ 2953 int max_param_num = 2; 2954 uint8_t param_nums = 0; 2955 long param[2]; 2956 bool valid_input = true; 2957 2958 if (size == 0) 2959 return -EINVAL; 2960 2961 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2962 if (!wr_buf) 2963 return -ENOMEM; 2964 2965 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2966 (long *)param, buf, 2967 max_param_num, 2968 ¶m_nums)) { 2969 kfree(wr_buf); 2970 return -EINVAL; 2971 } 2972 2973 if (param_nums <= 0) { 2974 kfree(wr_buf); 2975 return -EINVAL; 2976 } 2977 2978 switch (param[0]) { 2979 case LANE_COUNT_ONE: 2980 case LANE_COUNT_TWO: 2981 case LANE_COUNT_FOUR: 2982 break; 2983 default: 2984 valid_input = false; 2985 break; 2986 } 2987 2988 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2989 valid_input = false; 2990 2991 if (!valid_input) { 2992 kfree(wr_buf); 2993 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2994 prefer_link_settings.use_link_rate_set = false; 2995 mutex_lock(&adev->dm.dc_lock); 2996 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2997 mutex_unlock(&adev->dm.dc_lock); 2998 return size; 2999 } 3000 3001 /* save user force lane_count, link_rate to preferred settings 3002 * spread spectrum will not be changed 3003 */ 3004 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3005 prefer_link_settings.lane_count = param[0]; 3006 prefer_link_settings.use_link_rate_set = true; 3007 prefer_link_settings.link_rate_set = param[1]; 3008 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3009 3010 mutex_lock(&adev->dm.dc_lock); 3011 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3012 NULL, link, false); 3013 mutex_unlock(&adev->dm.dc_lock); 3014 3015 kfree(wr_buf); 3016 return size; 3017 } 3018 3019 static int edp_ilr_open(struct inode *inode, struct file *file) 3020 { 3021 return single_open(file, edp_ilr_show, inode->i_private); 3022 } 3023 3024 static const struct file_operations edp_ilr_debugfs_fops = { 3025 .owner = THIS_MODULE, 3026 .open = edp_ilr_open, 3027 .read = seq_read, 3028 .llseek = seq_lseek, 3029 .release = single_release, 3030 .write = edp_ilr_write 3031 }; 3032 3033 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3034 { 3035 int i; 3036 struct dentry *dir = connector->base.debugfs_entry; 3037 3038 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3039 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3040 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3041 debugfs_create_file(dp_debugfs_entries[i].name, 3042 0644, dir, connector, 3043 dp_debugfs_entries[i].fops); 3044 } 3045 } 3046 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3047 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3048 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3049 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3050 ¤t_backlight_fops); 3051 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3052 &target_backlight_fops); 3053 debugfs_create_file("ilr_setting", 0644, dir, connector, 3054 &edp_ilr_debugfs_fops); 3055 } 3056 3057 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3058 debugfs_create_file(connector_debugfs_entries[i].name, 3059 0644, dir, connector, 3060 connector_debugfs_entries[i].fops); 3061 } 3062 3063 connector->debugfs_dpcd_address = 0; 3064 connector->debugfs_dpcd_size = 0; 3065 3066 #ifdef CONFIG_DRM_AMD_DC_HDCP 3067 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3068 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3069 debugfs_create_file(hdmi_debugfs_entries[i].name, 3070 0644, dir, connector, 3071 hdmi_debugfs_entries[i].fops); 3072 } 3073 } 3074 #endif 3075 } 3076 3077 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3078 /* 3079 * Set crc window coordinate x start 3080 */ 3081 static int crc_win_x_start_set(void *data, u64 val) 3082 { 3083 struct drm_crtc *crtc = data; 3084 struct drm_device *drm_dev = crtc->dev; 3085 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3086 3087 spin_lock_irq(&drm_dev->event_lock); 3088 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; 3089 acrtc->dm_irq_params.window_param.update_win = false; 3090 spin_unlock_irq(&drm_dev->event_lock); 3091 3092 return 0; 3093 } 3094 3095 /* 3096 * Get crc window coordinate x start 3097 */ 3098 static int crc_win_x_start_get(void *data, u64 *val) 3099 { 3100 struct drm_crtc *crtc = data; 3101 struct drm_device *drm_dev = crtc->dev; 3102 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3103 3104 spin_lock_irq(&drm_dev->event_lock); 3105 *val = acrtc->dm_irq_params.window_param.x_start; 3106 spin_unlock_irq(&drm_dev->event_lock); 3107 3108 return 0; 3109 } 3110 3111 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3112 crc_win_x_start_set, "%llu\n"); 3113 3114 3115 /* 3116 * Set crc window coordinate y start 3117 */ 3118 static int crc_win_y_start_set(void *data, u64 val) 3119 { 3120 struct drm_crtc *crtc = data; 3121 struct drm_device *drm_dev = crtc->dev; 3122 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3123 3124 spin_lock_irq(&drm_dev->event_lock); 3125 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; 3126 acrtc->dm_irq_params.window_param.update_win = false; 3127 spin_unlock_irq(&drm_dev->event_lock); 3128 3129 return 0; 3130 } 3131 3132 /* 3133 * Get crc window coordinate y start 3134 */ 3135 static int crc_win_y_start_get(void *data, u64 *val) 3136 { 3137 struct drm_crtc *crtc = data; 3138 struct drm_device *drm_dev = crtc->dev; 3139 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3140 3141 spin_lock_irq(&drm_dev->event_lock); 3142 *val = acrtc->dm_irq_params.window_param.y_start; 3143 spin_unlock_irq(&drm_dev->event_lock); 3144 3145 return 0; 3146 } 3147 3148 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3149 crc_win_y_start_set, "%llu\n"); 3150 3151 /* 3152 * Set crc window coordinate x end 3153 */ 3154 static int crc_win_x_end_set(void *data, u64 val) 3155 { 3156 struct drm_crtc *crtc = data; 3157 struct drm_device *drm_dev = crtc->dev; 3158 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3159 3160 spin_lock_irq(&drm_dev->event_lock); 3161 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; 3162 acrtc->dm_irq_params.window_param.update_win = false; 3163 spin_unlock_irq(&drm_dev->event_lock); 3164 3165 return 0; 3166 } 3167 3168 /* 3169 * Get crc window coordinate x end 3170 */ 3171 static int crc_win_x_end_get(void *data, u64 *val) 3172 { 3173 struct drm_crtc *crtc = data; 3174 struct drm_device *drm_dev = crtc->dev; 3175 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3176 3177 spin_lock_irq(&drm_dev->event_lock); 3178 *val = acrtc->dm_irq_params.window_param.x_end; 3179 spin_unlock_irq(&drm_dev->event_lock); 3180 3181 return 0; 3182 } 3183 3184 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3185 crc_win_x_end_set, "%llu\n"); 3186 3187 /* 3188 * Set crc window coordinate y end 3189 */ 3190 static int crc_win_y_end_set(void *data, u64 val) 3191 { 3192 struct drm_crtc *crtc = data; 3193 struct drm_device *drm_dev = crtc->dev; 3194 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3195 3196 spin_lock_irq(&drm_dev->event_lock); 3197 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; 3198 acrtc->dm_irq_params.window_param.update_win = false; 3199 spin_unlock_irq(&drm_dev->event_lock); 3200 3201 return 0; 3202 } 3203 3204 /* 3205 * Get crc window coordinate y end 3206 */ 3207 static int crc_win_y_end_get(void *data, u64 *val) 3208 { 3209 struct drm_crtc *crtc = data; 3210 struct drm_device *drm_dev = crtc->dev; 3211 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3212 3213 spin_lock_irq(&drm_dev->event_lock); 3214 *val = acrtc->dm_irq_params.window_param.y_end; 3215 spin_unlock_irq(&drm_dev->event_lock); 3216 3217 return 0; 3218 } 3219 3220 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3221 crc_win_y_end_set, "%llu\n"); 3222 /* 3223 * Trigger to commit crc window 3224 */ 3225 static int crc_win_update_set(void *data, u64 val) 3226 { 3227 struct drm_crtc *new_crtc = data; 3228 struct drm_crtc *old_crtc = NULL; 3229 struct amdgpu_crtc *new_acrtc, *old_acrtc; 3230 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 3231 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 3232 3233 if (!crc_rd_wrk) 3234 return 0; 3235 3236 if (val) { 3237 new_acrtc = to_amdgpu_crtc(new_crtc); 3238 mutex_lock(&adev->dm.dc_lock); 3239 /* PSR may write to OTG CRC window control register, 3240 * so close it before starting secure_display. 3241 */ 3242 amdgpu_dm_psr_disable(new_acrtc->dm_irq_params.stream); 3243 3244 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3245 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 3246 if (crc_rd_wrk->crtc) { 3247 old_crtc = crc_rd_wrk->crtc; 3248 old_acrtc = to_amdgpu_crtc(old_crtc); 3249 } 3250 3251 if (old_crtc && old_crtc != new_crtc) { 3252 old_acrtc->dm_irq_params.window_param.activated = false; 3253 old_acrtc->dm_irq_params.window_param.update_win = false; 3254 old_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3255 3256 new_acrtc->dm_irq_params.window_param.activated = true; 3257 new_acrtc->dm_irq_params.window_param.update_win = true; 3258 new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3259 crc_rd_wrk->crtc = new_crtc; 3260 } else { 3261 new_acrtc->dm_irq_params.window_param.activated = true; 3262 new_acrtc->dm_irq_params.window_param.update_win = true; 3263 new_acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 3264 crc_rd_wrk->crtc = new_crtc; 3265 } 3266 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 3267 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3268 mutex_unlock(&adev->dm.dc_lock); 3269 } 3270 3271 return 0; 3272 } 3273 3274 /* 3275 * Get crc window update flag 3276 */ 3277 static int crc_win_update_get(void *data, u64 *val) 3278 { 3279 *val = 0; 3280 return 0; 3281 } 3282 3283 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3284 crc_win_update_set, "%llu\n"); 3285 #endif 3286 void crtc_debugfs_init(struct drm_crtc *crtc) 3287 { 3288 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3289 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3290 3291 if (!dir) 3292 return; 3293 3294 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3295 &crc_win_x_start_fops); 3296 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3297 &crc_win_y_start_fops); 3298 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3299 &crc_win_x_end_fops); 3300 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3301 &crc_win_y_end_fops); 3302 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3303 &crc_win_update_fops); 3304 dput(dir); 3305 #endif 3306 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 3307 crtc, &amdgpu_current_bpc_fops); 3308 } 3309 3310 /* 3311 * Writes DTN log state to the user supplied buffer. 3312 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3313 */ 3314 static ssize_t dtn_log_read( 3315 struct file *f, 3316 char __user *buf, 3317 size_t size, 3318 loff_t *pos) 3319 { 3320 struct amdgpu_device *adev = file_inode(f)->i_private; 3321 struct dc *dc = adev->dm.dc; 3322 struct dc_log_buffer_ctx log_ctx = { 0 }; 3323 ssize_t result = 0; 3324 3325 if (!buf || !size) 3326 return -EINVAL; 3327 3328 if (!dc->hwss.log_hw_state) 3329 return 0; 3330 3331 dc->hwss.log_hw_state(dc, &log_ctx); 3332 3333 if (*pos < log_ctx.pos) { 3334 size_t to_copy = log_ctx.pos - *pos; 3335 3336 to_copy = min(to_copy, size); 3337 3338 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3339 *pos += to_copy; 3340 result = to_copy; 3341 } 3342 } 3343 3344 kfree(log_ctx.buf); 3345 3346 return result; 3347 } 3348 3349 /* 3350 * Writes DTN log state to dmesg when triggered via a write. 3351 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3352 */ 3353 static ssize_t dtn_log_write( 3354 struct file *f, 3355 const char __user *buf, 3356 size_t size, 3357 loff_t *pos) 3358 { 3359 struct amdgpu_device *adev = file_inode(f)->i_private; 3360 struct dc *dc = adev->dm.dc; 3361 3362 /* Write triggers log output via dmesg. */ 3363 if (size == 0) 3364 return 0; 3365 3366 if (dc->hwss.log_hw_state) 3367 dc->hwss.log_hw_state(dc, NULL); 3368 3369 return size; 3370 } 3371 3372 static int mst_topo_show(struct seq_file *m, void *unused) 3373 { 3374 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3375 struct drm_device *dev = adev_to_drm(adev); 3376 struct drm_connector *connector; 3377 struct drm_connector_list_iter conn_iter; 3378 struct amdgpu_dm_connector *aconnector; 3379 3380 drm_connector_list_iter_begin(dev, &conn_iter); 3381 drm_for_each_connector_iter(connector, &conn_iter) { 3382 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3383 continue; 3384 3385 aconnector = to_amdgpu_dm_connector(connector); 3386 3387 /* Ensure we're only dumping the topology of a root mst node */ 3388 if (!aconnector->mst_mgr.mst_state) 3389 continue; 3390 3391 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3392 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3393 } 3394 drm_connector_list_iter_end(&conn_iter); 3395 3396 return 0; 3397 } 3398 3399 /* 3400 * Sets trigger hpd for MST topologies. 3401 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3402 * All topologies will be disconnected if val of 0 is set . 3403 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3404 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3405 */ 3406 static int trigger_hpd_mst_set(void *data, u64 val) 3407 { 3408 struct amdgpu_device *adev = data; 3409 struct drm_device *dev = adev_to_drm(adev); 3410 struct drm_connector_list_iter iter; 3411 struct amdgpu_dm_connector *aconnector; 3412 struct drm_connector *connector; 3413 struct dc_link *link = NULL; 3414 3415 if (val == 1) { 3416 drm_connector_list_iter_begin(dev, &iter); 3417 drm_for_each_connector_iter(connector, &iter) { 3418 aconnector = to_amdgpu_dm_connector(connector); 3419 if (aconnector->dc_link->type == dc_connection_mst_branch && 3420 aconnector->mst_mgr.aux) { 3421 mutex_lock(&adev->dm.dc_lock); 3422 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3423 mutex_unlock(&adev->dm.dc_lock); 3424 3425 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3426 } 3427 } 3428 } else if (val == 0) { 3429 drm_connector_list_iter_begin(dev, &iter); 3430 drm_for_each_connector_iter(connector, &iter) { 3431 aconnector = to_amdgpu_dm_connector(connector); 3432 if (!aconnector->dc_link) 3433 continue; 3434 3435 if (!aconnector->mst_port) 3436 continue; 3437 3438 link = aconnector->dc_link; 3439 dp_receiver_power_ctrl(link, false); 3440 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3441 link->mst_stream_alloc_table.stream_count = 0; 3442 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3443 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3444 } 3445 } else { 3446 return 0; 3447 } 3448 drm_kms_helper_hotplug_event(dev); 3449 3450 return 0; 3451 } 3452 3453 /* 3454 * The interface doesn't need get function, so it will return the 3455 * value of zero 3456 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3457 */ 3458 static int trigger_hpd_mst_get(void *data, u64 *val) 3459 { 3460 *val = 0; 3461 return 0; 3462 } 3463 3464 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3465 trigger_hpd_mst_set, "%llu\n"); 3466 3467 3468 /* 3469 * Sets the force_timing_sync debug option from the given string. 3470 * All connected displays will be force synchronized immediately. 3471 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3472 */ 3473 static int force_timing_sync_set(void *data, u64 val) 3474 { 3475 struct amdgpu_device *adev = data; 3476 3477 adev->dm.force_timing_sync = (bool)val; 3478 3479 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3480 3481 return 0; 3482 } 3483 3484 /* 3485 * Gets the force_timing_sync debug option value into the given buffer. 3486 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3487 */ 3488 static int force_timing_sync_get(void *data, u64 *val) 3489 { 3490 struct amdgpu_device *adev = data; 3491 3492 *val = adev->dm.force_timing_sync; 3493 3494 return 0; 3495 } 3496 3497 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3498 force_timing_sync_set, "%llu\n"); 3499 3500 3501 /* 3502 * Disables all HPD and HPD RX interrupt handling in the 3503 * driver when set to 1. Default is 0. 3504 */ 3505 static int disable_hpd_set(void *data, u64 val) 3506 { 3507 struct amdgpu_device *adev = data; 3508 3509 adev->dm.disable_hpd_irq = (bool)val; 3510 3511 return 0; 3512 } 3513 3514 3515 /* 3516 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3517 * 0 otherwise. 3518 */ 3519 static int disable_hpd_get(void *data, u64 *val) 3520 { 3521 struct amdgpu_device *adev = data; 3522 3523 *val = adev->dm.disable_hpd_irq; 3524 3525 return 0; 3526 } 3527 3528 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3529 disable_hpd_set, "%llu\n"); 3530 3531 /* 3532 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3533 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3534 */ 3535 static int dp_force_sst_set(void *data, u64 val) 3536 { 3537 struct amdgpu_device *adev = data; 3538 3539 adev->dm.dc->debug.set_mst_en_for_sst = val; 3540 3541 return 0; 3542 } 3543 3544 static int dp_force_sst_get(void *data, u64 *val) 3545 { 3546 struct amdgpu_device *adev = data; 3547 3548 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3549 3550 return 0; 3551 } 3552 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3553 dp_force_sst_set, "%llu\n"); 3554 3555 /* 3556 * Force DP2 sequence without VESA certified cable. 3557 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3558 */ 3559 static int dp_ignore_cable_id_set(void *data, u64 val) 3560 { 3561 struct amdgpu_device *adev = data; 3562 3563 adev->dm.dc->debug.ignore_cable_id = val; 3564 3565 return 0; 3566 } 3567 3568 static int dp_ignore_cable_id_get(void *data, u64 *val) 3569 { 3570 struct amdgpu_device *adev = data; 3571 3572 *val = adev->dm.dc->debug.ignore_cable_id; 3573 3574 return 0; 3575 } 3576 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3577 dp_ignore_cable_id_set, "%llu\n"); 3578 3579 /* 3580 * Sets the DC visual confirm debug option from the given string. 3581 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3582 */ 3583 static int visual_confirm_set(void *data, u64 val) 3584 { 3585 struct amdgpu_device *adev = data; 3586 3587 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3588 3589 return 0; 3590 } 3591 3592 /* 3593 * Reads the DC visual confirm debug option value into the given buffer. 3594 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3595 */ 3596 static int visual_confirm_get(void *data, u64 *val) 3597 { 3598 struct amdgpu_device *adev = data; 3599 3600 *val = adev->dm.dc->debug.visual_confirm; 3601 3602 return 0; 3603 } 3604 3605 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3606 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3607 visual_confirm_set, "%llu\n"); 3608 3609 3610 /* 3611 * Sets the DC skip_detection_link_training debug option from the given string. 3612 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 3613 */ 3614 static int skip_detection_link_training_set(void *data, u64 val) 3615 { 3616 struct amdgpu_device *adev = data; 3617 3618 if (val == 0) 3619 adev->dm.dc->debug.skip_detection_link_training = false; 3620 else 3621 adev->dm.dc->debug.skip_detection_link_training = true; 3622 3623 return 0; 3624 } 3625 3626 /* 3627 * Reads the DC skip_detection_link_training debug option value into the given buffer. 3628 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 3629 */ 3630 static int skip_detection_link_training_get(void *data, u64 *val) 3631 { 3632 struct amdgpu_device *adev = data; 3633 3634 *val = adev->dm.dc->debug.skip_detection_link_training; 3635 3636 return 0; 3637 } 3638 3639 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 3640 skip_detection_link_training_get, 3641 skip_detection_link_training_set, "%llu\n"); 3642 3643 /* 3644 * Dumps the DCC_EN bit for each pipe. 3645 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3646 */ 3647 static ssize_t dcc_en_bits_read( 3648 struct file *f, 3649 char __user *buf, 3650 size_t size, 3651 loff_t *pos) 3652 { 3653 struct amdgpu_device *adev = file_inode(f)->i_private; 3654 struct dc *dc = adev->dm.dc; 3655 char *rd_buf = NULL; 3656 const uint32_t rd_buf_size = 32; 3657 uint32_t result = 0; 3658 int offset = 0; 3659 int num_pipes = dc->res_pool->pipe_count; 3660 int *dcc_en_bits; 3661 int i, r; 3662 3663 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3664 if (!dcc_en_bits) 3665 return -ENOMEM; 3666 3667 if (!dc->hwss.get_dcc_en_bits) { 3668 kfree(dcc_en_bits); 3669 return 0; 3670 } 3671 3672 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3673 3674 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3675 if (!rd_buf) { 3676 kfree(dcc_en_bits); 3677 return -ENOMEM; 3678 } 3679 3680 for (i = 0; i < num_pipes; i++) 3681 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3682 "%d ", dcc_en_bits[i]); 3683 rd_buf[strlen(rd_buf)] = '\n'; 3684 3685 kfree(dcc_en_bits); 3686 3687 while (size) { 3688 if (*pos >= rd_buf_size) 3689 break; 3690 r = put_user(*(rd_buf + result), buf); 3691 if (r) { 3692 kfree(rd_buf); 3693 return r; /* r = -EFAULT */ 3694 } 3695 buf += 1; 3696 size -= 1; 3697 *pos += 1; 3698 result += 1; 3699 } 3700 3701 kfree(rd_buf); 3702 return result; 3703 } 3704 3705 void dtn_debugfs_init(struct amdgpu_device *adev) 3706 { 3707 static const struct file_operations dtn_log_fops = { 3708 .owner = THIS_MODULE, 3709 .read = dtn_log_read, 3710 .write = dtn_log_write, 3711 .llseek = default_llseek 3712 }; 3713 static const struct file_operations dcc_en_bits_fops = { 3714 .owner = THIS_MODULE, 3715 .read = dcc_en_bits_read, 3716 .llseek = default_llseek 3717 }; 3718 3719 struct drm_minor *minor = adev_to_drm(adev)->primary; 3720 struct dentry *root = minor->debugfs_root; 3721 3722 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3723 adev, &mst_topo_fops); 3724 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3725 &dtn_log_fops); 3726 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3727 &dp_set_mst_en_for_sst_ops); 3728 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3729 &dp_ignore_cable_id_ops); 3730 3731 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3732 &visual_confirm_fops); 3733 3734 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 3735 &skip_detection_link_training_fops); 3736 3737 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3738 adev, &dmub_tracebuffer_fops); 3739 3740 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3741 adev, &dmub_fw_state_fops); 3742 3743 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3744 adev, &force_timing_sync_ops); 3745 3746 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3747 adev, &dmcub_trace_event_state_fops); 3748 3749 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3750 adev, &trigger_hpd_mst_ops); 3751 3752 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3753 &dcc_en_bits_fops); 3754 3755 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3756 &disable_hpd_ops); 3757 3758 } 3759