1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/string_helpers.h> 27 #include <linux/uaccess.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm.h" 32 #include "amdgpu_dm_debugfs.h" 33 #include "dm_helpers.h" 34 #include "dmub/dmub_srv.h" 35 #include "resource.h" 36 #include "dsc.h" 37 #include "dc_link_dp.h" 38 #include "link_hwss.h" 39 #include "dc/dc_dmub_srv.h" 40 41 struct dmub_debugfs_trace_header { 42 uint32_t entry_count; 43 uint32_t reserved[3]; 44 }; 45 46 struct dmub_debugfs_trace_entry { 47 uint32_t trace_code; 48 uint32_t tick_count; 49 uint32_t param0; 50 uint32_t param1; 51 }; 52 53 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 54 * 55 * Function takes in attributes passed to debugfs write entry 56 * and writes into param array. 57 * The user passes max_param_num to identify maximum number of 58 * parameters that could be parsed. 59 * 60 */ 61 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 62 long *param, const char __user *buf, 63 int max_param_num, 64 uint8_t *param_nums) 65 { 66 char *wr_buf_ptr = NULL; 67 uint32_t wr_buf_count = 0; 68 int r; 69 char *sub_str = NULL; 70 const char delimiter[3] = {' ', '\n', '\0'}; 71 uint8_t param_index = 0; 72 73 *param_nums = 0; 74 75 wr_buf_ptr = wr_buf; 76 77 /* r is bytes not be copied */ 78 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 79 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 80 return -EFAULT; 81 } 82 83 /* check number of parameters. isspace could not differ space and \n */ 84 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 85 /* skip space*/ 86 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 87 wr_buf_ptr++; 88 wr_buf_count++; 89 } 90 91 if (wr_buf_count == wr_buf_size) 92 break; 93 94 /* skip non-space*/ 95 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 96 wr_buf_ptr++; 97 wr_buf_count++; 98 } 99 100 (*param_nums)++; 101 102 if (wr_buf_count == wr_buf_size) 103 break; 104 } 105 106 if (*param_nums > max_param_num) 107 *param_nums = max_param_num; 108 109 wr_buf_ptr = wr_buf; /* reset buf pointer */ 110 wr_buf_count = 0; /* number of char already checked */ 111 112 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 113 wr_buf_ptr++; 114 wr_buf_count++; 115 } 116 117 while (param_index < *param_nums) { 118 /* after strsep, wr_buf_ptr will be moved to after space */ 119 sub_str = strsep(&wr_buf_ptr, delimiter); 120 121 r = kstrtol(sub_str, 16, &(param[param_index])); 122 123 if (r) 124 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 125 126 param_index++; 127 } 128 129 return 0; 130 } 131 132 /* function description 133 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 134 * 135 * valid lane count value: 1, 2, 4 136 * valid link rate value: 137 * 06h = 1.62Gbps per lane 138 * 0Ah = 2.7Gbps per lane 139 * 0Ch = 3.24Gbps per lane 140 * 14h = 5.4Gbps per lane 141 * 1Eh = 8.1Gbps per lane 142 * 143 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 144 * 145 * --- to get dp configuration 146 * 147 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 148 * 149 * It will list current, verified, reported, preferred dp configuration. 150 * current -- for current video mode 151 * verified --- maximum configuration which pass link training 152 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 153 * preferred --- user force settings 154 * 155 * --- set (or force) dp configuration 156 * 157 * echo <lane_count> <link_rate> > link_settings 158 * 159 * for example, to force to 2 lane, 2.7GHz, 160 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * spread_spectrum could not be changed dynamically. 163 * 164 * in case invalid lane count, link rate are force, no hw programming will be 165 * done. please check link settings after force operation to see if HW get 166 * programming. 167 * 168 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 169 * 170 * check current and preferred settings. 171 * 172 */ 173 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 174 size_t size, loff_t *pos) 175 { 176 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 177 struct dc_link *link = connector->dc_link; 178 char *rd_buf = NULL; 179 char *rd_buf_ptr = NULL; 180 const uint32_t rd_buf_size = 100; 181 uint32_t result = 0; 182 uint8_t str_len = 0; 183 int r; 184 185 if (*pos & 3 || size & 3) 186 return -EINVAL; 187 188 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 189 if (!rd_buf) 190 return 0; 191 192 rd_buf_ptr = rd_buf; 193 194 str_len = strlen("Current: %d 0x%x %d "); 195 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 196 link->cur_link_settings.lane_count, 197 link->cur_link_settings.link_rate, 198 link->cur_link_settings.link_spread); 199 rd_buf_ptr += str_len; 200 201 str_len = strlen("Verified: %d 0x%x %d "); 202 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 203 link->verified_link_cap.lane_count, 204 link->verified_link_cap.link_rate, 205 link->verified_link_cap.link_spread); 206 rd_buf_ptr += str_len; 207 208 str_len = strlen("Reported: %d 0x%x %d "); 209 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 210 link->reported_link_cap.lane_count, 211 link->reported_link_cap.link_rate, 212 link->reported_link_cap.link_spread); 213 rd_buf_ptr += str_len; 214 215 str_len = strlen("Preferred: %d 0x%x %d "); 216 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 217 link->preferred_link_setting.lane_count, 218 link->preferred_link_setting.link_rate, 219 link->preferred_link_setting.link_spread); 220 221 while (size) { 222 if (*pos >= rd_buf_size) 223 break; 224 225 r = put_user(*(rd_buf + result), buf); 226 if (r) { 227 kfree(rd_buf); 228 return r; /* r = -EFAULT */ 229 } 230 231 buf += 1; 232 size -= 1; 233 *pos += 1; 234 result += 1; 235 } 236 237 kfree(rd_buf); 238 return result; 239 } 240 241 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 242 size_t size, loff_t *pos) 243 { 244 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 245 struct dc_link *link = connector->dc_link; 246 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 247 struct dc *dc = (struct dc *)link->dc; 248 struct dc_link_settings prefer_link_settings; 249 char *wr_buf = NULL; 250 const uint32_t wr_buf_size = 40; 251 /* 0: lane_count; 1: link_rate */ 252 int max_param_num = 2; 253 uint8_t param_nums = 0; 254 long param[2]; 255 bool valid_input = true; 256 257 if (size == 0) 258 return -EINVAL; 259 260 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 261 if (!wr_buf) 262 return -ENOSPC; 263 264 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 265 (long *)param, buf, 266 max_param_num, 267 ¶m_nums)) { 268 kfree(wr_buf); 269 return -EINVAL; 270 } 271 272 if (param_nums <= 0) { 273 kfree(wr_buf); 274 DRM_DEBUG_DRIVER("user data not be read\n"); 275 return -EINVAL; 276 } 277 278 switch (param[0]) { 279 case LANE_COUNT_ONE: 280 case LANE_COUNT_TWO: 281 case LANE_COUNT_FOUR: 282 break; 283 default: 284 valid_input = false; 285 break; 286 } 287 288 switch (param[1]) { 289 case LINK_RATE_LOW: 290 case LINK_RATE_HIGH: 291 case LINK_RATE_RBR2: 292 case LINK_RATE_HIGH2: 293 case LINK_RATE_HIGH3: 294 #if defined(CONFIG_DRM_AMD_DC_DCN) 295 case LINK_RATE_UHBR10: 296 #endif 297 break; 298 default: 299 valid_input = false; 300 break; 301 } 302 303 if (!valid_input) { 304 kfree(wr_buf); 305 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 306 mutex_lock(&adev->dm.dc_lock); 307 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 308 mutex_unlock(&adev->dm.dc_lock); 309 return size; 310 } 311 312 /* save user force lane_count, link_rate to preferred settings 313 * spread spectrum will not be changed 314 */ 315 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 316 prefer_link_settings.use_link_rate_set = false; 317 prefer_link_settings.lane_count = param[0]; 318 prefer_link_settings.link_rate = param[1]; 319 320 mutex_lock(&adev->dm.dc_lock); 321 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 322 mutex_unlock(&adev->dm.dc_lock); 323 324 kfree(wr_buf); 325 return size; 326 } 327 328 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 329 * post-cursor2 (defined by VESA DP specification) 330 * 331 * valid values 332 * voltage swing: 0,1,2,3 333 * pre-emphasis : 0,1,2,3 334 * post cursor2 : 0,1,2,3 335 * 336 * 337 * how to use this debugfs 338 * 339 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 340 * 341 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 342 * 343 * To figure out which DP-x is the display for DP to be check, 344 * cd DP-x 345 * ls -ll 346 * There should be debugfs file, like link_settings, phy_settings. 347 * cat link_settings 348 * from lane_count, link_rate to figure which DP-x is for display to be worked 349 * on 350 * 351 * To get current DP PHY settings, 352 * cat phy_settings 353 * 354 * To change DP PHY settings, 355 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 356 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 357 * 0, 358 * echo 2 3 0 > phy_settings 359 * 360 * To check if change be applied, get current phy settings by 361 * cat phy_settings 362 * 363 * In case invalid values are set by user, like 364 * echo 1 4 0 > phy_settings 365 * 366 * HW will NOT be programmed by these settings. 367 * cat phy_settings will show the previous valid settings. 368 */ 369 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 370 size_t size, loff_t *pos) 371 { 372 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 373 struct dc_link *link = connector->dc_link; 374 char *rd_buf = NULL; 375 const uint32_t rd_buf_size = 20; 376 uint32_t result = 0; 377 int r; 378 379 if (*pos & 3 || size & 3) 380 return -EINVAL; 381 382 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 383 if (!rd_buf) 384 return -EINVAL; 385 386 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 387 link->cur_lane_setting[0].VOLTAGE_SWING, 388 link->cur_lane_setting[0].PRE_EMPHASIS, 389 link->cur_lane_setting[0].POST_CURSOR2); 390 391 while (size) { 392 if (*pos >= rd_buf_size) 393 break; 394 395 r = put_user((*(rd_buf + result)), buf); 396 if (r) { 397 kfree(rd_buf); 398 return r; /* r = -EFAULT */ 399 } 400 401 buf += 1; 402 size -= 1; 403 *pos += 1; 404 result += 1; 405 } 406 407 kfree(rd_buf); 408 return result; 409 } 410 411 static int dp_lttpr_status_show(struct seq_file *m, void *d) 412 { 413 char *data; 414 struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private; 415 struct dc_link *link = connector->dc_link; 416 uint32_t read_size = 1; 417 uint8_t repeater_count = 0; 418 419 data = kzalloc(read_size, GFP_KERNEL); 420 if (!data) 421 return 0; 422 423 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size); 424 425 switch ((uint8_t)*data) { 426 case 0x80: 427 repeater_count = 1; 428 break; 429 case 0x40: 430 repeater_count = 2; 431 break; 432 case 0x20: 433 repeater_count = 3; 434 break; 435 case 0x10: 436 repeater_count = 4; 437 break; 438 case 0x8: 439 repeater_count = 5; 440 break; 441 case 0x4: 442 repeater_count = 6; 443 break; 444 case 0x2: 445 repeater_count = 7; 446 break; 447 case 0x1: 448 repeater_count = 8; 449 break; 450 case 0x0: 451 repeater_count = 0; 452 break; 453 default: 454 repeater_count = (uint8_t)*data; 455 break; 456 } 457 458 seq_printf(m, "phy repeater count: %d\n", repeater_count); 459 460 dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size); 461 462 if ((uint8_t)*data == 0x55) 463 seq_printf(m, "phy repeater mode: transparent\n"); 464 else if ((uint8_t)*data == 0xAA) 465 seq_printf(m, "phy repeater mode: non-transparent\n"); 466 else if ((uint8_t)*data == 0x00) 467 seq_printf(m, "phy repeater mode: non lttpr\n"); 468 else 469 seq_printf(m, "phy repeater mode: read error\n"); 470 471 kfree(data); 472 return 0; 473 } 474 475 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 476 size_t size, loff_t *pos) 477 { 478 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 479 struct dc_link *link = connector->dc_link; 480 struct dc *dc = (struct dc *)link->dc; 481 char *wr_buf = NULL; 482 uint32_t wr_buf_size = 40; 483 long param[3]; 484 bool use_prefer_link_setting; 485 struct link_training_settings link_lane_settings; 486 int max_param_num = 3; 487 uint8_t param_nums = 0; 488 int r = 0; 489 490 491 if (size == 0) 492 return -EINVAL; 493 494 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 495 if (!wr_buf) 496 return -ENOSPC; 497 498 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 499 (long *)param, buf, 500 max_param_num, 501 ¶m_nums)) { 502 kfree(wr_buf); 503 return -EINVAL; 504 } 505 506 if (param_nums <= 0) { 507 kfree(wr_buf); 508 DRM_DEBUG_DRIVER("user data not be read\n"); 509 return -EINVAL; 510 } 511 512 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 513 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 514 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 515 kfree(wr_buf); 516 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 517 return size; 518 } 519 520 /* get link settings: lane count, link rate */ 521 use_prefer_link_setting = 522 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 523 (link->test_pattern_enabled)); 524 525 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 526 527 if (use_prefer_link_setting) { 528 link_lane_settings.link_settings.lane_count = 529 link->preferred_link_setting.lane_count; 530 link_lane_settings.link_settings.link_rate = 531 link->preferred_link_setting.link_rate; 532 link_lane_settings.link_settings.link_spread = 533 link->preferred_link_setting.link_spread; 534 } else { 535 link_lane_settings.link_settings.lane_count = 536 link->cur_link_settings.lane_count; 537 link_lane_settings.link_settings.link_rate = 538 link->cur_link_settings.link_rate; 539 link_lane_settings.link_settings.link_spread = 540 link->cur_link_settings.link_spread; 541 } 542 543 /* apply phy settings from user */ 544 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 545 link_lane_settings.lane_settings[r].VOLTAGE_SWING = 546 (enum dc_voltage_swing) (param[0]); 547 link_lane_settings.lane_settings[r].PRE_EMPHASIS = 548 (enum dc_pre_emphasis) (param[1]); 549 link_lane_settings.lane_settings[r].POST_CURSOR2 = 550 (enum dc_post_cursor2) (param[2]); 551 } 552 553 /* program ASIC registers and DPCD registers */ 554 dc_link_set_drive_settings(dc, &link_lane_settings, link); 555 556 kfree(wr_buf); 557 return size; 558 } 559 560 /* function description 561 * 562 * set PHY layer or Link layer test pattern 563 * PHY test pattern is used for PHY SI check. 564 * Link layer test will not affect PHY SI. 565 * 566 * Reset Test Pattern: 567 * 0 = DP_TEST_PATTERN_VIDEO_MODE 568 * 569 * PHY test pattern supported: 570 * 1 = DP_TEST_PATTERN_D102 571 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 572 * 3 = DP_TEST_PATTERN_PRBS7 573 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 574 * 5 = DP_TEST_PATTERN_CP2520_1 575 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 576 * 7 = DP_TEST_PATTERN_CP2520_3 577 * 578 * DP PHY Link Training Patterns 579 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 580 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 581 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 582 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 583 * 584 * DP Link Layer Test pattern 585 * c = DP_TEST_PATTERN_COLOR_SQUARES 586 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 587 * e = DP_TEST_PATTERN_VERTICAL_BARS 588 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 589 * 10= DP_TEST_PATTERN_COLOR_RAMP 590 * 591 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 592 * 593 * --- set test pattern 594 * echo <test pattern #> > test_pattern 595 * 596 * If test pattern # is not supported, NO HW programming will be done. 597 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 598 * for the user pattern. input 10 bytes data are separated by space 599 * 600 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 601 * 602 * --- reset test pattern 603 * echo 0 > test_pattern 604 * 605 * --- HPD detection is disabled when set PHY test pattern 606 * 607 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 608 * is disable. User could unplug DP display from DP connected and plug scope to 609 * check test pattern PHY SI. 610 * If there is need unplug scope and plug DP display back, do steps below: 611 * echo 0 > phy_test_pattern 612 * unplug scope 613 * plug DP display. 614 * 615 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 616 * driver could detect "unplug scope" and "plug DP display" 617 */ 618 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 619 size_t size, loff_t *pos) 620 { 621 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 622 struct dc_link *link = connector->dc_link; 623 char *wr_buf = NULL; 624 uint32_t wr_buf_size = 100; 625 long param[11] = {0x0}; 626 int max_param_num = 11; 627 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 628 bool disable_hpd = false; 629 bool valid_test_pattern = false; 630 uint8_t param_nums = 0; 631 /* init with default 80bit custom pattern */ 632 uint8_t custom_pattern[10] = { 633 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 634 0x1f, 0x7c, 0xf0, 0xc1, 0x07 635 }; 636 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 637 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 638 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 639 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 640 struct link_training_settings link_training_settings; 641 int i; 642 643 if (size == 0) 644 return -EINVAL; 645 646 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 647 if (!wr_buf) 648 return -ENOSPC; 649 650 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 651 (long *)param, buf, 652 max_param_num, 653 ¶m_nums)) { 654 kfree(wr_buf); 655 return -EINVAL; 656 } 657 658 if (param_nums <= 0) { 659 kfree(wr_buf); 660 DRM_DEBUG_DRIVER("user data not be read\n"); 661 return -EINVAL; 662 } 663 664 665 test_pattern = param[0]; 666 667 switch (test_pattern) { 668 case DP_TEST_PATTERN_VIDEO_MODE: 669 case DP_TEST_PATTERN_COLOR_SQUARES: 670 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 671 case DP_TEST_PATTERN_VERTICAL_BARS: 672 case DP_TEST_PATTERN_HORIZONTAL_BARS: 673 case DP_TEST_PATTERN_COLOR_RAMP: 674 valid_test_pattern = true; 675 break; 676 677 case DP_TEST_PATTERN_D102: 678 case DP_TEST_PATTERN_SYMBOL_ERROR: 679 case DP_TEST_PATTERN_PRBS7: 680 case DP_TEST_PATTERN_80BIT_CUSTOM: 681 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 682 case DP_TEST_PATTERN_TRAINING_PATTERN4: 683 disable_hpd = true; 684 valid_test_pattern = true; 685 break; 686 687 default: 688 valid_test_pattern = false; 689 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 690 break; 691 } 692 693 if (!valid_test_pattern) { 694 kfree(wr_buf); 695 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 696 return size; 697 } 698 699 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 700 for (i = 0; i < 10; i++) { 701 if ((uint8_t) param[i + 1] != 0x0) 702 break; 703 } 704 705 if (i < 10) { 706 /* not use default value */ 707 for (i = 0; i < 10; i++) 708 custom_pattern[i] = (uint8_t) param[i + 1]; 709 } 710 } 711 712 /* Usage: set DP physical test pattern using debugfs with normal DP 713 * panel. Then plug out DP panel and connect a scope to measure 714 * For normal video mode and test pattern generated from CRCT, 715 * they are visibile to user. So do not disable HPD. 716 * Video Mode is also set to clear the test pattern, so enable HPD 717 * because it might have been disabled after a test pattern was set. 718 * AUX depends on HPD * sequence dependent, do not move! 719 */ 720 if (!disable_hpd) 721 dc_link_enable_hpd(link); 722 723 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 724 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 725 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 726 727 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 728 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 729 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 730 731 link_training_settings.link_settings = cur_link_settings; 732 733 734 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 735 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 736 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 737 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 738 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 739 link_training_settings.link_settings = prefer_link_settings; 740 } 741 742 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 743 link_training_settings.lane_settings[i] = link->cur_lane_setting[i]; 744 745 dc_link_set_test_pattern( 746 link, 747 test_pattern, 748 DP_TEST_PATTERN_COLOR_SPACE_RGB, 749 &link_training_settings, 750 custom_pattern, 751 10); 752 753 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 754 * Then plug out DP panel and connect a scope to measure DP PHY signal. 755 * Need disable interrupt to avoid SW driver disable DP output. This is 756 * done after the test pattern is set. 757 */ 758 if (valid_test_pattern && disable_hpd) 759 dc_link_disable_hpd(link); 760 761 kfree(wr_buf); 762 763 return size; 764 } 765 766 /* 767 * Returns the DMCUB tracebuffer contents. 768 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 769 */ 770 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 771 { 772 struct amdgpu_device *adev = m->private; 773 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 774 struct dmub_debugfs_trace_entry *entries; 775 uint8_t *tbuf_base; 776 uint32_t tbuf_size, max_entries, num_entries, i; 777 778 if (!fb_info) 779 return 0; 780 781 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 782 if (!tbuf_base) 783 return 0; 784 785 tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size; 786 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 787 sizeof(struct dmub_debugfs_trace_entry); 788 789 num_entries = 790 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 791 792 num_entries = min(num_entries, max_entries); 793 794 entries = (struct dmub_debugfs_trace_entry 795 *)(tbuf_base + 796 sizeof(struct dmub_debugfs_trace_header)); 797 798 for (i = 0; i < num_entries; ++i) { 799 struct dmub_debugfs_trace_entry *entry = &entries[i]; 800 801 seq_printf(m, 802 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 803 entry->trace_code, entry->tick_count, entry->param0, 804 entry->param1); 805 } 806 807 return 0; 808 } 809 810 /* 811 * Returns the DMCUB firmware state contents. 812 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 813 */ 814 static int dmub_fw_state_show(struct seq_file *m, void *data) 815 { 816 struct amdgpu_device *adev = m->private; 817 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 818 uint8_t *state_base; 819 uint32_t state_size; 820 821 if (!fb_info) 822 return 0; 823 824 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 825 if (!state_base) 826 return 0; 827 828 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 829 830 return seq_write(m, state_base, state_size); 831 } 832 833 /* psr_capability_show() - show eDP panel PSR capability 834 * 835 * The read function: sink_psr_capability_show 836 * Shows if sink has PSR capability or not. 837 * If yes - the PSR version is appended 838 * 839 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 840 * 841 * Expected output: 842 * "Sink support: no\n" - if panel doesn't support PSR 843 * "Sink support: yes [0x01]\n" - if panel supports PSR1 844 * "Driver support: no\n" - if driver doesn't support PSR 845 * "Driver support: yes [0x01]\n" - if driver supports PSR1 846 */ 847 static int psr_capability_show(struct seq_file *m, void *data) 848 { 849 struct drm_connector *connector = m->private; 850 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 851 struct dc_link *link = aconnector->dc_link; 852 853 if (!link) 854 return -ENODEV; 855 856 if (link->type == dc_connection_none) 857 return -ENODEV; 858 859 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 860 return -ENODEV; 861 862 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 863 if (link->dpcd_caps.psr_info.psr_version) 864 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 865 seq_puts(m, "\n"); 866 867 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 868 if (link->psr_settings.psr_version) 869 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 870 seq_puts(m, "\n"); 871 872 return 0; 873 } 874 875 /* 876 * Returns the current and maximum output bpc for the connector. 877 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc 878 */ 879 static int output_bpc_show(struct seq_file *m, void *data) 880 { 881 struct drm_connector *connector = m->private; 882 struct drm_device *dev = connector->dev; 883 struct drm_crtc *crtc = NULL; 884 struct dm_crtc_state *dm_crtc_state = NULL; 885 int res = -ENODEV; 886 unsigned int bpc; 887 888 mutex_lock(&dev->mode_config.mutex); 889 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 890 891 if (connector->state == NULL) 892 goto unlock; 893 894 crtc = connector->state->crtc; 895 if (crtc == NULL) 896 goto unlock; 897 898 drm_modeset_lock(&crtc->mutex, NULL); 899 if (crtc->state == NULL) 900 goto unlock; 901 902 dm_crtc_state = to_dm_crtc_state(crtc->state); 903 if (dm_crtc_state->stream == NULL) 904 goto unlock; 905 906 switch (dm_crtc_state->stream->timing.display_color_depth) { 907 case COLOR_DEPTH_666: 908 bpc = 6; 909 break; 910 case COLOR_DEPTH_888: 911 bpc = 8; 912 break; 913 case COLOR_DEPTH_101010: 914 bpc = 10; 915 break; 916 case COLOR_DEPTH_121212: 917 bpc = 12; 918 break; 919 case COLOR_DEPTH_161616: 920 bpc = 16; 921 break; 922 default: 923 goto unlock; 924 } 925 926 seq_printf(m, "Current: %u\n", bpc); 927 seq_printf(m, "Maximum: %u\n", connector->display_info.bpc); 928 res = 0; 929 930 unlock: 931 if (crtc) 932 drm_modeset_unlock(&crtc->mutex); 933 934 drm_modeset_unlock(&dev->mode_config.connection_mutex); 935 mutex_unlock(&dev->mode_config.mutex); 936 937 return res; 938 } 939 940 /* 941 * Example usage: 942 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 943 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 944 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 945 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 946 */ 947 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 948 size_t size, loff_t *pos) 949 { 950 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 951 char *wr_buf = NULL; 952 uint32_t wr_buf_size = 42; 953 int max_param_num = 1; 954 long param; 955 uint8_t param_nums = 0; 956 957 if (size == 0) 958 return -EINVAL; 959 960 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 961 962 if (!wr_buf) { 963 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 964 return -ENOSPC; 965 } 966 967 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 968 ¶m, buf, 969 max_param_num, 970 ¶m_nums)) { 971 kfree(wr_buf); 972 return -EINVAL; 973 } 974 975 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 976 977 kfree(wr_buf); 978 return 0; 979 } 980 981 #ifdef CONFIG_DRM_AMD_DC_HDCP 982 /* 983 * Returns the HDCP capability of the Display (1.4 for now). 984 * 985 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 986 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 987 * 988 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 989 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 990 */ 991 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 992 { 993 struct drm_connector *connector = m->private; 994 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 995 bool hdcp_cap, hdcp2_cap; 996 997 if (connector->status != connector_status_connected) 998 return -ENODEV; 999 1000 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1001 1002 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1003 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1004 1005 1006 if (hdcp_cap) 1007 seq_printf(m, "%s ", "HDCP1.4"); 1008 if (hdcp2_cap) 1009 seq_printf(m, "%s ", "HDCP2.2"); 1010 1011 if (!hdcp_cap && !hdcp2_cap) 1012 seq_printf(m, "%s ", "None"); 1013 1014 seq_puts(m, "\n"); 1015 1016 return 0; 1017 } 1018 #endif 1019 1020 /* 1021 * Returns whether the connected display is internal and not hotpluggable. 1022 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1023 */ 1024 static int internal_display_show(struct seq_file *m, void *data) 1025 { 1026 struct drm_connector *connector = m->private; 1027 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1028 struct dc_link *link = aconnector->dc_link; 1029 1030 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1031 1032 return 0; 1033 } 1034 1035 /* function description 1036 * 1037 * generic SDP message access for testing 1038 * 1039 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1040 * 1041 * SDP header 1042 * Hb0 : Secondary-Data Packet ID 1043 * Hb1 : Secondary-Data Packet type 1044 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1045 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1046 * 1047 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1048 */ 1049 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1050 size_t size, loff_t *pos) 1051 { 1052 int r; 1053 uint8_t data[36]; 1054 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1055 struct dm_crtc_state *acrtc_state; 1056 uint32_t write_size = 36; 1057 1058 if (connector->base.status != connector_status_connected) 1059 return -ENODEV; 1060 1061 if (size == 0) 1062 return 0; 1063 1064 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1065 1066 r = copy_from_user(data, buf, write_size); 1067 1068 write_size -= r; 1069 1070 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1071 1072 return write_size; 1073 } 1074 1075 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf, 1076 size_t size, loff_t *pos) 1077 { 1078 int r; 1079 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1080 1081 if (size < sizeof(connector->debugfs_dpcd_address)) 1082 return -EINVAL; 1083 1084 r = copy_from_user(&connector->debugfs_dpcd_address, 1085 buf, sizeof(connector->debugfs_dpcd_address)); 1086 1087 return size - r; 1088 } 1089 1090 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf, 1091 size_t size, loff_t *pos) 1092 { 1093 int r; 1094 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1095 1096 if (size < sizeof(connector->debugfs_dpcd_size)) 1097 return -EINVAL; 1098 1099 r = copy_from_user(&connector->debugfs_dpcd_size, 1100 buf, sizeof(connector->debugfs_dpcd_size)); 1101 1102 if (connector->debugfs_dpcd_size > 256) 1103 connector->debugfs_dpcd_size = 0; 1104 1105 return size - r; 1106 } 1107 1108 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf, 1109 size_t size, loff_t *pos) 1110 { 1111 int r; 1112 char *data; 1113 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1114 struct dc_link *link = connector->dc_link; 1115 uint32_t write_size = connector->debugfs_dpcd_size; 1116 1117 if (!write_size || size < write_size) 1118 return -EINVAL; 1119 1120 data = kzalloc(write_size, GFP_KERNEL); 1121 if (!data) 1122 return 0; 1123 1124 r = copy_from_user(data, buf, write_size); 1125 1126 dm_helpers_dp_write_dpcd(link->ctx, link, 1127 connector->debugfs_dpcd_address, data, write_size - r); 1128 kfree(data); 1129 return write_size - r; 1130 } 1131 1132 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, 1133 size_t size, loff_t *pos) 1134 { 1135 int r; 1136 char *data; 1137 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1138 struct dc_link *link = connector->dc_link; 1139 uint32_t read_size = connector->debugfs_dpcd_size; 1140 1141 if (!read_size || size < read_size) 1142 return 0; 1143 1144 data = kzalloc(read_size, GFP_KERNEL); 1145 if (!data) 1146 return 0; 1147 1148 dm_helpers_dp_read_dpcd(link->ctx, link, 1149 connector->debugfs_dpcd_address, data, read_size); 1150 1151 r = copy_to_user(buf, data, read_size); 1152 1153 kfree(data); 1154 return read_size - r; 1155 } 1156 1157 /* function: Read link's DSC & FEC capabilities 1158 * 1159 * 1160 * Access it with the following command (you need to specify 1161 * connector like DP-1): 1162 * 1163 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1164 * 1165 */ 1166 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1167 { 1168 struct drm_connector *connector = m->private; 1169 struct drm_modeset_acquire_ctx ctx; 1170 struct drm_device *dev = connector->dev; 1171 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1172 int ret = 0; 1173 bool try_again = false; 1174 bool is_fec_supported = false; 1175 bool is_dsc_supported = false; 1176 struct dpcd_caps dpcd_caps; 1177 1178 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1179 do { 1180 try_again = false; 1181 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1182 if (ret) { 1183 if (ret == -EDEADLK) { 1184 ret = drm_modeset_backoff(&ctx); 1185 if (!ret) { 1186 try_again = true; 1187 continue; 1188 } 1189 } 1190 break; 1191 } 1192 if (connector->status != connector_status_connected) { 1193 ret = -ENODEV; 1194 break; 1195 } 1196 dpcd_caps = aconnector->dc_link->dpcd_caps; 1197 if (aconnector->port) { 1198 /* aconnector sets dsc_aux during get_modes call 1199 * if MST connector has it means it can either 1200 * enable DSC on the sink device or on MST branch 1201 * its connected to. 1202 */ 1203 if (aconnector->dsc_aux) { 1204 is_fec_supported = true; 1205 is_dsc_supported = true; 1206 } 1207 } else { 1208 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1209 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1210 } 1211 } while (try_again); 1212 1213 drm_modeset_drop_locks(&ctx); 1214 drm_modeset_acquire_fini(&ctx); 1215 1216 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1217 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1218 1219 return ret; 1220 } 1221 1222 /* function: Trigger virtual HPD redetection on connector 1223 * 1224 * This function will perform link rediscovery, link disable 1225 * and enable, and dm connector state update. 1226 * 1227 * Retrigger HPD on an existing connector by echoing 1 into 1228 * its respectful "trigger_hotplug" debugfs entry: 1229 * 1230 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1231 * 1232 * This function can perform HPD unplug: 1233 * 1234 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1235 * 1236 */ 1237 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1238 size_t size, loff_t *pos) 1239 { 1240 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1241 struct drm_connector *connector = &aconnector->base; 1242 struct dc_link *link = NULL; 1243 struct drm_device *dev = connector->dev; 1244 enum dc_connection_type new_connection_type = dc_connection_none; 1245 char *wr_buf = NULL; 1246 uint32_t wr_buf_size = 42; 1247 int max_param_num = 1; 1248 long param[1] = {0}; 1249 uint8_t param_nums = 0; 1250 1251 if (!aconnector || !aconnector->dc_link) 1252 return -EINVAL; 1253 1254 if (size == 0) 1255 return -EINVAL; 1256 1257 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1258 1259 if (!wr_buf) { 1260 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1261 return -ENOSPC; 1262 } 1263 1264 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1265 (long *)param, buf, 1266 max_param_num, 1267 ¶m_nums)) { 1268 kfree(wr_buf); 1269 return -EINVAL; 1270 } 1271 1272 if (param_nums <= 0) { 1273 DRM_DEBUG_DRIVER("user data not be read\n"); 1274 kfree(wr_buf); 1275 return -EINVAL; 1276 } 1277 1278 if (param[0] == 1) { 1279 mutex_lock(&aconnector->hpd_lock); 1280 1281 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) && 1282 new_connection_type != dc_connection_none) 1283 goto unlock; 1284 1285 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) 1286 goto unlock; 1287 1288 amdgpu_dm_update_connector_after_detect(aconnector); 1289 1290 drm_modeset_lock_all(dev); 1291 dm_restore_drm_connector_state(dev, connector); 1292 drm_modeset_unlock_all(dev); 1293 1294 drm_kms_helper_connector_hotplug_event(connector); 1295 } else if (param[0] == 0) { 1296 if (!aconnector->dc_link) 1297 goto unlock; 1298 1299 link = aconnector->dc_link; 1300 1301 if (link->local_sink) { 1302 dc_sink_release(link->local_sink); 1303 link->local_sink = NULL; 1304 } 1305 1306 link->dpcd_sink_count = 0; 1307 link->type = dc_connection_none; 1308 link->dongle_max_pix_clk = 0; 1309 1310 amdgpu_dm_update_connector_after_detect(aconnector); 1311 1312 drm_modeset_lock_all(dev); 1313 dm_restore_drm_connector_state(dev, connector); 1314 drm_modeset_unlock_all(dev); 1315 1316 drm_kms_helper_connector_hotplug_event(connector); 1317 } 1318 1319 unlock: 1320 mutex_unlock(&aconnector->hpd_lock); 1321 1322 kfree(wr_buf); 1323 return size; 1324 } 1325 1326 /* function: read DSC status on the connector 1327 * 1328 * The read function: dp_dsc_clock_en_read 1329 * returns current status of DSC clock on the connector. 1330 * The return is a boolean flag: 1 or 0. 1331 * 1332 * Access it with the following command (you need to specify 1333 * connector like DP-1): 1334 * 1335 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1336 * 1337 * Expected output: 1338 * 1 - means that DSC is currently enabled 1339 * 0 - means that DSC is disabled 1340 */ 1341 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1342 size_t size, loff_t *pos) 1343 { 1344 char *rd_buf = NULL; 1345 char *rd_buf_ptr = NULL; 1346 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1347 struct display_stream_compressor *dsc; 1348 struct dcn_dsc_state dsc_state = {0}; 1349 const uint32_t rd_buf_size = 10; 1350 struct pipe_ctx *pipe_ctx; 1351 ssize_t result = 0; 1352 int i, r, str_len = 30; 1353 1354 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1355 1356 if (!rd_buf) 1357 return -ENOMEM; 1358 1359 rd_buf_ptr = rd_buf; 1360 1361 for (i = 0; i < MAX_PIPES; i++) { 1362 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1363 if (pipe_ctx && pipe_ctx->stream && 1364 pipe_ctx->stream->link == aconnector->dc_link) 1365 break; 1366 } 1367 1368 if (!pipe_ctx) { 1369 kfree(rd_buf); 1370 return -ENXIO; 1371 } 1372 1373 dsc = pipe_ctx->stream_res.dsc; 1374 if (dsc) 1375 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1376 1377 snprintf(rd_buf_ptr, str_len, 1378 "%d\n", 1379 dsc_state.dsc_clock_en); 1380 rd_buf_ptr += str_len; 1381 1382 while (size) { 1383 if (*pos >= rd_buf_size) 1384 break; 1385 1386 r = put_user(*(rd_buf + result), buf); 1387 if (r) { 1388 kfree(rd_buf); 1389 return r; /* r = -EFAULT */ 1390 } 1391 1392 buf += 1; 1393 size -= 1; 1394 *pos += 1; 1395 result += 1; 1396 } 1397 1398 kfree(rd_buf); 1399 return result; 1400 } 1401 1402 /* function: write force DSC on the connector 1403 * 1404 * The write function: dp_dsc_clock_en_write 1405 * enables to force DSC on the connector. 1406 * User can write to either force enable or force disable DSC 1407 * on the next modeset or set it to driver default 1408 * 1409 * Accepted inputs: 1410 * 0 - default DSC enablement policy 1411 * 1 - force enable DSC on the connector 1412 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1413 * 1414 * Writing DSC settings is done with the following command: 1415 * - To force enable DSC (you need to specify 1416 * connector like DP-1): 1417 * 1418 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1419 * 1420 * - To return to default state set the flag to zero and 1421 * let driver deal with DSC automatically 1422 * (you need to specify connector like DP-1): 1423 * 1424 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1425 * 1426 */ 1427 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1428 size_t size, loff_t *pos) 1429 { 1430 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1431 struct drm_connector *connector = &aconnector->base; 1432 struct drm_device *dev = connector->dev; 1433 struct drm_crtc *crtc = NULL; 1434 struct dm_crtc_state *dm_crtc_state = NULL; 1435 struct pipe_ctx *pipe_ctx; 1436 int i; 1437 char *wr_buf = NULL; 1438 uint32_t wr_buf_size = 42; 1439 int max_param_num = 1; 1440 long param[1] = {0}; 1441 uint8_t param_nums = 0; 1442 1443 if (size == 0) 1444 return -EINVAL; 1445 1446 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1447 1448 if (!wr_buf) { 1449 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1450 return -ENOSPC; 1451 } 1452 1453 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1454 (long *)param, buf, 1455 max_param_num, 1456 ¶m_nums)) { 1457 kfree(wr_buf); 1458 return -EINVAL; 1459 } 1460 1461 if (param_nums <= 0) { 1462 DRM_DEBUG_DRIVER("user data not be read\n"); 1463 kfree(wr_buf); 1464 return -EINVAL; 1465 } 1466 1467 for (i = 0; i < MAX_PIPES; i++) { 1468 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1469 if (pipe_ctx && pipe_ctx->stream && 1470 pipe_ctx->stream->link == aconnector->dc_link) 1471 break; 1472 } 1473 1474 if (!pipe_ctx || !pipe_ctx->stream) 1475 goto done; 1476 1477 // Get CRTC state 1478 mutex_lock(&dev->mode_config.mutex); 1479 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1480 1481 if (connector->state == NULL) 1482 goto unlock; 1483 1484 crtc = connector->state->crtc; 1485 if (crtc == NULL) 1486 goto unlock; 1487 1488 drm_modeset_lock(&crtc->mutex, NULL); 1489 if (crtc->state == NULL) 1490 goto unlock; 1491 1492 dm_crtc_state = to_dm_crtc_state(crtc->state); 1493 if (dm_crtc_state->stream == NULL) 1494 goto unlock; 1495 1496 if (param[0] == 1) 1497 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1498 else if (param[0] == 2) 1499 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1500 else 1501 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1502 1503 dm_crtc_state->dsc_force_changed = true; 1504 1505 unlock: 1506 if (crtc) 1507 drm_modeset_unlock(&crtc->mutex); 1508 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1509 mutex_unlock(&dev->mode_config.mutex); 1510 1511 done: 1512 kfree(wr_buf); 1513 return size; 1514 } 1515 1516 /* function: read DSC slice width parameter on the connector 1517 * 1518 * The read function: dp_dsc_slice_width_read 1519 * returns dsc slice width used in the current configuration 1520 * The return is an integer: 0 or other positive number 1521 * 1522 * Access the status with the following command: 1523 * 1524 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1525 * 1526 * 0 - means that DSC is disabled 1527 * 1528 * Any other number more than zero represents the 1529 * slice width currently used by DSC in pixels 1530 * 1531 */ 1532 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1533 size_t size, loff_t *pos) 1534 { 1535 char *rd_buf = NULL; 1536 char *rd_buf_ptr = NULL; 1537 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1538 struct display_stream_compressor *dsc; 1539 struct dcn_dsc_state dsc_state = {0}; 1540 const uint32_t rd_buf_size = 100; 1541 struct pipe_ctx *pipe_ctx; 1542 ssize_t result = 0; 1543 int i, r, str_len = 30; 1544 1545 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1546 1547 if (!rd_buf) 1548 return -ENOMEM; 1549 1550 rd_buf_ptr = rd_buf; 1551 1552 for (i = 0; i < MAX_PIPES; i++) { 1553 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1554 if (pipe_ctx && pipe_ctx->stream && 1555 pipe_ctx->stream->link == aconnector->dc_link) 1556 break; 1557 } 1558 1559 if (!pipe_ctx) { 1560 kfree(rd_buf); 1561 return -ENXIO; 1562 } 1563 1564 dsc = pipe_ctx->stream_res.dsc; 1565 if (dsc) 1566 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1567 1568 snprintf(rd_buf_ptr, str_len, 1569 "%d\n", 1570 dsc_state.dsc_slice_width); 1571 rd_buf_ptr += str_len; 1572 1573 while (size) { 1574 if (*pos >= rd_buf_size) 1575 break; 1576 1577 r = put_user(*(rd_buf + result), buf); 1578 if (r) { 1579 kfree(rd_buf); 1580 return r; /* r = -EFAULT */ 1581 } 1582 1583 buf += 1; 1584 size -= 1; 1585 *pos += 1; 1586 result += 1; 1587 } 1588 1589 kfree(rd_buf); 1590 return result; 1591 } 1592 1593 /* function: write DSC slice width parameter 1594 * 1595 * The write function: dp_dsc_slice_width_write 1596 * overwrites automatically generated DSC configuration 1597 * of slice width. 1598 * 1599 * The user has to write the slice width divisible by the 1600 * picture width. 1601 * 1602 * Also the user has to write width in hexidecimal 1603 * rather than in decimal. 1604 * 1605 * Writing DSC settings is done with the following command: 1606 * - To force overwrite slice width: (example sets to 1920 pixels) 1607 * 1608 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1609 * 1610 * - To stop overwriting and let driver find the optimal size, 1611 * set the width to zero: 1612 * 1613 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1614 * 1615 */ 1616 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1617 size_t size, loff_t *pos) 1618 { 1619 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1620 struct pipe_ctx *pipe_ctx; 1621 struct drm_connector *connector = &aconnector->base; 1622 struct drm_device *dev = connector->dev; 1623 struct drm_crtc *crtc = NULL; 1624 struct dm_crtc_state *dm_crtc_state = NULL; 1625 int i; 1626 char *wr_buf = NULL; 1627 uint32_t wr_buf_size = 42; 1628 int max_param_num = 1; 1629 long param[1] = {0}; 1630 uint8_t param_nums = 0; 1631 1632 if (size == 0) 1633 return -EINVAL; 1634 1635 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1636 1637 if (!wr_buf) { 1638 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1639 return -ENOSPC; 1640 } 1641 1642 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1643 (long *)param, buf, 1644 max_param_num, 1645 ¶m_nums)) { 1646 kfree(wr_buf); 1647 return -EINVAL; 1648 } 1649 1650 if (param_nums <= 0) { 1651 DRM_DEBUG_DRIVER("user data not be read\n"); 1652 kfree(wr_buf); 1653 return -EINVAL; 1654 } 1655 1656 for (i = 0; i < MAX_PIPES; i++) { 1657 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1658 if (pipe_ctx && pipe_ctx->stream && 1659 pipe_ctx->stream->link == aconnector->dc_link) 1660 break; 1661 } 1662 1663 if (!pipe_ctx || !pipe_ctx->stream) 1664 goto done; 1665 1666 // Safely get CRTC state 1667 mutex_lock(&dev->mode_config.mutex); 1668 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1669 1670 if (connector->state == NULL) 1671 goto unlock; 1672 1673 crtc = connector->state->crtc; 1674 if (crtc == NULL) 1675 goto unlock; 1676 1677 drm_modeset_lock(&crtc->mutex, NULL); 1678 if (crtc->state == NULL) 1679 goto unlock; 1680 1681 dm_crtc_state = to_dm_crtc_state(crtc->state); 1682 if (dm_crtc_state->stream == NULL) 1683 goto unlock; 1684 1685 if (param[0] > 0) 1686 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1687 pipe_ctx->stream->timing.h_addressable, 1688 param[0]); 1689 else 1690 aconnector->dsc_settings.dsc_num_slices_h = 0; 1691 1692 dm_crtc_state->dsc_force_changed = true; 1693 1694 unlock: 1695 if (crtc) 1696 drm_modeset_unlock(&crtc->mutex); 1697 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1698 mutex_unlock(&dev->mode_config.mutex); 1699 1700 done: 1701 kfree(wr_buf); 1702 return size; 1703 } 1704 1705 /* function: read DSC slice height parameter on the connector 1706 * 1707 * The read function: dp_dsc_slice_height_read 1708 * returns dsc slice height used in the current configuration 1709 * The return is an integer: 0 or other positive number 1710 * 1711 * Access the status with the following command: 1712 * 1713 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1714 * 1715 * 0 - means that DSC is disabled 1716 * 1717 * Any other number more than zero represents the 1718 * slice height currently used by DSC in pixels 1719 * 1720 */ 1721 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1722 size_t size, loff_t *pos) 1723 { 1724 char *rd_buf = NULL; 1725 char *rd_buf_ptr = NULL; 1726 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1727 struct display_stream_compressor *dsc; 1728 struct dcn_dsc_state dsc_state = {0}; 1729 const uint32_t rd_buf_size = 100; 1730 struct pipe_ctx *pipe_ctx; 1731 ssize_t result = 0; 1732 int i, r, str_len = 30; 1733 1734 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1735 1736 if (!rd_buf) 1737 return -ENOMEM; 1738 1739 rd_buf_ptr = rd_buf; 1740 1741 for (i = 0; i < MAX_PIPES; i++) { 1742 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1743 if (pipe_ctx && pipe_ctx->stream && 1744 pipe_ctx->stream->link == aconnector->dc_link) 1745 break; 1746 } 1747 1748 if (!pipe_ctx) { 1749 kfree(rd_buf); 1750 return -ENXIO; 1751 } 1752 1753 dsc = pipe_ctx->stream_res.dsc; 1754 if (dsc) 1755 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1756 1757 snprintf(rd_buf_ptr, str_len, 1758 "%d\n", 1759 dsc_state.dsc_slice_height); 1760 rd_buf_ptr += str_len; 1761 1762 while (size) { 1763 if (*pos >= rd_buf_size) 1764 break; 1765 1766 r = put_user(*(rd_buf + result), buf); 1767 if (r) { 1768 kfree(rd_buf); 1769 return r; /* r = -EFAULT */ 1770 } 1771 1772 buf += 1; 1773 size -= 1; 1774 *pos += 1; 1775 result += 1; 1776 } 1777 1778 kfree(rd_buf); 1779 return result; 1780 } 1781 1782 /* function: write DSC slice height parameter 1783 * 1784 * The write function: dp_dsc_slice_height_write 1785 * overwrites automatically generated DSC configuration 1786 * of slice height. 1787 * 1788 * The user has to write the slice height divisible by the 1789 * picture height. 1790 * 1791 * Also the user has to write height in hexidecimal 1792 * rather than in decimal. 1793 * 1794 * Writing DSC settings is done with the following command: 1795 * - To force overwrite slice height (example sets to 128 pixels): 1796 * 1797 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1798 * 1799 * - To stop overwriting and let driver find the optimal size, 1800 * set the height to zero: 1801 * 1802 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1803 * 1804 */ 1805 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 1806 size_t size, loff_t *pos) 1807 { 1808 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1809 struct drm_connector *connector = &aconnector->base; 1810 struct drm_device *dev = connector->dev; 1811 struct drm_crtc *crtc = NULL; 1812 struct dm_crtc_state *dm_crtc_state = NULL; 1813 struct pipe_ctx *pipe_ctx; 1814 int i; 1815 char *wr_buf = NULL; 1816 uint32_t wr_buf_size = 42; 1817 int max_param_num = 1; 1818 uint8_t param_nums = 0; 1819 long param[1] = {0}; 1820 1821 if (size == 0) 1822 return -EINVAL; 1823 1824 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1825 1826 if (!wr_buf) { 1827 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1828 return -ENOSPC; 1829 } 1830 1831 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1832 (long *)param, buf, 1833 max_param_num, 1834 ¶m_nums)) { 1835 kfree(wr_buf); 1836 return -EINVAL; 1837 } 1838 1839 if (param_nums <= 0) { 1840 DRM_DEBUG_DRIVER("user data not be read\n"); 1841 kfree(wr_buf); 1842 return -EINVAL; 1843 } 1844 1845 for (i = 0; i < MAX_PIPES; i++) { 1846 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1847 if (pipe_ctx && pipe_ctx->stream && 1848 pipe_ctx->stream->link == aconnector->dc_link) 1849 break; 1850 } 1851 1852 if (!pipe_ctx || !pipe_ctx->stream) 1853 goto done; 1854 1855 // Get CRTC state 1856 mutex_lock(&dev->mode_config.mutex); 1857 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1858 1859 if (connector->state == NULL) 1860 goto unlock; 1861 1862 crtc = connector->state->crtc; 1863 if (crtc == NULL) 1864 goto unlock; 1865 1866 drm_modeset_lock(&crtc->mutex, NULL); 1867 if (crtc->state == NULL) 1868 goto unlock; 1869 1870 dm_crtc_state = to_dm_crtc_state(crtc->state); 1871 if (dm_crtc_state->stream == NULL) 1872 goto unlock; 1873 1874 if (param[0] > 0) 1875 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 1876 pipe_ctx->stream->timing.v_addressable, 1877 param[0]); 1878 else 1879 aconnector->dsc_settings.dsc_num_slices_v = 0; 1880 1881 dm_crtc_state->dsc_force_changed = true; 1882 1883 unlock: 1884 if (crtc) 1885 drm_modeset_unlock(&crtc->mutex); 1886 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1887 mutex_unlock(&dev->mode_config.mutex); 1888 1889 done: 1890 kfree(wr_buf); 1891 return size; 1892 } 1893 1894 /* function: read DSC target rate on the connector in bits per pixel 1895 * 1896 * The read function: dp_dsc_bits_per_pixel_read 1897 * returns target rate of compression in bits per pixel 1898 * The return is an integer: 0 or other positive integer 1899 * 1900 * Access it with the following command: 1901 * 1902 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1903 * 1904 * 0 - means that DSC is disabled 1905 */ 1906 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 1907 size_t size, loff_t *pos) 1908 { 1909 char *rd_buf = NULL; 1910 char *rd_buf_ptr = NULL; 1911 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1912 struct display_stream_compressor *dsc; 1913 struct dcn_dsc_state dsc_state = {0}; 1914 const uint32_t rd_buf_size = 100; 1915 struct pipe_ctx *pipe_ctx; 1916 ssize_t result = 0; 1917 int i, r, str_len = 30; 1918 1919 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1920 1921 if (!rd_buf) 1922 return -ENOMEM; 1923 1924 rd_buf_ptr = rd_buf; 1925 1926 for (i = 0; i < MAX_PIPES; i++) { 1927 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1928 if (pipe_ctx && pipe_ctx->stream && 1929 pipe_ctx->stream->link == aconnector->dc_link) 1930 break; 1931 } 1932 1933 if (!pipe_ctx) { 1934 kfree(rd_buf); 1935 return -ENXIO; 1936 } 1937 1938 dsc = pipe_ctx->stream_res.dsc; 1939 if (dsc) 1940 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1941 1942 snprintf(rd_buf_ptr, str_len, 1943 "%d\n", 1944 dsc_state.dsc_bits_per_pixel); 1945 rd_buf_ptr += str_len; 1946 1947 while (size) { 1948 if (*pos >= rd_buf_size) 1949 break; 1950 1951 r = put_user(*(rd_buf + result), buf); 1952 if (r) { 1953 kfree(rd_buf); 1954 return r; /* r = -EFAULT */ 1955 } 1956 1957 buf += 1; 1958 size -= 1; 1959 *pos += 1; 1960 result += 1; 1961 } 1962 1963 kfree(rd_buf); 1964 return result; 1965 } 1966 1967 /* function: write DSC target rate in bits per pixel 1968 * 1969 * The write function: dp_dsc_bits_per_pixel_write 1970 * overwrites automatically generated DSC configuration 1971 * of DSC target bit rate. 1972 * 1973 * Also the user has to write bpp in hexidecimal 1974 * rather than in decimal. 1975 * 1976 * Writing DSC settings is done with the following command: 1977 * - To force overwrite rate (example sets to 256 bpp x 1/16): 1978 * 1979 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1980 * 1981 * - To stop overwriting and let driver find the optimal rate, 1982 * set the rate to zero: 1983 * 1984 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 1985 * 1986 */ 1987 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 1988 size_t size, loff_t *pos) 1989 { 1990 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1991 struct drm_connector *connector = &aconnector->base; 1992 struct drm_device *dev = connector->dev; 1993 struct drm_crtc *crtc = NULL; 1994 struct dm_crtc_state *dm_crtc_state = NULL; 1995 struct pipe_ctx *pipe_ctx; 1996 int i; 1997 char *wr_buf = NULL; 1998 uint32_t wr_buf_size = 42; 1999 int max_param_num = 1; 2000 uint8_t param_nums = 0; 2001 long param[1] = {0}; 2002 2003 if (size == 0) 2004 return -EINVAL; 2005 2006 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2007 2008 if (!wr_buf) { 2009 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2010 return -ENOSPC; 2011 } 2012 2013 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2014 (long *)param, buf, 2015 max_param_num, 2016 ¶m_nums)) { 2017 kfree(wr_buf); 2018 return -EINVAL; 2019 } 2020 2021 if (param_nums <= 0) { 2022 DRM_DEBUG_DRIVER("user data not be read\n"); 2023 kfree(wr_buf); 2024 return -EINVAL; 2025 } 2026 2027 for (i = 0; i < MAX_PIPES; i++) { 2028 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2029 if (pipe_ctx && pipe_ctx->stream && 2030 pipe_ctx->stream->link == aconnector->dc_link) 2031 break; 2032 } 2033 2034 if (!pipe_ctx || !pipe_ctx->stream) 2035 goto done; 2036 2037 // Get CRTC state 2038 mutex_lock(&dev->mode_config.mutex); 2039 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2040 2041 if (connector->state == NULL) 2042 goto unlock; 2043 2044 crtc = connector->state->crtc; 2045 if (crtc == NULL) 2046 goto unlock; 2047 2048 drm_modeset_lock(&crtc->mutex, NULL); 2049 if (crtc->state == NULL) 2050 goto unlock; 2051 2052 dm_crtc_state = to_dm_crtc_state(crtc->state); 2053 if (dm_crtc_state->stream == NULL) 2054 goto unlock; 2055 2056 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2057 2058 dm_crtc_state->dsc_force_changed = true; 2059 2060 unlock: 2061 if (crtc) 2062 drm_modeset_unlock(&crtc->mutex); 2063 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2064 mutex_unlock(&dev->mode_config.mutex); 2065 2066 done: 2067 kfree(wr_buf); 2068 return size; 2069 } 2070 2071 /* function: read DSC picture width parameter on the connector 2072 * 2073 * The read function: dp_dsc_pic_width_read 2074 * returns dsc picture width used in the current configuration 2075 * It is the same as h_addressable of the current 2076 * display's timing 2077 * The return is an integer: 0 or other positive integer 2078 * If 0 then DSC is disabled. 2079 * 2080 * Access it with the following command: 2081 * 2082 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2083 * 2084 * 0 - means that DSC is disabled 2085 */ 2086 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2087 size_t size, loff_t *pos) 2088 { 2089 char *rd_buf = NULL; 2090 char *rd_buf_ptr = NULL; 2091 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2092 struct display_stream_compressor *dsc; 2093 struct dcn_dsc_state dsc_state = {0}; 2094 const uint32_t rd_buf_size = 100; 2095 struct pipe_ctx *pipe_ctx; 2096 ssize_t result = 0; 2097 int i, r, str_len = 30; 2098 2099 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2100 2101 if (!rd_buf) 2102 return -ENOMEM; 2103 2104 rd_buf_ptr = rd_buf; 2105 2106 for (i = 0; i < MAX_PIPES; i++) { 2107 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2108 if (pipe_ctx && pipe_ctx->stream && 2109 pipe_ctx->stream->link == aconnector->dc_link) 2110 break; 2111 } 2112 2113 if (!pipe_ctx) { 2114 kfree(rd_buf); 2115 return -ENXIO; 2116 } 2117 2118 dsc = pipe_ctx->stream_res.dsc; 2119 if (dsc) 2120 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2121 2122 snprintf(rd_buf_ptr, str_len, 2123 "%d\n", 2124 dsc_state.dsc_pic_width); 2125 rd_buf_ptr += str_len; 2126 2127 while (size) { 2128 if (*pos >= rd_buf_size) 2129 break; 2130 2131 r = put_user(*(rd_buf + result), buf); 2132 if (r) { 2133 kfree(rd_buf); 2134 return r; /* r = -EFAULT */ 2135 } 2136 2137 buf += 1; 2138 size -= 1; 2139 *pos += 1; 2140 result += 1; 2141 } 2142 2143 kfree(rd_buf); 2144 return result; 2145 } 2146 2147 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2148 size_t size, loff_t *pos) 2149 { 2150 char *rd_buf = NULL; 2151 char *rd_buf_ptr = NULL; 2152 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2153 struct display_stream_compressor *dsc; 2154 struct dcn_dsc_state dsc_state = {0}; 2155 const uint32_t rd_buf_size = 100; 2156 struct pipe_ctx *pipe_ctx; 2157 ssize_t result = 0; 2158 int i, r, str_len = 30; 2159 2160 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2161 2162 if (!rd_buf) 2163 return -ENOMEM; 2164 2165 rd_buf_ptr = rd_buf; 2166 2167 for (i = 0; i < MAX_PIPES; i++) { 2168 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2169 if (pipe_ctx && pipe_ctx->stream && 2170 pipe_ctx->stream->link == aconnector->dc_link) 2171 break; 2172 } 2173 2174 if (!pipe_ctx) { 2175 kfree(rd_buf); 2176 return -ENXIO; 2177 } 2178 2179 dsc = pipe_ctx->stream_res.dsc; 2180 if (dsc) 2181 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2182 2183 snprintf(rd_buf_ptr, str_len, 2184 "%d\n", 2185 dsc_state.dsc_pic_height); 2186 rd_buf_ptr += str_len; 2187 2188 while (size) { 2189 if (*pos >= rd_buf_size) 2190 break; 2191 2192 r = put_user(*(rd_buf + result), buf); 2193 if (r) { 2194 kfree(rd_buf); 2195 return r; /* r = -EFAULT */ 2196 } 2197 2198 buf += 1; 2199 size -= 1; 2200 *pos += 1; 2201 result += 1; 2202 } 2203 2204 kfree(rd_buf); 2205 return result; 2206 } 2207 2208 /* function: read DSC chunk size parameter on the connector 2209 * 2210 * The read function: dp_dsc_chunk_size_read 2211 * returns dsc chunk size set in the current configuration 2212 * The value is calculated automatically by DSC code 2213 * and depends on slice parameters and bpp target rate 2214 * The return is an integer: 0 or other positive integer 2215 * If 0 then DSC is disabled. 2216 * 2217 * Access it with the following command: 2218 * 2219 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2220 * 2221 * 0 - means that DSC is disabled 2222 */ 2223 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2224 size_t size, loff_t *pos) 2225 { 2226 char *rd_buf = NULL; 2227 char *rd_buf_ptr = NULL; 2228 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2229 struct display_stream_compressor *dsc; 2230 struct dcn_dsc_state dsc_state = {0}; 2231 const uint32_t rd_buf_size = 100; 2232 struct pipe_ctx *pipe_ctx; 2233 ssize_t result = 0; 2234 int i, r, str_len = 30; 2235 2236 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2237 2238 if (!rd_buf) 2239 return -ENOMEM; 2240 2241 rd_buf_ptr = rd_buf; 2242 2243 for (i = 0; i < MAX_PIPES; i++) { 2244 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2245 if (pipe_ctx && pipe_ctx->stream && 2246 pipe_ctx->stream->link == aconnector->dc_link) 2247 break; 2248 } 2249 2250 if (!pipe_ctx) { 2251 kfree(rd_buf); 2252 return -ENXIO; 2253 } 2254 2255 dsc = pipe_ctx->stream_res.dsc; 2256 if (dsc) 2257 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2258 2259 snprintf(rd_buf_ptr, str_len, 2260 "%d\n", 2261 dsc_state.dsc_chunk_size); 2262 rd_buf_ptr += str_len; 2263 2264 while (size) { 2265 if (*pos >= rd_buf_size) 2266 break; 2267 2268 r = put_user(*(rd_buf + result), buf); 2269 if (r) { 2270 kfree(rd_buf); 2271 return r; /* r = -EFAULT */ 2272 } 2273 2274 buf += 1; 2275 size -= 1; 2276 *pos += 1; 2277 result += 1; 2278 } 2279 2280 kfree(rd_buf); 2281 return result; 2282 } 2283 2284 /* function: read DSC slice bpg offset on the connector 2285 * 2286 * The read function: dp_dsc_slice_bpg_offset_read 2287 * returns dsc bpg slice offset set in the current configuration 2288 * The value is calculated automatically by DSC code 2289 * and depends on slice parameters and bpp target rate 2290 * The return is an integer: 0 or other positive integer 2291 * If 0 then DSC is disabled. 2292 * 2293 * Access it with the following command: 2294 * 2295 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2296 * 2297 * 0 - means that DSC is disabled 2298 */ 2299 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2300 size_t size, loff_t *pos) 2301 { 2302 char *rd_buf = NULL; 2303 char *rd_buf_ptr = NULL; 2304 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2305 struct display_stream_compressor *dsc; 2306 struct dcn_dsc_state dsc_state = {0}; 2307 const uint32_t rd_buf_size = 100; 2308 struct pipe_ctx *pipe_ctx; 2309 ssize_t result = 0; 2310 int i, r, str_len = 30; 2311 2312 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2313 2314 if (!rd_buf) 2315 return -ENOMEM; 2316 2317 rd_buf_ptr = rd_buf; 2318 2319 for (i = 0; i < MAX_PIPES; i++) { 2320 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2321 if (pipe_ctx && pipe_ctx->stream && 2322 pipe_ctx->stream->link == aconnector->dc_link) 2323 break; 2324 } 2325 2326 if (!pipe_ctx) { 2327 kfree(rd_buf); 2328 return -ENXIO; 2329 } 2330 2331 dsc = pipe_ctx->stream_res.dsc; 2332 if (dsc) 2333 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2334 2335 snprintf(rd_buf_ptr, str_len, 2336 "%d\n", 2337 dsc_state.dsc_slice_bpg_offset); 2338 rd_buf_ptr += str_len; 2339 2340 while (size) { 2341 if (*pos >= rd_buf_size) 2342 break; 2343 2344 r = put_user(*(rd_buf + result), buf); 2345 if (r) { 2346 kfree(rd_buf); 2347 return r; /* r = -EFAULT */ 2348 } 2349 2350 buf += 1; 2351 size -= 1; 2352 *pos += 1; 2353 result += 1; 2354 } 2355 2356 kfree(rd_buf); 2357 return result; 2358 } 2359 2360 2361 /* 2362 * function description: Read max_requested_bpc property from the connector 2363 * 2364 * Access it with the following command: 2365 * 2366 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2367 * 2368 */ 2369 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2370 size_t size, loff_t *pos) 2371 { 2372 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2373 struct drm_connector *connector = &aconnector->base; 2374 struct drm_device *dev = connector->dev; 2375 struct dm_connector_state *state; 2376 ssize_t result = 0; 2377 char *rd_buf = NULL; 2378 char *rd_buf_ptr = NULL; 2379 const uint32_t rd_buf_size = 10; 2380 int r; 2381 2382 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2383 2384 if (!rd_buf) 2385 return -ENOMEM; 2386 2387 mutex_lock(&dev->mode_config.mutex); 2388 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2389 2390 if (connector->state == NULL) 2391 goto unlock; 2392 2393 state = to_dm_connector_state(connector->state); 2394 2395 rd_buf_ptr = rd_buf; 2396 snprintf(rd_buf_ptr, rd_buf_size, 2397 "%u\n", 2398 state->base.max_requested_bpc); 2399 2400 while (size) { 2401 if (*pos >= rd_buf_size) 2402 break; 2403 2404 r = put_user(*(rd_buf + result), buf); 2405 if (r) { 2406 result = r; /* r = -EFAULT */ 2407 goto unlock; 2408 } 2409 buf += 1; 2410 size -= 1; 2411 *pos += 1; 2412 result += 1; 2413 } 2414 unlock: 2415 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2416 mutex_unlock(&dev->mode_config.mutex); 2417 kfree(rd_buf); 2418 return result; 2419 } 2420 2421 2422 /* 2423 * function description: Set max_requested_bpc property on the connector 2424 * 2425 * This function will not force the input BPC on connector, it will only 2426 * change the max value. This is equivalent to setting max_bpc through 2427 * xrandr. 2428 * 2429 * The BPC value written must be >= 6 and <= 16. Values outside of this 2430 * range will result in errors. 2431 * 2432 * BPC values: 2433 * 0x6 - 6 BPC 2434 * 0x8 - 8 BPC 2435 * 0xa - 10 BPC 2436 * 0xc - 12 BPC 2437 * 0x10 - 16 BPC 2438 * 2439 * Write the max_bpc in the following way: 2440 * 2441 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2442 * 2443 */ 2444 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2445 size_t size, loff_t *pos) 2446 { 2447 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2448 struct drm_connector *connector = &aconnector->base; 2449 struct dm_connector_state *state; 2450 struct drm_device *dev = connector->dev; 2451 char *wr_buf = NULL; 2452 uint32_t wr_buf_size = 42; 2453 int max_param_num = 1; 2454 long param[1] = {0}; 2455 uint8_t param_nums = 0; 2456 2457 if (size == 0) 2458 return -EINVAL; 2459 2460 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2461 2462 if (!wr_buf) { 2463 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2464 return -ENOSPC; 2465 } 2466 2467 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2468 (long *)param, buf, 2469 max_param_num, 2470 ¶m_nums)) { 2471 kfree(wr_buf); 2472 return -EINVAL; 2473 } 2474 2475 if (param_nums <= 0) { 2476 DRM_DEBUG_DRIVER("user data not be read\n"); 2477 kfree(wr_buf); 2478 return -EINVAL; 2479 } 2480 2481 if (param[0] < 6 || param[0] > 16) { 2482 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2483 kfree(wr_buf); 2484 return -EINVAL; 2485 } 2486 2487 mutex_lock(&dev->mode_config.mutex); 2488 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2489 2490 if (connector->state == NULL) 2491 goto unlock; 2492 2493 state = to_dm_connector_state(connector->state); 2494 state->base.max_requested_bpc = param[0]; 2495 unlock: 2496 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2497 mutex_unlock(&dev->mode_config.mutex); 2498 2499 kfree(wr_buf); 2500 return size; 2501 } 2502 2503 /* 2504 * Backlight at this moment. Read only. 2505 * As written to display, taking ABM and backlight lut into account. 2506 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2507 * 2508 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2509 */ 2510 static int current_backlight_show(struct seq_file *m, void *unused) 2511 { 2512 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2513 struct dc_link *link = aconnector->dc_link; 2514 unsigned int backlight; 2515 2516 backlight = dc_link_get_backlight_level(link); 2517 seq_printf(m, "0x%x\n", backlight); 2518 2519 return 0; 2520 } 2521 2522 /* 2523 * Backlight value that is being approached. Read only. 2524 * As written to display, taking ABM and backlight lut into account. 2525 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2526 * 2527 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2528 */ 2529 static int target_backlight_show(struct seq_file *m, void *unused) 2530 { 2531 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2532 struct dc_link *link = aconnector->dc_link; 2533 unsigned int backlight; 2534 2535 backlight = dc_link_get_target_backlight_pwm(link); 2536 seq_printf(m, "0x%x\n", backlight); 2537 2538 return 0; 2539 } 2540 2541 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2542 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2543 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2544 DEFINE_SHOW_ATTRIBUTE(output_bpc); 2545 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2546 #ifdef CONFIG_DRM_AMD_DC_HDCP 2547 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2548 #endif 2549 DEFINE_SHOW_ATTRIBUTE(internal_display); 2550 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2551 2552 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 2553 .owner = THIS_MODULE, 2554 .read = dp_dsc_clock_en_read, 2555 .write = dp_dsc_clock_en_write, 2556 .llseek = default_llseek 2557 }; 2558 2559 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 2560 .owner = THIS_MODULE, 2561 .read = dp_dsc_slice_width_read, 2562 .write = dp_dsc_slice_width_write, 2563 .llseek = default_llseek 2564 }; 2565 2566 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 2567 .owner = THIS_MODULE, 2568 .read = dp_dsc_slice_height_read, 2569 .write = dp_dsc_slice_height_write, 2570 .llseek = default_llseek 2571 }; 2572 2573 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 2574 .owner = THIS_MODULE, 2575 .read = dp_dsc_bits_per_pixel_read, 2576 .write = dp_dsc_bits_per_pixel_write, 2577 .llseek = default_llseek 2578 }; 2579 2580 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 2581 .owner = THIS_MODULE, 2582 .read = dp_dsc_pic_width_read, 2583 .llseek = default_llseek 2584 }; 2585 2586 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 2587 .owner = THIS_MODULE, 2588 .read = dp_dsc_pic_height_read, 2589 .llseek = default_llseek 2590 }; 2591 2592 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 2593 .owner = THIS_MODULE, 2594 .read = dp_dsc_chunk_size_read, 2595 .llseek = default_llseek 2596 }; 2597 2598 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 2599 .owner = THIS_MODULE, 2600 .read = dp_dsc_slice_bpg_offset_read, 2601 .llseek = default_llseek 2602 }; 2603 2604 static const struct file_operations trigger_hotplug_debugfs_fops = { 2605 .owner = THIS_MODULE, 2606 .write = trigger_hotplug, 2607 .llseek = default_llseek 2608 }; 2609 2610 static const struct file_operations dp_link_settings_debugfs_fops = { 2611 .owner = THIS_MODULE, 2612 .read = dp_link_settings_read, 2613 .write = dp_link_settings_write, 2614 .llseek = default_llseek 2615 }; 2616 2617 static const struct file_operations dp_phy_settings_debugfs_fop = { 2618 .owner = THIS_MODULE, 2619 .read = dp_phy_settings_read, 2620 .write = dp_phy_settings_write, 2621 .llseek = default_llseek 2622 }; 2623 2624 static const struct file_operations dp_phy_test_pattern_fops = { 2625 .owner = THIS_MODULE, 2626 .write = dp_phy_test_pattern_debugfs_write, 2627 .llseek = default_llseek 2628 }; 2629 2630 static const struct file_operations sdp_message_fops = { 2631 .owner = THIS_MODULE, 2632 .write = dp_sdp_message_debugfs_write, 2633 .llseek = default_llseek 2634 }; 2635 2636 static const struct file_operations dp_dpcd_address_debugfs_fops = { 2637 .owner = THIS_MODULE, 2638 .write = dp_dpcd_address_write, 2639 .llseek = default_llseek 2640 }; 2641 2642 static const struct file_operations dp_dpcd_size_debugfs_fops = { 2643 .owner = THIS_MODULE, 2644 .write = dp_dpcd_size_write, 2645 .llseek = default_llseek 2646 }; 2647 2648 static const struct file_operations dp_dpcd_data_debugfs_fops = { 2649 .owner = THIS_MODULE, 2650 .read = dp_dpcd_data_read, 2651 .write = dp_dpcd_data_write, 2652 .llseek = default_llseek 2653 }; 2654 2655 static const struct file_operations dp_max_bpc_debugfs_fops = { 2656 .owner = THIS_MODULE, 2657 .read = dp_max_bpc_read, 2658 .write = dp_max_bpc_write, 2659 .llseek = default_llseek 2660 }; 2661 2662 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 2663 .owner = THIS_MODULE, 2664 .write = dp_dsc_passthrough_set, 2665 .llseek = default_llseek 2666 }; 2667 2668 static const struct { 2669 char *name; 2670 const struct file_operations *fops; 2671 } dp_debugfs_entries[] = { 2672 {"link_settings", &dp_link_settings_debugfs_fops}, 2673 {"phy_settings", &dp_phy_settings_debugfs_fop}, 2674 {"lttpr_status", &dp_lttpr_status_fops}, 2675 {"test_pattern", &dp_phy_test_pattern_fops}, 2676 #ifdef CONFIG_DRM_AMD_DC_HDCP 2677 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 2678 #endif 2679 {"sdp_message", &sdp_message_fops}, 2680 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops}, 2681 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops}, 2682 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops}, 2683 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 2684 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 2685 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 2686 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 2687 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 2688 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 2689 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 2690 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 2691 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 2692 {"max_bpc", &dp_max_bpc_debugfs_fops}, 2693 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 2694 }; 2695 2696 #ifdef CONFIG_DRM_AMD_DC_HDCP 2697 static const struct { 2698 char *name; 2699 const struct file_operations *fops; 2700 } hdmi_debugfs_entries[] = { 2701 {"hdcp_sink_capability", &hdcp_sink_capability_fops} 2702 }; 2703 #endif 2704 /* 2705 * Force YUV420 output if available from the given mode 2706 */ 2707 static int force_yuv420_output_set(void *data, u64 val) 2708 { 2709 struct amdgpu_dm_connector *connector = data; 2710 2711 connector->force_yuv420_output = (bool)val; 2712 2713 return 0; 2714 } 2715 2716 /* 2717 * Check if YUV420 is forced when available from the given mode 2718 */ 2719 static int force_yuv420_output_get(void *data, u64 *val) 2720 { 2721 struct amdgpu_dm_connector *connector = data; 2722 2723 *val = connector->force_yuv420_output; 2724 2725 return 0; 2726 } 2727 2728 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 2729 force_yuv420_output_set, "%llu\n"); 2730 2731 /* 2732 * Read PSR state 2733 */ 2734 static int psr_get(void *data, u64 *val) 2735 { 2736 struct amdgpu_dm_connector *connector = data; 2737 struct dc_link *link = connector->dc_link; 2738 enum dc_psr_state state = PSR_STATE0; 2739 2740 dc_link_get_psr_state(link, &state); 2741 2742 *val = state; 2743 2744 return 0; 2745 } 2746 2747 /* 2748 * Set dmcub trace event IRQ enable or disable. 2749 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2750 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2751 */ 2752 static int dmcub_trace_event_state_set(void *data, u64 val) 2753 { 2754 struct amdgpu_device *adev = data; 2755 2756 if (val == 1 || val == 0) { 2757 dc_dmub_trace_event_control(adev->dm.dc, val); 2758 adev->dm.dmcub_trace_event_en = (bool)val; 2759 } else 2760 return 0; 2761 2762 return 0; 2763 } 2764 2765 /* 2766 * The interface doesn't need get function, so it will return the 2767 * value of zero 2768 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 2769 */ 2770 static int dmcub_trace_event_state_get(void *data, u64 *val) 2771 { 2772 struct amdgpu_device *adev = data; 2773 2774 *val = adev->dm.dmcub_trace_event_en; 2775 return 0; 2776 } 2777 2778 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 2779 dmcub_trace_event_state_set, "%llu\n"); 2780 2781 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 2782 2783 DEFINE_SHOW_ATTRIBUTE(current_backlight); 2784 DEFINE_SHOW_ATTRIBUTE(target_backlight); 2785 2786 static const struct { 2787 char *name; 2788 const struct file_operations *fops; 2789 } connector_debugfs_entries[] = { 2790 {"force_yuv420_output", &force_yuv420_output_fops}, 2791 {"output_bpc", &output_bpc_fops}, 2792 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 2793 {"internal_display", &internal_display_fops} 2794 }; 2795 2796 /* 2797 * Returns supported customized link rates by this eDP panel. 2798 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2799 */ 2800 static int edp_ilr_show(struct seq_file *m, void *unused) 2801 { 2802 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2803 struct dc_link *link = aconnector->dc_link; 2804 uint8_t supported_link_rates[16]; 2805 uint32_t link_rate_in_khz; 2806 uint32_t entry = 0; 2807 uint8_t dpcd_rev; 2808 2809 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 2810 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 2811 supported_link_rates, sizeof(supported_link_rates)); 2812 2813 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 2814 2815 if (dpcd_rev >= DP_DPCD_REV_13 && 2816 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 2817 2818 for (entry = 0; entry < 16; entry += 2) { 2819 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 2820 supported_link_rates[entry]) * 200; 2821 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 2822 } 2823 } else { 2824 seq_printf(m, "ILR is not supported by this eDP panel.\n"); 2825 } 2826 2827 return 0; 2828 } 2829 2830 /* 2831 * Set supported customized link rate to eDP panel. 2832 * 2833 * echo <lane_count> <link_rate option> > ilr_setting 2834 * 2835 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 2836 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 2837 * to set 4 lanes and 2.16 GHz 2838 */ 2839 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 2840 size_t size, loff_t *pos) 2841 { 2842 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 2843 struct dc_link *link = connector->dc_link; 2844 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 2845 struct dc *dc = (struct dc *)link->dc; 2846 struct dc_link_settings prefer_link_settings; 2847 char *wr_buf = NULL; 2848 const uint32_t wr_buf_size = 40; 2849 /* 0: lane_count; 1: link_rate */ 2850 int max_param_num = 2; 2851 uint8_t param_nums = 0; 2852 long param[2]; 2853 bool valid_input = true; 2854 2855 if (size == 0) 2856 return -EINVAL; 2857 2858 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2859 if (!wr_buf) 2860 return -ENOMEM; 2861 2862 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2863 (long *)param, buf, 2864 max_param_num, 2865 ¶m_nums)) { 2866 kfree(wr_buf); 2867 return -EINVAL; 2868 } 2869 2870 if (param_nums <= 0) { 2871 kfree(wr_buf); 2872 return -EINVAL; 2873 } 2874 2875 switch (param[0]) { 2876 case LANE_COUNT_ONE: 2877 case LANE_COUNT_TWO: 2878 case LANE_COUNT_FOUR: 2879 break; 2880 default: 2881 valid_input = false; 2882 break; 2883 } 2884 2885 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 2886 valid_input = false; 2887 2888 if (!valid_input) { 2889 kfree(wr_buf); 2890 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 2891 prefer_link_settings.use_link_rate_set = false; 2892 mutex_lock(&adev->dm.dc_lock); 2893 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 2894 mutex_unlock(&adev->dm.dc_lock); 2895 return size; 2896 } 2897 2898 /* save user force lane_count, link_rate to preferred settings 2899 * spread spectrum will not be changed 2900 */ 2901 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 2902 prefer_link_settings.lane_count = param[0]; 2903 prefer_link_settings.use_link_rate_set = true; 2904 prefer_link_settings.link_rate_set = param[1]; 2905 prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 2906 2907 mutex_lock(&adev->dm.dc_lock); 2908 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 2909 NULL, link, false); 2910 mutex_unlock(&adev->dm.dc_lock); 2911 2912 kfree(wr_buf); 2913 return size; 2914 } 2915 2916 static int edp_ilr_open(struct inode *inode, struct file *file) 2917 { 2918 return single_open(file, edp_ilr_show, inode->i_private); 2919 } 2920 2921 static const struct file_operations edp_ilr_debugfs_fops = { 2922 .owner = THIS_MODULE, 2923 .open = edp_ilr_open, 2924 .read = seq_read, 2925 .llseek = seq_lseek, 2926 .release = single_release, 2927 .write = edp_ilr_write 2928 }; 2929 2930 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 2931 { 2932 int i; 2933 struct dentry *dir = connector->base.debugfs_entry; 2934 2935 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2936 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2937 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 2938 debugfs_create_file(dp_debugfs_entries[i].name, 2939 0644, dir, connector, 2940 dp_debugfs_entries[i].fops); 2941 } 2942 } 2943 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 2944 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 2945 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 2946 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 2947 ¤t_backlight_fops); 2948 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 2949 &target_backlight_fops); 2950 debugfs_create_file("ilr_setting", 0644, dir, connector, 2951 &edp_ilr_debugfs_fops); 2952 } 2953 2954 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 2955 debugfs_create_file(connector_debugfs_entries[i].name, 2956 0644, dir, connector, 2957 connector_debugfs_entries[i].fops); 2958 } 2959 2960 connector->debugfs_dpcd_address = 0; 2961 connector->debugfs_dpcd_size = 0; 2962 2963 #ifdef CONFIG_DRM_AMD_DC_HDCP 2964 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 2965 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 2966 debugfs_create_file(hdmi_debugfs_entries[i].name, 2967 0644, dir, connector, 2968 hdmi_debugfs_entries[i].fops); 2969 } 2970 } 2971 #endif 2972 } 2973 2974 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 2975 /* 2976 * Set crc window coordinate x start 2977 */ 2978 static int crc_win_x_start_set(void *data, u64 val) 2979 { 2980 struct drm_crtc *crtc = data; 2981 struct drm_device *drm_dev = crtc->dev; 2982 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 2983 2984 spin_lock_irq(&drm_dev->event_lock); 2985 acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val; 2986 acrtc->dm_irq_params.crc_window.update_win = false; 2987 spin_unlock_irq(&drm_dev->event_lock); 2988 2989 return 0; 2990 } 2991 2992 /* 2993 * Get crc window coordinate x start 2994 */ 2995 static int crc_win_x_start_get(void *data, u64 *val) 2996 { 2997 struct drm_crtc *crtc = data; 2998 struct drm_device *drm_dev = crtc->dev; 2999 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3000 3001 spin_lock_irq(&drm_dev->event_lock); 3002 *val = acrtc->dm_irq_params.crc_window.x_start; 3003 spin_unlock_irq(&drm_dev->event_lock); 3004 3005 return 0; 3006 } 3007 3008 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3009 crc_win_x_start_set, "%llu\n"); 3010 3011 3012 /* 3013 * Set crc window coordinate y start 3014 */ 3015 static int crc_win_y_start_set(void *data, u64 val) 3016 { 3017 struct drm_crtc *crtc = data; 3018 struct drm_device *drm_dev = crtc->dev; 3019 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3020 3021 spin_lock_irq(&drm_dev->event_lock); 3022 acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val; 3023 acrtc->dm_irq_params.crc_window.update_win = false; 3024 spin_unlock_irq(&drm_dev->event_lock); 3025 3026 return 0; 3027 } 3028 3029 /* 3030 * Get crc window coordinate y start 3031 */ 3032 static int crc_win_y_start_get(void *data, u64 *val) 3033 { 3034 struct drm_crtc *crtc = data; 3035 struct drm_device *drm_dev = crtc->dev; 3036 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3037 3038 spin_lock_irq(&drm_dev->event_lock); 3039 *val = acrtc->dm_irq_params.crc_window.y_start; 3040 spin_unlock_irq(&drm_dev->event_lock); 3041 3042 return 0; 3043 } 3044 3045 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3046 crc_win_y_start_set, "%llu\n"); 3047 3048 /* 3049 * Set crc window coordinate x end 3050 */ 3051 static int crc_win_x_end_set(void *data, u64 val) 3052 { 3053 struct drm_crtc *crtc = data; 3054 struct drm_device *drm_dev = crtc->dev; 3055 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3056 3057 spin_lock_irq(&drm_dev->event_lock); 3058 acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val; 3059 acrtc->dm_irq_params.crc_window.update_win = false; 3060 spin_unlock_irq(&drm_dev->event_lock); 3061 3062 return 0; 3063 } 3064 3065 /* 3066 * Get crc window coordinate x end 3067 */ 3068 static int crc_win_x_end_get(void *data, u64 *val) 3069 { 3070 struct drm_crtc *crtc = data; 3071 struct drm_device *drm_dev = crtc->dev; 3072 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3073 3074 spin_lock_irq(&drm_dev->event_lock); 3075 *val = acrtc->dm_irq_params.crc_window.x_end; 3076 spin_unlock_irq(&drm_dev->event_lock); 3077 3078 return 0; 3079 } 3080 3081 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3082 crc_win_x_end_set, "%llu\n"); 3083 3084 /* 3085 * Set crc window coordinate y end 3086 */ 3087 static int crc_win_y_end_set(void *data, u64 val) 3088 { 3089 struct drm_crtc *crtc = data; 3090 struct drm_device *drm_dev = crtc->dev; 3091 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3092 3093 spin_lock_irq(&drm_dev->event_lock); 3094 acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val; 3095 acrtc->dm_irq_params.crc_window.update_win = false; 3096 spin_unlock_irq(&drm_dev->event_lock); 3097 3098 return 0; 3099 } 3100 3101 /* 3102 * Get crc window coordinate y end 3103 */ 3104 static int crc_win_y_end_get(void *data, u64 *val) 3105 { 3106 struct drm_crtc *crtc = data; 3107 struct drm_device *drm_dev = crtc->dev; 3108 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3109 3110 spin_lock_irq(&drm_dev->event_lock); 3111 *val = acrtc->dm_irq_params.crc_window.y_end; 3112 spin_unlock_irq(&drm_dev->event_lock); 3113 3114 return 0; 3115 } 3116 3117 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3118 crc_win_y_end_set, "%llu\n"); 3119 /* 3120 * Trigger to commit crc window 3121 */ 3122 static int crc_win_update_set(void *data, u64 val) 3123 { 3124 struct drm_crtc *new_crtc = data; 3125 struct drm_crtc *old_crtc = NULL; 3126 struct amdgpu_crtc *new_acrtc, *old_acrtc; 3127 struct amdgpu_device *adev = drm_to_adev(new_crtc->dev); 3128 struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk; 3129 3130 if (!crc_rd_wrk) 3131 return 0; 3132 3133 if (val) { 3134 spin_lock_irq(&adev_to_drm(adev)->event_lock); 3135 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 3136 if (crc_rd_wrk->crtc) { 3137 old_crtc = crc_rd_wrk->crtc; 3138 old_acrtc = to_amdgpu_crtc(old_crtc); 3139 } 3140 new_acrtc = to_amdgpu_crtc(new_crtc); 3141 3142 if (old_crtc && old_crtc != new_crtc) { 3143 old_acrtc->dm_irq_params.crc_window.activated = false; 3144 old_acrtc->dm_irq_params.crc_window.update_win = false; 3145 old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3146 3147 new_acrtc->dm_irq_params.crc_window.activated = true; 3148 new_acrtc->dm_irq_params.crc_window.update_win = true; 3149 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3150 crc_rd_wrk->crtc = new_crtc; 3151 } else { 3152 new_acrtc->dm_irq_params.crc_window.activated = true; 3153 new_acrtc->dm_irq_params.crc_window.update_win = true; 3154 new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0; 3155 crc_rd_wrk->crtc = new_crtc; 3156 } 3157 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 3158 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3159 } 3160 3161 return 0; 3162 } 3163 3164 /* 3165 * Get crc window update flag 3166 */ 3167 static int crc_win_update_get(void *data, u64 *val) 3168 { 3169 *val = 0; 3170 return 0; 3171 } 3172 3173 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3174 crc_win_update_set, "%llu\n"); 3175 3176 void crtc_debugfs_init(struct drm_crtc *crtc) 3177 { 3178 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 3179 3180 if (!dir) 3181 return; 3182 3183 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 3184 &crc_win_x_start_fops); 3185 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 3186 &crc_win_y_start_fops); 3187 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 3188 &crc_win_x_end_fops); 3189 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 3190 &crc_win_y_end_fops); 3191 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3192 &crc_win_update_fops); 3193 3194 } 3195 #endif 3196 /* 3197 * Writes DTN log state to the user supplied buffer. 3198 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3199 */ 3200 static ssize_t dtn_log_read( 3201 struct file *f, 3202 char __user *buf, 3203 size_t size, 3204 loff_t *pos) 3205 { 3206 struct amdgpu_device *adev = file_inode(f)->i_private; 3207 struct dc *dc = adev->dm.dc; 3208 struct dc_log_buffer_ctx log_ctx = { 0 }; 3209 ssize_t result = 0; 3210 3211 if (!buf || !size) 3212 return -EINVAL; 3213 3214 if (!dc->hwss.log_hw_state) 3215 return 0; 3216 3217 dc->hwss.log_hw_state(dc, &log_ctx); 3218 3219 if (*pos < log_ctx.pos) { 3220 size_t to_copy = log_ctx.pos - *pos; 3221 3222 to_copy = min(to_copy, size); 3223 3224 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 3225 *pos += to_copy; 3226 result = to_copy; 3227 } 3228 } 3229 3230 kfree(log_ctx.buf); 3231 3232 return result; 3233 } 3234 3235 /* 3236 * Writes DTN log state to dmesg when triggered via a write. 3237 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 3238 */ 3239 static ssize_t dtn_log_write( 3240 struct file *f, 3241 const char __user *buf, 3242 size_t size, 3243 loff_t *pos) 3244 { 3245 struct amdgpu_device *adev = file_inode(f)->i_private; 3246 struct dc *dc = adev->dm.dc; 3247 3248 /* Write triggers log output via dmesg. */ 3249 if (size == 0) 3250 return 0; 3251 3252 if (dc->hwss.log_hw_state) 3253 dc->hwss.log_hw_state(dc, NULL); 3254 3255 return size; 3256 } 3257 3258 static int mst_topo_show(struct seq_file *m, void *unused) 3259 { 3260 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3261 struct drm_device *dev = adev_to_drm(adev); 3262 struct drm_connector *connector; 3263 struct drm_connector_list_iter conn_iter; 3264 struct amdgpu_dm_connector *aconnector; 3265 3266 drm_connector_list_iter_begin(dev, &conn_iter); 3267 drm_for_each_connector_iter(connector, &conn_iter) { 3268 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3269 continue; 3270 3271 aconnector = to_amdgpu_dm_connector(connector); 3272 3273 /* Ensure we're only dumping the topology of a root mst node */ 3274 if (!aconnector->mst_mgr.mst_state) 3275 continue; 3276 3277 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 3278 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 3279 } 3280 drm_connector_list_iter_end(&conn_iter); 3281 3282 return 0; 3283 } 3284 3285 /* 3286 * Sets trigger hpd for MST topologies. 3287 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 3288 * All topologies will be disconnected if val of 0 is set . 3289 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3290 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3291 */ 3292 static int trigger_hpd_mst_set(void *data, u64 val) 3293 { 3294 struct amdgpu_device *adev = data; 3295 struct drm_device *dev = adev_to_drm(adev); 3296 struct drm_connector_list_iter iter; 3297 struct amdgpu_dm_connector *aconnector; 3298 struct drm_connector *connector; 3299 struct dc_link *link = NULL; 3300 3301 if (val == 1) { 3302 drm_connector_list_iter_begin(dev, &iter); 3303 drm_for_each_connector_iter(connector, &iter) { 3304 aconnector = to_amdgpu_dm_connector(connector); 3305 if (aconnector->dc_link->type == dc_connection_mst_branch && 3306 aconnector->mst_mgr.aux) { 3307 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3308 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 3309 } 3310 } 3311 } else if (val == 0) { 3312 drm_connector_list_iter_begin(dev, &iter); 3313 drm_for_each_connector_iter(connector, &iter) { 3314 aconnector = to_amdgpu_dm_connector(connector); 3315 if (!aconnector->dc_link) 3316 continue; 3317 3318 if (!aconnector->mst_port) 3319 continue; 3320 3321 link = aconnector->dc_link; 3322 dp_receiver_power_ctrl(link, false); 3323 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false); 3324 link->mst_stream_alloc_table.stream_count = 0; 3325 memset(link->mst_stream_alloc_table.stream_allocations, 0, 3326 sizeof(link->mst_stream_alloc_table.stream_allocations)); 3327 } 3328 } else { 3329 return 0; 3330 } 3331 drm_kms_helper_hotplug_event(dev); 3332 3333 return 0; 3334 } 3335 3336 /* 3337 * The interface doesn't need get function, so it will return the 3338 * value of zero 3339 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 3340 */ 3341 static int trigger_hpd_mst_get(void *data, u64 *val) 3342 { 3343 *val = 0; 3344 return 0; 3345 } 3346 3347 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 3348 trigger_hpd_mst_set, "%llu\n"); 3349 3350 3351 /* 3352 * Sets the force_timing_sync debug option from the given string. 3353 * All connected displays will be force synchronized immediately. 3354 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3355 */ 3356 static int force_timing_sync_set(void *data, u64 val) 3357 { 3358 struct amdgpu_device *adev = data; 3359 3360 adev->dm.force_timing_sync = (bool)val; 3361 3362 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 3363 3364 return 0; 3365 } 3366 3367 /* 3368 * Gets the force_timing_sync debug option value into the given buffer. 3369 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 3370 */ 3371 static int force_timing_sync_get(void *data, u64 *val) 3372 { 3373 struct amdgpu_device *adev = data; 3374 3375 *val = adev->dm.force_timing_sync; 3376 3377 return 0; 3378 } 3379 3380 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 3381 force_timing_sync_set, "%llu\n"); 3382 3383 3384 /* 3385 * Disables all HPD and HPD RX interrupt handling in the 3386 * driver when set to 1. Default is 0. 3387 */ 3388 static int disable_hpd_set(void *data, u64 val) 3389 { 3390 struct amdgpu_device *adev = data; 3391 3392 adev->dm.disable_hpd_irq = (bool)val; 3393 3394 return 0; 3395 } 3396 3397 3398 /* 3399 * Returns 1 if HPD and HPRX interrupt handling is disabled, 3400 * 0 otherwise. 3401 */ 3402 static int disable_hpd_get(void *data, u64 *val) 3403 { 3404 struct amdgpu_device *adev = data; 3405 3406 *val = adev->dm.disable_hpd_irq; 3407 3408 return 0; 3409 } 3410 3411 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 3412 disable_hpd_set, "%llu\n"); 3413 3414 #if defined(CONFIG_DRM_AMD_DC_DCN) 3415 /* 3416 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 3417 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 3418 */ 3419 static int dp_force_sst_set(void *data, u64 val) 3420 { 3421 struct amdgpu_device *adev = data; 3422 3423 adev->dm.dc->debug.set_mst_en_for_sst = val; 3424 3425 return 0; 3426 } 3427 3428 static int dp_force_sst_get(void *data, u64 *val) 3429 { 3430 struct amdgpu_device *adev = data; 3431 3432 *val = adev->dm.dc->debug.set_mst_en_for_sst; 3433 3434 return 0; 3435 } 3436 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 3437 dp_force_sst_set, "%llu\n"); 3438 3439 /* 3440 * Force DP2 sequence without VESA certified cable. 3441 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 3442 */ 3443 static int dp_ignore_cable_id_set(void *data, u64 val) 3444 { 3445 struct amdgpu_device *adev = data; 3446 3447 adev->dm.dc->debug.ignore_cable_id = val; 3448 3449 return 0; 3450 } 3451 3452 static int dp_ignore_cable_id_get(void *data, u64 *val) 3453 { 3454 struct amdgpu_device *adev = data; 3455 3456 *val = adev->dm.dc->debug.ignore_cable_id; 3457 3458 return 0; 3459 } 3460 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 3461 dp_ignore_cable_id_set, "%llu\n"); 3462 #endif 3463 3464 /* 3465 * Sets the DC visual confirm debug option from the given string. 3466 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 3467 */ 3468 static int visual_confirm_set(void *data, u64 val) 3469 { 3470 struct amdgpu_device *adev = data; 3471 3472 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 3473 3474 return 0; 3475 } 3476 3477 /* 3478 * Reads the DC visual confirm debug option value into the given buffer. 3479 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 3480 */ 3481 static int visual_confirm_get(void *data, u64 *val) 3482 { 3483 struct amdgpu_device *adev = data; 3484 3485 *val = adev->dm.dc->debug.visual_confirm; 3486 3487 return 0; 3488 } 3489 3490 DEFINE_SHOW_ATTRIBUTE(mst_topo); 3491 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 3492 visual_confirm_set, "%llu\n"); 3493 3494 /* 3495 * Dumps the DCC_EN bit for each pipe. 3496 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 3497 */ 3498 static ssize_t dcc_en_bits_read( 3499 struct file *f, 3500 char __user *buf, 3501 size_t size, 3502 loff_t *pos) 3503 { 3504 struct amdgpu_device *adev = file_inode(f)->i_private; 3505 struct dc *dc = adev->dm.dc; 3506 char *rd_buf = NULL; 3507 const uint32_t rd_buf_size = 32; 3508 uint32_t result = 0; 3509 int offset = 0; 3510 int num_pipes = dc->res_pool->pipe_count; 3511 int *dcc_en_bits; 3512 int i, r; 3513 3514 dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL); 3515 if (!dcc_en_bits) 3516 return -ENOMEM; 3517 3518 if (!dc->hwss.get_dcc_en_bits) { 3519 kfree(dcc_en_bits); 3520 return 0; 3521 } 3522 3523 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 3524 3525 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 3526 if (!rd_buf) { 3527 kfree(dcc_en_bits); 3528 return -ENOMEM; 3529 } 3530 3531 for (i = 0; i < num_pipes; i++) 3532 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 3533 "%d ", dcc_en_bits[i]); 3534 rd_buf[strlen(rd_buf)] = '\n'; 3535 3536 kfree(dcc_en_bits); 3537 3538 while (size) { 3539 if (*pos >= rd_buf_size) 3540 break; 3541 r = put_user(*(rd_buf + result), buf); 3542 if (r) { 3543 kfree(rd_buf); 3544 return r; /* r = -EFAULT */ 3545 } 3546 buf += 1; 3547 size -= 1; 3548 *pos += 1; 3549 result += 1; 3550 } 3551 3552 kfree(rd_buf); 3553 return result; 3554 } 3555 3556 void dtn_debugfs_init(struct amdgpu_device *adev) 3557 { 3558 static const struct file_operations dtn_log_fops = { 3559 .owner = THIS_MODULE, 3560 .read = dtn_log_read, 3561 .write = dtn_log_write, 3562 .llseek = default_llseek 3563 }; 3564 static const struct file_operations dcc_en_bits_fops = { 3565 .owner = THIS_MODULE, 3566 .read = dcc_en_bits_read, 3567 .llseek = default_llseek 3568 }; 3569 3570 struct drm_minor *minor = adev_to_drm(adev)->primary; 3571 struct dentry *root = minor->debugfs_root; 3572 3573 debugfs_create_file("amdgpu_mst_topology", 0444, root, 3574 adev, &mst_topo_fops); 3575 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 3576 &dtn_log_fops); 3577 #if defined(CONFIG_DRM_AMD_DC_DCN) 3578 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 3579 &dp_set_mst_en_for_sst_ops); 3580 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 3581 &dp_ignore_cable_id_ops); 3582 #endif 3583 3584 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 3585 &visual_confirm_fops); 3586 3587 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 3588 adev, &dmub_tracebuffer_fops); 3589 3590 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 3591 adev, &dmub_fw_state_fops); 3592 3593 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 3594 adev, &force_timing_sync_ops); 3595 3596 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 3597 adev, &dmcub_trace_event_state_fops); 3598 3599 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 3600 adev, &trigger_hpd_mst_ops); 3601 3602 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 3603 &dcc_en_bits_fops); 3604 3605 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 3606 &disable_hpd_ops); 3607 3608 } 3609