1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include <drm/drm_vblank.h> 27 #include <drm/drm_atomic_helper.h> 28 29 #include "dc.h" 30 #include "amdgpu.h" 31 #include "amdgpu_dm_psr.h" 32 #include "amdgpu_dm_crtc.h" 33 #include "amdgpu_dm_plane.h" 34 #include "amdgpu_dm_trace.h" 35 #include "amdgpu_dm_debugfs.h" 36 37 void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) 38 { 39 struct drm_crtc *crtc = &acrtc->base; 40 struct drm_device *dev = crtc->dev; 41 unsigned long flags; 42 43 drm_crtc_handle_vblank(crtc); 44 45 spin_lock_irqsave(&dev->event_lock, flags); 46 47 /* Send completion event for cursor-only commits */ 48 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 49 drm_crtc_send_vblank_event(crtc, acrtc->event); 50 drm_crtc_vblank_put(crtc); 51 acrtc->event = NULL; 52 } 53 54 spin_unlock_irqrestore(&dev->event_lock, flags); 55 } 56 57 bool modeset_required(struct drm_crtc_state *crtc_state, 58 struct dc_stream_state *new_stream, 59 struct dc_stream_state *old_stream) 60 { 61 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 62 } 63 64 bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc) 65 66 { 67 return acrtc->dm_irq_params.freesync_config.state == 68 VRR_STATE_ACTIVE_VARIABLE || 69 acrtc->dm_irq_params.freesync_config.state == 70 VRR_STATE_ACTIVE_FIXED; 71 } 72 73 int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable) 74 { 75 enum dc_irq_source irq_source; 76 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 77 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 78 int rc; 79 80 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; 81 82 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 83 84 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", 85 acrtc->crtc_id, enable ? "en" : "dis", rc); 86 return rc; 87 } 88 89 bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state) 90 { 91 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || 92 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 93 } 94 95 static void vblank_control_worker(struct work_struct *work) 96 { 97 struct vblank_control_work *vblank_work = 98 container_of(work, struct vblank_control_work, work); 99 struct amdgpu_display_manager *dm = vblank_work->dm; 100 101 mutex_lock(&dm->dc_lock); 102 103 if (vblank_work->enable) 104 dm->active_vblank_irq_count++; 105 else if (dm->active_vblank_irq_count) 106 dm->active_vblank_irq_count--; 107 108 dc_allow_idle_optimizations( 109 dm->dc, dm->active_vblank_irq_count == 0 ? true : false); 110 111 DRM_DEBUG_KMS("Allow idle optimizations (MALL): %d\n", dm->active_vblank_irq_count == 0); 112 113 /* 114 * Control PSR based on vblank requirements from OS 115 * 116 * If panel supports PSR SU, there's no need to disable PSR when OS is 117 * submitting fast atomic commits (we infer this by whether the OS 118 * requests vblank events). Fast atomic commits will simply trigger a 119 * full-frame-update (FFU); a specific case of selective-update (SU) 120 * where the SU region is the full hactive*vactive region. See 121 * fill_dc_dirty_rects(). 122 */ 123 if (vblank_work->stream && vblank_work->stream->link) { 124 if (vblank_work->enable) { 125 if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && 126 vblank_work->stream->link->psr_settings.psr_allow_active) 127 amdgpu_dm_psr_disable(vblank_work->stream); 128 } else if (vblank_work->stream->link->psr_settings.psr_feature_enabled && 129 !vblank_work->stream->link->psr_settings.psr_allow_active && 130 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 131 !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) && 132 #endif 133 vblank_work->acrtc->dm_irq_params.allow_psr_entry) { 134 amdgpu_dm_psr_enable(vblank_work->stream); 135 } 136 } 137 138 mutex_unlock(&dm->dc_lock); 139 140 dc_stream_release(vblank_work->stream); 141 142 kfree(vblank_work); 143 } 144 145 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) 146 { 147 enum dc_irq_source irq_source; 148 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 149 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 150 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); 151 struct amdgpu_display_manager *dm = &adev->dm; 152 struct vblank_control_work *work; 153 int rc = 0; 154 155 if (enable) { 156 /* vblank irq on -> Only need vupdate irq in vrr mode */ 157 if (amdgpu_dm_vrr_active(acrtc_state)) 158 rc = dm_set_vupdate_irq(crtc, true); 159 } else { 160 /* vblank irq off -> vupdate irq off */ 161 rc = dm_set_vupdate_irq(crtc, false); 162 } 163 164 if (rc) 165 return rc; 166 167 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 168 169 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 170 return -EBUSY; 171 172 if (amdgpu_in_reset(adev)) 173 return 0; 174 175 if (dm->vblank_control_workqueue) { 176 work = kzalloc(sizeof(*work), GFP_ATOMIC); 177 if (!work) 178 return -ENOMEM; 179 180 INIT_WORK(&work->work, vblank_control_worker); 181 work->dm = dm; 182 work->acrtc = acrtc; 183 work->enable = enable; 184 185 if (acrtc_state->stream) { 186 dc_stream_retain(acrtc_state->stream); 187 work->stream = acrtc_state->stream; 188 } 189 190 queue_work(dm->vblank_control_workqueue, &work->work); 191 } 192 193 return 0; 194 } 195 196 int dm_enable_vblank(struct drm_crtc *crtc) 197 { 198 return dm_set_vblank(crtc, true); 199 } 200 201 void dm_disable_vblank(struct drm_crtc *crtc) 202 { 203 dm_set_vblank(crtc, false); 204 } 205 206 static void dm_crtc_destroy_state(struct drm_crtc *crtc, 207 struct drm_crtc_state *state) 208 { 209 struct dm_crtc_state *cur = to_dm_crtc_state(state); 210 211 /* TODO Destroy dc_stream objects are stream object is flattened */ 212 if (cur->stream) 213 dc_stream_release(cur->stream); 214 215 216 __drm_atomic_helper_crtc_destroy_state(state); 217 218 219 kfree(state); 220 } 221 222 static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) 223 { 224 struct dm_crtc_state *state, *cur; 225 226 cur = to_dm_crtc_state(crtc->state); 227 228 if (WARN_ON(!crtc->state)) 229 return NULL; 230 231 state = kzalloc(sizeof(*state), GFP_KERNEL); 232 if (!state) 233 return NULL; 234 235 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 236 237 if (cur->stream) { 238 state->stream = cur->stream; 239 dc_stream_retain(state->stream); 240 } 241 242 state->active_planes = cur->active_planes; 243 state->vrr_infopacket = cur->vrr_infopacket; 244 state->abm_level = cur->abm_level; 245 state->vrr_supported = cur->vrr_supported; 246 state->freesync_config = cur->freesync_config; 247 state->cm_has_degamma = cur->cm_has_degamma; 248 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; 249 state->crc_skip_count = cur->crc_skip_count; 250 state->mpo_requested = cur->mpo_requested; 251 /* TODO Duplicate dc_stream after objects are stream object is flattened */ 252 253 return &state->base; 254 } 255 256 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) 257 { 258 drm_crtc_cleanup(crtc); 259 kfree(crtc); 260 } 261 262 static void dm_crtc_reset_state(struct drm_crtc *crtc) 263 { 264 struct dm_crtc_state *state; 265 266 if (crtc->state) 267 dm_crtc_destroy_state(crtc, crtc->state); 268 269 state = kzalloc(sizeof(*state), GFP_KERNEL); 270 if (WARN_ON(!state)) 271 return; 272 273 __drm_atomic_helper_crtc_reset(crtc, &state->base); 274 } 275 276 #ifdef CONFIG_DEBUG_FS 277 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) 278 { 279 crtc_debugfs_init(crtc); 280 281 return 0; 282 } 283 #endif 284 285 /* Implemented only the options currently available for the driver */ 286 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { 287 .reset = dm_crtc_reset_state, 288 .destroy = amdgpu_dm_crtc_destroy, 289 .set_config = drm_atomic_helper_set_config, 290 .page_flip = drm_atomic_helper_page_flip, 291 .atomic_duplicate_state = dm_crtc_duplicate_state, 292 .atomic_destroy_state = dm_crtc_destroy_state, 293 .set_crc_source = amdgpu_dm_crtc_set_crc_source, 294 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, 295 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, 296 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 297 .enable_vblank = dm_enable_vblank, 298 .disable_vblank = dm_disable_vblank, 299 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 300 #if defined(CONFIG_DEBUG_FS) 301 .late_register = amdgpu_dm_crtc_late_register, 302 #endif 303 }; 304 305 static void dm_crtc_helper_disable(struct drm_crtc *crtc) 306 { 307 } 308 309 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state) 310 { 311 struct drm_atomic_state *state = new_crtc_state->state; 312 struct drm_plane *plane; 313 int num_active = 0; 314 315 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) { 316 struct drm_plane_state *new_plane_state; 317 318 /* Cursor planes are "fake". */ 319 if (plane->type == DRM_PLANE_TYPE_CURSOR) 320 continue; 321 322 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 323 324 if (!new_plane_state) { 325 /* 326 * The plane is enable on the CRTC and hasn't changed 327 * state. This means that it previously passed 328 * validation and is therefore enabled. 329 */ 330 num_active += 1; 331 continue; 332 } 333 334 /* We need a framebuffer to be considered enabled. */ 335 num_active += (new_plane_state->fb != NULL); 336 } 337 338 return num_active; 339 } 340 341 static void dm_update_crtc_active_planes(struct drm_crtc *crtc, 342 struct drm_crtc_state *new_crtc_state) 343 { 344 struct dm_crtc_state *dm_new_crtc_state = 345 to_dm_crtc_state(new_crtc_state); 346 347 dm_new_crtc_state->active_planes = 0; 348 349 if (!dm_new_crtc_state->stream) 350 return; 351 352 dm_new_crtc_state->active_planes = 353 count_crtc_active_planes(new_crtc_state); 354 } 355 356 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, 357 const struct drm_display_mode *mode, 358 struct drm_display_mode *adjusted_mode) 359 { 360 return true; 361 } 362 363 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, 364 struct drm_atomic_state *state) 365 { 366 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 367 crtc); 368 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 369 struct dc *dc = adev->dm.dc; 370 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 371 int ret = -EINVAL; 372 373 trace_amdgpu_dm_crtc_atomic_check(crtc_state); 374 375 dm_update_crtc_active_planes(crtc, crtc_state); 376 377 if (WARN_ON(unlikely(!dm_crtc_state->stream && 378 modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) { 379 return ret; 380 } 381 382 /* 383 * We require the primary plane to be enabled whenever the CRTC is, otherwise 384 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other 385 * planes are disabled, which is not supported by the hardware. And there is legacy 386 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. 387 */ 388 if (crtc_state->enable && 389 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) { 390 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n"); 391 return -EINVAL; 392 } 393 394 /* In some use cases, like reset, no stream is attached */ 395 if (!dm_crtc_state->stream) 396 return 0; 397 398 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) 399 return 0; 400 401 DRM_DEBUG_ATOMIC("Failed DC stream validation\n"); 402 return ret; 403 } 404 405 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { 406 .disable = dm_crtc_helper_disable, 407 .atomic_check = dm_crtc_helper_atomic_check, 408 .mode_fixup = dm_crtc_helper_mode_fixup, 409 .get_scanout_position = amdgpu_crtc_get_scanout_position, 410 }; 411 412 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 413 struct drm_plane *plane, 414 uint32_t crtc_index) 415 { 416 struct amdgpu_crtc *acrtc = NULL; 417 struct drm_plane *cursor_plane; 418 bool is_dcn; 419 int res = -ENOMEM; 420 421 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); 422 if (!cursor_plane) 423 goto fail; 424 425 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 426 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); 427 428 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 429 if (!acrtc) 430 goto fail; 431 432 res = drm_crtc_init_with_planes( 433 dm->ddev, 434 &acrtc->base, 435 plane, 436 cursor_plane, 437 &amdgpu_dm_crtc_funcs, NULL); 438 439 if (res) 440 goto fail; 441 442 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); 443 444 /* Create (reset) the plane state */ 445 if (acrtc->base.funcs->reset) 446 acrtc->base.funcs->reset(&acrtc->base); 447 448 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; 449 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; 450 451 acrtc->crtc_id = crtc_index; 452 acrtc->base.enabled = false; 453 acrtc->otg_inst = -1; 454 455 dm->adev->mode_info.crtcs[crtc_index] = acrtc; 456 457 /* Don't enable DRM CRTC degamma property for DCE since it doesn't 458 * support programmable degamma anywhere. 459 */ 460 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 461 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 462 true, MAX_COLOR_LUT_ENTRIES); 463 464 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); 465 466 return 0; 467 468 fail: 469 kfree(acrtc); 470 kfree(cursor_plane); 471 return res; 472 } 473 474