1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_dm.h" 31 #include "dc.h" 32 #include "amdgpu_securedisplay.h" 33 34 static const char *const pipe_crc_sources[] = { 35 "none", 36 "crtc", 37 "crtc dither", 38 "dprx", 39 "dprx dither", 40 "auto", 41 }; 42 43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) 44 { 45 if (!source || !strcmp(source, "none")) 46 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE; 47 if (!strcmp(source, "auto") || !strcmp(source, "crtc")) 48 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC; 49 if (!strcmp(source, "dprx")) 50 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX; 51 if (!strcmp(source, "crtc dither")) 52 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER; 53 if (!strcmp(source, "dprx dither")) 54 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER; 55 56 return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID; 57 } 58 59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src) 60 { 61 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || 62 (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER); 63 } 64 65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src) 66 { 67 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) || 68 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER); 69 } 70 71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) 72 { 73 return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) || 74 (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) || 75 (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); 76 } 77 78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, 79 size_t *count) 80 { 81 *count = ARRAY_SIZE(pipe_crc_sources); 82 return pipe_crc_sources; 83 } 84 85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc) 87 { 88 struct drm_device *drm_dev = crtc->dev; 89 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 90 91 spin_lock_irq(&drm_dev->event_lock); 92 acrtc->dm_irq_params.window_param.x_start = 0; 93 acrtc->dm_irq_params.window_param.y_start = 0; 94 acrtc->dm_irq_params.window_param.x_end = 0; 95 acrtc->dm_irq_params.window_param.y_end = 0; 96 acrtc->dm_irq_params.window_param.activated = false; 97 acrtc->dm_irq_params.window_param.update_win = false; 98 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; 99 spin_unlock_irq(&drm_dev->event_lock); 100 } 101 102 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work) 103 { 104 struct crc_rd_work *crc_rd_wrk; 105 struct amdgpu_device *adev; 106 struct psp_context *psp; 107 struct securedisplay_cmd *securedisplay_cmd; 108 struct drm_crtc *crtc; 109 uint8_t phy_id; 110 int ret; 111 112 crc_rd_wrk = container_of(work, struct crc_rd_work, notify_ta_work); 113 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock); 114 crtc = crc_rd_wrk->crtc; 115 116 if (!crtc) { 117 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 118 return; 119 } 120 121 adev = drm_to_adev(crtc->dev); 122 psp = &adev->psp; 123 phy_id = crc_rd_wrk->phy_inst; 124 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock); 125 126 mutex_lock(&psp->securedisplay_context.mutex); 127 128 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 129 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 130 securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = 131 phy_id; 132 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC); 133 if (!ret) { 134 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 135 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 136 } 137 } 138 139 mutex_unlock(&psp->securedisplay_context.mutex); 140 } 141 142 static void 143 amdgpu_dm_forward_crc_window(struct work_struct *work) 144 { 145 struct crc_fw_work *crc_fw_wrk; 146 struct amdgpu_display_manager *dm; 147 148 crc_fw_wrk = container_of(work, struct crc_fw_work, forward_roi_work); 149 dm = crc_fw_wrk->dm; 150 151 mutex_lock(&dm->dc_lock); 152 dc_stream_forward_crc_window(dm->dc, &crc_fw_wrk->rect, crc_fw_wrk->stream, crc_fw_wrk->is_stop_cmd); 153 mutex_unlock(&dm->dc_lock); 154 155 kfree(crc_fw_wrk); 156 } 157 158 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc) 159 { 160 struct drm_device *drm_dev = crtc->dev; 161 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 162 bool ret = false; 163 164 spin_lock_irq(&drm_dev->event_lock); 165 ret = acrtc->dm_irq_params.window_param.activated; 166 spin_unlock_irq(&drm_dev->event_lock); 167 168 return ret; 169 } 170 #endif 171 172 int 173 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, 174 size_t *values_cnt) 175 { 176 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 177 178 if (source < 0) { 179 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 180 src_name, crtc->index); 181 return -EINVAL; 182 } 183 184 *values_cnt = 3; 185 return 0; 186 } 187 188 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, 189 struct dm_crtc_state *dm_crtc_state, 190 enum amdgpu_dm_pipe_crc_source source) 191 { 192 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 193 struct dc_stream_state *stream_state = dm_crtc_state->stream; 194 bool enable = amdgpu_dm_is_valid_crc_source(source); 195 int ret = 0; 196 197 /* Configuration will be deferred to stream enable. */ 198 if (!stream_state) 199 return -EINVAL; 200 201 mutex_lock(&adev->dm.dc_lock); 202 203 /* Enable CRTC CRC generation if necessary. */ 204 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 205 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 206 if (!enable) { 207 if (adev->dm.crc_rd_wrk) { 208 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); 209 spin_lock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); 210 211 if (adev->dm.crc_rd_wrk->crtc == crtc) { 212 /* stop ROI update on this crtc */ 213 dc_stream_forward_crc_window(stream_state->ctx->dc, 214 NULL, stream_state, true); 215 adev->dm.crc_rd_wrk->crtc = NULL; 216 } 217 spin_unlock_irq(&adev->dm.crc_rd_wrk->crc_rd_work_lock); 218 } 219 } 220 #endif 221 if (!dc_stream_configure_crc(stream_state->ctx->dc, 222 stream_state, NULL, enable, enable)) { 223 ret = -EINVAL; 224 goto unlock; 225 } 226 } 227 228 /* Configure dithering */ 229 if (!dm_need_crc_dither(source)) { 230 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8); 231 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 232 DYN_EXPANSION_DISABLE); 233 } else { 234 dc_stream_set_dither_option(stream_state, 235 DITHER_OPTION_DEFAULT); 236 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 237 DYN_EXPANSION_AUTO); 238 } 239 240 unlock: 241 mutex_unlock(&adev->dm.dc_lock); 242 243 return ret; 244 } 245 246 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 247 { 248 enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name); 249 enum amdgpu_dm_pipe_crc_source cur_crc_src; 250 struct drm_crtc_commit *commit; 251 struct dm_crtc_state *crtc_state; 252 struct drm_device *drm_dev = crtc->dev; 253 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 254 struct drm_dp_aux *aux = NULL; 255 bool enable = false; 256 bool enabled = false; 257 int ret = 0; 258 259 if (source < 0) { 260 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n", 261 src_name, crtc->index); 262 return -EINVAL; 263 } 264 265 ret = drm_modeset_lock(&crtc->mutex, NULL); 266 if (ret) 267 return ret; 268 269 spin_lock(&crtc->commit_lock); 270 commit = list_first_entry_or_null(&crtc->commit_list, 271 struct drm_crtc_commit, commit_entry); 272 if (commit) 273 drm_crtc_commit_get(commit); 274 spin_unlock(&crtc->commit_lock); 275 276 if (commit) { 277 /* 278 * Need to wait for all outstanding programming to complete 279 * in commit tail since it can modify CRC related fields and 280 * hardware state. Since we're holding the CRTC lock we're 281 * guaranteed that no other commit work can be queued off 282 * before we modify the state below. 283 */ 284 ret = wait_for_completion_interruptible_timeout( 285 &commit->hw_done, 10 * HZ); 286 if (ret) 287 goto cleanup; 288 } 289 290 enable = amdgpu_dm_is_valid_crc_source(source); 291 crtc_state = to_dm_crtc_state(crtc->state); 292 spin_lock_irq(&drm_dev->event_lock); 293 cur_crc_src = acrtc->dm_irq_params.crc_src; 294 spin_unlock_irq(&drm_dev->event_lock); 295 296 /* 297 * USER REQ SRC | CURRENT SRC | BEHAVIOR 298 * ----------------------------- 299 * None | None | Do nothing 300 * None | CRTC | Disable CRTC CRC, set default to dither 301 * None | DPRX | Disable DPRX CRC, need 'aux', set default to dither 302 * None | CRTC DITHER | Disable CRTC CRC 303 * None | DPRX DITHER | Disable DPRX CRC, need 'aux' 304 * CRTC | XXXX | Enable CRTC CRC, no dither 305 * DPRX | XXXX | Enable DPRX CRC, need 'aux', no dither 306 * CRTC DITHER | XXXX | Enable CRTC CRC, set dither 307 * DPRX DITHER | XXXX | Enable DPRX CRC, need 'aux', set dither 308 */ 309 if (dm_is_crc_source_dprx(source) || 310 (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE && 311 dm_is_crc_source_dprx(cur_crc_src))) { 312 struct amdgpu_dm_connector *aconn = NULL; 313 struct drm_connector *connector; 314 struct drm_connector_list_iter conn_iter; 315 316 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 317 drm_for_each_connector_iter(connector, &conn_iter) { 318 if (!connector->state || connector->state->crtc != crtc) 319 continue; 320 321 aconn = to_amdgpu_dm_connector(connector); 322 break; 323 } 324 drm_connector_list_iter_end(&conn_iter); 325 326 if (!aconn) { 327 DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); 328 ret = -EINVAL; 329 goto cleanup; 330 } 331 332 aux = (aconn->port) ? &aconn->port->aux : &aconn->dm_dp_aux.aux; 333 334 if (!aux) { 335 DRM_DEBUG_DRIVER("No dp aux for amd connector\n"); 336 ret = -EINVAL; 337 goto cleanup; 338 } 339 340 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) && 341 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) { 342 DRM_DEBUG_DRIVER("No DP connector available for CRC source\n"); 343 ret = -EINVAL; 344 goto cleanup; 345 } 346 347 } 348 349 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 350 amdgpu_dm_set_crc_window_default(crtc); 351 #endif 352 353 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { 354 ret = -EINVAL; 355 goto cleanup; 356 } 357 358 /* 359 * Reading the CRC requires the vblank interrupt handler to be 360 * enabled. Keep a reference until CRC capture stops. 361 */ 362 enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src); 363 if (!enabled && enable) { 364 ret = drm_crtc_vblank_get(crtc); 365 if (ret) 366 goto cleanup; 367 368 if (dm_is_crc_source_dprx(source)) { 369 if (drm_dp_start_crc(aux, crtc)) { 370 DRM_DEBUG_DRIVER("dp start crc failed\n"); 371 ret = -EINVAL; 372 goto cleanup; 373 } 374 } 375 } else if (enabled && !enable) { 376 drm_crtc_vblank_put(crtc); 377 if (dm_is_crc_source_dprx(source)) { 378 if (drm_dp_stop_crc(aux)) { 379 DRM_DEBUG_DRIVER("dp stop crc failed\n"); 380 ret = -EINVAL; 381 goto cleanup; 382 } 383 } 384 } 385 386 spin_lock_irq(&drm_dev->event_lock); 387 acrtc->dm_irq_params.crc_src = source; 388 spin_unlock_irq(&drm_dev->event_lock); 389 390 /* Reset crc_skipped on dm state */ 391 crtc_state->crc_skip_count = 0; 392 393 cleanup: 394 if (commit) 395 drm_crtc_commit_put(commit); 396 397 drm_modeset_unlock(&crtc->mutex); 398 399 return ret; 400 } 401 402 /** 403 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC. 404 * @crtc: DRM CRTC object. 405 * 406 * This function should be called at the end of a vblank, when the fb has been 407 * fully processed through the pipe. 408 */ 409 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc) 410 { 411 struct dm_crtc_state *crtc_state; 412 struct dc_stream_state *stream_state; 413 struct drm_device *drm_dev = NULL; 414 enum amdgpu_dm_pipe_crc_source cur_crc_src; 415 struct amdgpu_crtc *acrtc = NULL; 416 uint32_t crcs[3]; 417 unsigned long flags; 418 419 if (crtc == NULL) 420 return; 421 422 crtc_state = to_dm_crtc_state(crtc->state); 423 stream_state = crtc_state->stream; 424 acrtc = to_amdgpu_crtc(crtc); 425 drm_dev = crtc->dev; 426 427 spin_lock_irqsave(&drm_dev->event_lock, flags); 428 cur_crc_src = acrtc->dm_irq_params.crc_src; 429 spin_unlock_irqrestore(&drm_dev->event_lock, flags); 430 431 /* Early return if CRC capture is not enabled. */ 432 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 433 return; 434 435 /* 436 * Since flipping and crc enablement happen asynchronously, we - more 437 * often than not - will be returning an 'uncooked' crc on first frame. 438 * Probably because hw isn't ready yet. For added security, skip the 439 * first two CRC values. 440 */ 441 if (crtc_state->crc_skip_count < 2) { 442 crtc_state->crc_skip_count += 1; 443 return; 444 } 445 446 if (dm_is_crc_source_crtc(cur_crc_src)) { 447 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state, 448 &crcs[0], &crcs[1], &crcs[2])) 449 return; 450 451 drm_crtc_add_crc_entry(crtc, true, 452 drm_crtc_accurate_vblank_count(crtc), crcs); 453 } 454 } 455 456 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 457 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) 458 { 459 struct dc_stream_state *stream_state; 460 struct drm_device *drm_dev = NULL; 461 enum amdgpu_dm_pipe_crc_source cur_crc_src; 462 struct amdgpu_crtc *acrtc = NULL; 463 struct amdgpu_device *adev = NULL; 464 struct crc_rd_work *crc_rd_wrk; 465 struct crc_fw_work *crc_fw_wrk; 466 unsigned long flags1, flags2; 467 468 if (crtc == NULL) 469 return; 470 471 acrtc = to_amdgpu_crtc(crtc); 472 adev = drm_to_adev(crtc->dev); 473 drm_dev = crtc->dev; 474 475 spin_lock_irqsave(&drm_dev->event_lock, flags1); 476 stream_state = acrtc->dm_irq_params.stream; 477 cur_crc_src = acrtc->dm_irq_params.crc_src; 478 479 /* Early return if CRC capture is not enabled. */ 480 if (!amdgpu_dm_is_valid_crc_source(cur_crc_src)) 481 goto cleanup; 482 483 if (!dm_is_crc_source_crtc(cur_crc_src)) 484 goto cleanup; 485 486 if (!acrtc->dm_irq_params.window_param.activated) 487 goto cleanup; 488 489 if (acrtc->dm_irq_params.window_param.update_win) { 490 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 491 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 492 goto cleanup; 493 } 494 495 /* prepare work for dmub to update ROI */ 496 crc_fw_wrk = kzalloc(sizeof(*crc_fw_wrk), GFP_ATOMIC); 497 if (!crc_fw_wrk) 498 goto cleanup; 499 500 INIT_WORK(&crc_fw_wrk->forward_roi_work, amdgpu_dm_forward_crc_window); 501 crc_fw_wrk->dm = &adev->dm; 502 crc_fw_wrk->stream = stream_state; 503 crc_fw_wrk->rect.x = acrtc->dm_irq_params.window_param.x_start; 504 crc_fw_wrk->rect.y = acrtc->dm_irq_params.window_param.y_start; 505 crc_fw_wrk->rect.width = acrtc->dm_irq_params.window_param.x_end - 506 acrtc->dm_irq_params.window_param.x_start; 507 crc_fw_wrk->rect.height = acrtc->dm_irq_params.window_param.y_end - 508 acrtc->dm_irq_params.window_param.y_start; 509 schedule_work(&crc_fw_wrk->forward_roi_work); 510 511 acrtc->dm_irq_params.window_param.update_win = false; 512 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1; 513 514 } else { 515 if (acrtc->dm_irq_params.window_param.skip_frame_cnt) { 516 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1; 517 goto cleanup; 518 } 519 520 if (adev->dm.crc_rd_wrk) { 521 crc_rd_wrk = adev->dm.crc_rd_wrk; 522 spin_lock_irqsave(&crc_rd_wrk->crc_rd_work_lock, flags2); 523 crc_rd_wrk->phy_inst = stream_state->link->link_enc_hw_inst; 524 spin_unlock_irqrestore(&crc_rd_wrk->crc_rd_work_lock, flags2); 525 schedule_work(&crc_rd_wrk->notify_ta_work); 526 } 527 } 528 529 cleanup: 530 spin_unlock_irqrestore(&drm_dev->event_lock, flags1); 531 } 532 533 struct crc_rd_work *amdgpu_dm_crtc_secure_display_create_work(void) 534 { 535 struct crc_rd_work *crc_rd_wrk = NULL; 536 537 crc_rd_wrk = kzalloc(sizeof(*crc_rd_wrk), GFP_KERNEL); 538 539 if (!crc_rd_wrk) 540 return NULL; 541 542 spin_lock_init(&crc_rd_wrk->crc_rd_work_lock); 543 INIT_WORK(&crc_rd_wrk->notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read); 544 545 return crc_rd_wrk; 546 } 547 #endif 548