1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 #define AMDGPU_DM_MAX_NUM_EDP 2 50 51 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 52 53 /* 54 #include "include/amdgpu_dal_power_if.h" 55 #include "amdgpu_dm_irq.h" 56 */ 57 58 #include "irq_types.h" 59 #include "signal_types.h" 60 #include "amdgpu_dm_crc.h" 61 struct aux_payload; 62 enum aux_return_code_type; 63 64 /* Forward declarations */ 65 struct amdgpu_device; 66 struct amdgpu_crtc; 67 struct drm_device; 68 struct dc; 69 struct amdgpu_bo; 70 struct dmub_srv; 71 struct dc_plane_state; 72 struct dmub_notification; 73 74 struct common_irq_params { 75 struct amdgpu_device *adev; 76 enum dc_irq_source irq_src; 77 atomic64_t previous_timestamp; 78 }; 79 80 /** 81 * struct dm_compressor_info - Buffer info used by frame buffer compression 82 * @cpu_addr: MMIO cpu addr 83 * @bo_ptr: Pointer to the buffer object 84 * @gpu_addr: MMIO gpu addr 85 */ 86 struct dm_compressor_info { 87 void *cpu_addr; 88 struct amdgpu_bo *bo_ptr; 89 uint64_t gpu_addr; 90 }; 91 92 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 93 94 /** 95 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 96 * 97 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 98 * @dmub_notify: notification for callback function 99 * @adev: amdgpu_device pointer 100 */ 101 struct dmub_hpd_work { 102 struct work_struct handle_hpd_work; 103 struct dmub_notification *dmub_notify; 104 struct amdgpu_device *adev; 105 }; 106 107 /** 108 * struct vblank_control_work - Work data for vblank control 109 * @work: Kernel work data for the work event 110 * @dm: amdgpu display manager device 111 * @acrtc: amdgpu CRTC instance for which the event has occurred 112 * @stream: DC stream for which the event has occurred 113 * @enable: true if enabling vblank 114 */ 115 struct vblank_control_work { 116 struct work_struct work; 117 struct amdgpu_display_manager *dm; 118 struct amdgpu_crtc *acrtc; 119 struct dc_stream_state *stream; 120 bool enable; 121 }; 122 123 /** 124 * struct amdgpu_dm_backlight_caps - Information about backlight 125 * 126 * Describe the backlight support for ACPI or eDP AUX. 127 */ 128 struct amdgpu_dm_backlight_caps { 129 /** 130 * @ext_caps: Keep the data struct with all the information about the 131 * display support for HDR. 132 */ 133 union dpcd_sink_ext_caps *ext_caps; 134 /** 135 * @aux_min_input_signal: Min brightness value supported by the display 136 */ 137 u32 aux_min_input_signal; 138 /** 139 * @aux_max_input_signal: Max brightness value supported by the display 140 * in nits. 141 */ 142 u32 aux_max_input_signal; 143 /** 144 * @min_input_signal: minimum possible input in range 0-255. 145 */ 146 int min_input_signal; 147 /** 148 * @max_input_signal: maximum possible input in range 0-255. 149 */ 150 int max_input_signal; 151 /** 152 * @caps_valid: true if these values are from the ACPI interface. 153 */ 154 bool caps_valid; 155 /** 156 * @aux_support: Describes if the display supports AUX backlight. 157 */ 158 bool aux_support; 159 }; 160 161 /** 162 * struct dal_allocation - Tracks mapped FB memory for SMU communication 163 * @list: list of dal allocations 164 * @bo: GPU buffer object 165 * @cpu_ptr: CPU virtual address of the GPU buffer object 166 * @gpu_addr: GPU virtual address of the GPU buffer object 167 */ 168 struct dal_allocation { 169 struct list_head list; 170 struct amdgpu_bo *bo; 171 void *cpu_ptr; 172 u64 gpu_addr; 173 }; 174 175 /** 176 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 177 * offload work 178 */ 179 struct hpd_rx_irq_offload_work_queue { 180 /** 181 * @wq: workqueue structure to queue offload work. 182 */ 183 struct workqueue_struct *wq; 184 /** 185 * @offload_lock: To protect fields of offload work queue. 186 */ 187 spinlock_t offload_lock; 188 /** 189 * @is_handling_link_loss: Used to prevent inserting link loss event when 190 * we're handling link loss 191 */ 192 bool is_handling_link_loss; 193 /** 194 * @aconnector: The aconnector that this work queue is attached to 195 */ 196 struct amdgpu_dm_connector *aconnector; 197 }; 198 199 /** 200 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 201 */ 202 struct hpd_rx_irq_offload_work { 203 /** 204 * @work: offload work 205 */ 206 struct work_struct work; 207 /** 208 * @data: reference irq data which is used while handling offload work 209 */ 210 union hpd_irq_data data; 211 /** 212 * @offload_wq: offload work queue that this work is queued to 213 */ 214 struct hpd_rx_irq_offload_work_queue *offload_wq; 215 }; 216 217 /** 218 * struct amdgpu_display_manager - Central amdgpu display manager device 219 * 220 * @dc: Display Core control structure 221 * @adev: AMDGPU base driver structure 222 * @ddev: DRM base driver structure 223 * @display_indexes_num: Max number of display streams supported 224 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 225 * @backlight_dev: Backlight control device 226 * @backlight_link: Link on which to control backlight 227 * @backlight_caps: Capabilities of the backlight device 228 * @freesync_module: Module handling freesync calculations 229 * @hdcp_workqueue: AMDGPU content protection queue 230 * @fw_dmcu: Reference to DMCU firmware 231 * @dmcu_fw_version: Version of the DMCU firmware 232 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 233 * @cached_state: Caches device atomic state for suspend/resume 234 * @cached_dc_state: Cached state of content streams 235 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 236 * @force_timing_sync: set via debugfs. When set, indicates that all connected 237 * displays will be forced to synchronize. 238 * @dmcub_trace_event_en: enable dmcub trace events 239 * @dmub_outbox_params: DMUB Outbox parameters 240 * @num_of_edps: number of backlight eDPs 241 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 242 * driver when true 243 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 244 * transfers are done 245 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 246 */ 247 struct amdgpu_display_manager { 248 249 struct dc *dc; 250 251 /** 252 * @dmub_srv: 253 * 254 * DMUB service, used for controlling the DMUB on hardware 255 * that supports it. The pointer to the dmub_srv will be 256 * NULL on hardware that does not support it. 257 */ 258 struct dmub_srv *dmub_srv; 259 260 /** 261 * @dmub_notify: 262 * 263 * Notification from DMUB. 264 */ 265 266 struct dmub_notification *dmub_notify; 267 268 /** 269 * @dmub_callback: 270 * 271 * Callback functions to handle notification from DMUB. 272 */ 273 274 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 275 276 /** 277 * @dmub_thread_offload: 278 * 279 * Flag to indicate if callback is offload. 280 */ 281 282 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 283 284 /** 285 * @dmub_fb_info: 286 * 287 * Framebuffer regions for the DMUB. 288 */ 289 struct dmub_srv_fb_info *dmub_fb_info; 290 291 /** 292 * @dmub_fw: 293 * 294 * DMUB firmware, required on hardware that has DMUB support. 295 */ 296 const struct firmware *dmub_fw; 297 298 /** 299 * @dmub_bo: 300 * 301 * Buffer object for the DMUB. 302 */ 303 struct amdgpu_bo *dmub_bo; 304 305 /** 306 * @dmub_bo_gpu_addr: 307 * 308 * GPU virtual address for the DMUB buffer object. 309 */ 310 u64 dmub_bo_gpu_addr; 311 312 /** 313 * @dmub_bo_cpu_addr: 314 * 315 * CPU address for the DMUB buffer object. 316 */ 317 void *dmub_bo_cpu_addr; 318 319 /** 320 * @dmcub_fw_version: 321 * 322 * DMCUB firmware version. 323 */ 324 uint32_t dmcub_fw_version; 325 326 /** 327 * @cgs_device: 328 * 329 * The Common Graphics Services device. It provides an interface for 330 * accessing registers. 331 */ 332 struct cgs_device *cgs_device; 333 334 struct amdgpu_device *adev; 335 struct drm_device *ddev; 336 u16 display_indexes_num; 337 338 /** 339 * @atomic_obj: 340 * 341 * In combination with &dm_atomic_state it helps manage 342 * global atomic state that doesn't map cleanly into existing 343 * drm resources, like &dc_context. 344 */ 345 struct drm_private_obj atomic_obj; 346 347 /** 348 * @dc_lock: 349 * 350 * Guards access to DC functions that can issue register write 351 * sequences. 352 */ 353 struct mutex dc_lock; 354 355 /** 356 * @audio_lock: 357 * 358 * Guards access to audio instance changes. 359 */ 360 struct mutex audio_lock; 361 362 /** 363 * @audio_component: 364 * 365 * Used to notify ELD changes to sound driver. 366 */ 367 struct drm_audio_component *audio_component; 368 369 /** 370 * @audio_registered: 371 * 372 * True if the audio component has been registered 373 * successfully, false otherwise. 374 */ 375 bool audio_registered; 376 377 /** 378 * @irq_handler_list_low_tab: 379 * 380 * Low priority IRQ handler table. 381 * 382 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 383 * source. Low priority IRQ handlers are deferred to a workqueue to be 384 * processed. Hence, they can sleep. 385 * 386 * Note that handlers are called in the same order as they were 387 * registered (FIFO). 388 */ 389 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 390 391 /** 392 * @irq_handler_list_high_tab: 393 * 394 * High priority IRQ handler table. 395 * 396 * It is a n*m table, same as &irq_handler_list_low_tab. However, 397 * handlers in this table are not deferred and are called immediately. 398 */ 399 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 400 401 /** 402 * @pflip_params: 403 * 404 * Page flip IRQ parameters, passed to registered handlers when 405 * triggered. 406 */ 407 struct common_irq_params 408 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 409 410 /** 411 * @vblank_params: 412 * 413 * Vertical blanking IRQ parameters, passed to registered handlers when 414 * triggered. 415 */ 416 struct common_irq_params 417 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 418 419 /** 420 * @vline0_params: 421 * 422 * OTG vertical interrupt0 IRQ parameters, passed to registered 423 * handlers when triggered. 424 */ 425 struct common_irq_params 426 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 427 428 /** 429 * @vupdate_params: 430 * 431 * Vertical update IRQ parameters, passed to registered handlers when 432 * triggered. 433 */ 434 struct common_irq_params 435 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 436 437 /** 438 * @dmub_trace_params: 439 * 440 * DMUB trace event IRQ parameters, passed to registered handlers when 441 * triggered. 442 */ 443 struct common_irq_params 444 dmub_trace_params[1]; 445 446 struct common_irq_params 447 dmub_outbox_params[1]; 448 449 spinlock_t irq_handler_list_table_lock; 450 451 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 452 453 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 454 455 uint8_t num_of_edps; 456 457 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 458 459 struct mod_freesync *freesync_module; 460 #ifdef CONFIG_DRM_AMD_DC_HDCP 461 struct hdcp_workqueue *hdcp_workqueue; 462 #endif 463 464 /** 465 * @vblank_control_workqueue: 466 * 467 * Deferred work for vblank control events. 468 */ 469 struct workqueue_struct *vblank_control_workqueue; 470 471 struct drm_atomic_state *cached_state; 472 struct dc_state *cached_dc_state; 473 474 struct dm_compressor_info compressor; 475 476 const struct firmware *fw_dmcu; 477 uint32_t dmcu_fw_version; 478 /** 479 * @soc_bounding_box: 480 * 481 * gpu_info FW provided soc bounding box struct or 0 if not 482 * available in FW 483 */ 484 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 485 486 /** 487 * @active_vblank_irq_count: 488 * 489 * number of currently active vblank irqs 490 */ 491 uint32_t active_vblank_irq_count; 492 493 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 494 /** 495 * @crc_rd_wrk: 496 * 497 * Work to be executed in a separate thread to communicate with PSP. 498 */ 499 struct crc_rd_work *crc_rd_wrk; 500 #endif 501 /** 502 * @hpd_rx_offload_wq: 503 * 504 * Work queue to offload works of hpd_rx_irq 505 */ 506 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 507 /** 508 * @mst_encoders: 509 * 510 * fake encoders used for DP MST. 511 */ 512 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 513 bool force_timing_sync; 514 bool disable_hpd_irq; 515 bool dmcub_trace_event_en; 516 /** 517 * @da_list: 518 * 519 * DAL fb memory allocation list, for communication with SMU. 520 */ 521 struct list_head da_list; 522 struct completion dmub_aux_transfer_done; 523 struct workqueue_struct *delayed_hpd_wq; 524 525 /** 526 * @brightness: 527 * 528 * cached backlight values. 529 */ 530 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 531 /** 532 * @actual_brightness: 533 * 534 * last successfully applied backlight values. 535 */ 536 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 537 538 /** 539 * @aux_hpd_discon_quirk: 540 * 541 * quirk for hpd discon while aux is on-going. 542 * occurred on certain intel platform 543 */ 544 bool aux_hpd_discon_quirk; 545 }; 546 547 enum dsc_clock_force_state { 548 DSC_CLK_FORCE_DEFAULT = 0, 549 DSC_CLK_FORCE_ENABLE, 550 DSC_CLK_FORCE_DISABLE, 551 }; 552 553 struct dsc_preferred_settings { 554 enum dsc_clock_force_state dsc_force_enable; 555 uint32_t dsc_num_slices_v; 556 uint32_t dsc_num_slices_h; 557 uint32_t dsc_bits_per_pixel; 558 bool dsc_force_disable_passthrough; 559 }; 560 561 enum mst_progress_status { 562 MST_STATUS_DEFAULT = 0, 563 MST_PROBE = BIT(0), 564 MST_REMOTE_EDID = BIT(1), 565 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 566 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 567 }; 568 569 struct amdgpu_dm_connector { 570 571 struct drm_connector base; 572 uint32_t connector_id; 573 574 /* we need to mind the EDID between detect 575 and get modes due to analog/digital/tvencoder */ 576 struct edid *edid; 577 578 /* shared with amdgpu */ 579 struct amdgpu_hpd hpd; 580 581 /* number of modes generated from EDID at 'dc_sink' */ 582 int num_modes; 583 584 /* The 'old' sink - before an HPD. 585 * The 'current' sink is in dc_link->sink. */ 586 struct dc_sink *dc_sink; 587 struct dc_link *dc_link; 588 589 /** 590 * @dc_em_sink: Reference to the emulated (virtual) sink. 591 */ 592 struct dc_sink *dc_em_sink; 593 594 /* DM only */ 595 struct drm_dp_mst_topology_mgr mst_mgr; 596 struct amdgpu_dm_dp_aux dm_dp_aux; 597 struct drm_dp_mst_port *port; 598 struct amdgpu_dm_connector *mst_port; 599 struct drm_dp_aux *dsc_aux; 600 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 601 struct amdgpu_i2c_adapter *i2c; 602 603 /* Monitor range limits */ 604 /** 605 * @min_vfreq: Minimal frequency supported by the display in Hz. This 606 * value is set to zero when there is no FreeSync support. 607 */ 608 int min_vfreq; 609 610 /** 611 * @max_vfreq: Maximum frequency supported by the display in Hz. This 612 * value is set to zero when there is no FreeSync support. 613 */ 614 int max_vfreq ; 615 int pixel_clock_mhz; 616 617 /* Audio instance - protected by audio_lock. */ 618 int audio_inst; 619 620 struct mutex hpd_lock; 621 622 bool fake_enable; 623 #ifdef CONFIG_DEBUG_FS 624 uint32_t debugfs_dpcd_address; 625 uint32_t debugfs_dpcd_size; 626 #endif 627 bool force_yuv420_output; 628 struct dsc_preferred_settings dsc_settings; 629 union dp_downstream_port_present mst_downstream_port_present; 630 /* Cached display modes */ 631 struct drm_display_mode freesync_vid_base; 632 633 int psr_skip_count; 634 635 /* Record progress status of mst*/ 636 uint8_t mst_status; 637 }; 638 639 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 640 uint8_t flags, bool set) 641 { 642 if (set) 643 *status |= flags; 644 else 645 *status &= ~flags; 646 } 647 648 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 649 650 extern const struct amdgpu_ip_block_version dm_ip_block; 651 652 struct dm_plane_state { 653 struct drm_plane_state base; 654 struct dc_plane_state *dc_state; 655 }; 656 657 struct dm_crtc_state { 658 struct drm_crtc_state base; 659 struct dc_stream_state *stream; 660 661 bool cm_has_degamma; 662 bool cm_is_degamma_srgb; 663 664 bool mpo_requested; 665 666 int update_type; 667 int active_planes; 668 669 int crc_skip_count; 670 671 bool freesync_vrr_info_changed; 672 673 bool dsc_force_changed; 674 bool vrr_supported; 675 struct mod_freesync_config freesync_config; 676 struct dc_info_packet vrr_infopacket; 677 678 int abm_level; 679 }; 680 681 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 682 683 struct dm_atomic_state { 684 struct drm_private_state base; 685 686 struct dc_state *context; 687 }; 688 689 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 690 691 struct dm_connector_state { 692 struct drm_connector_state base; 693 694 enum amdgpu_rmx_type scaling; 695 uint8_t underscan_vborder; 696 uint8_t underscan_hborder; 697 bool underscan_enable; 698 bool freesync_capable; 699 #ifdef CONFIG_DRM_AMD_DC_HDCP 700 bool update_hdcp; 701 #endif 702 uint8_t abm_level; 703 int vcpi_slots; 704 uint64_t pbn; 705 }; 706 707 /** 708 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 709 * 710 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 711 * struct is useful to keep track of the display-specific information about 712 * FreeSync. 713 */ 714 struct amdgpu_hdmi_vsdb_info { 715 /** 716 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 717 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 718 */ 719 unsigned int amd_vsdb_version; 720 721 /** 722 * @freesync_supported: FreeSync Supported. 723 */ 724 bool freesync_supported; 725 726 /** 727 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 728 */ 729 unsigned int min_refresh_rate_hz; 730 731 /** 732 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 733 */ 734 unsigned int max_refresh_rate_hz; 735 }; 736 737 738 #define to_dm_connector_state(x)\ 739 container_of((x), struct dm_connector_state, base) 740 741 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 742 struct drm_connector_state * 743 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 744 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 745 struct drm_connector_state *state, 746 struct drm_property *property, 747 uint64_t val); 748 749 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 750 const struct drm_connector_state *state, 751 struct drm_property *property, 752 uint64_t *val); 753 754 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 755 756 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 757 struct amdgpu_dm_connector *aconnector, 758 int connector_type, 759 struct dc_link *link, 760 int link_index); 761 762 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 763 struct drm_display_mode *mode); 764 765 void dm_restore_drm_connector_state(struct drm_device *dev, 766 struct drm_connector *connector); 767 768 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 769 struct edid *edid); 770 771 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 772 773 #define MAX_COLOR_LUT_ENTRIES 4096 774 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 775 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 776 777 void amdgpu_dm_init_color_mod(void); 778 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 779 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 780 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 781 struct dc_plane_state *dc_plane_state); 782 783 void amdgpu_dm_update_connector_after_detect( 784 struct amdgpu_dm_connector *aconnector); 785 786 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 787 788 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, 789 struct dc_context *ctx, unsigned int link_index, 790 void *payload, void *operation_result); 791 792 bool check_seamless_boot_capability(struct amdgpu_device *adev); 793 794 struct dc_stream_state * 795 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 796 const struct drm_display_mode *drm_mode, 797 const struct dm_connector_state *dm_state, 798 const struct dc_stream_state *old_stream); 799 800 int dm_atomic_get_state(struct drm_atomic_state *state, 801 struct dm_atomic_state **dm_state); 802 803 struct amdgpu_dm_connector * 804 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 805 struct drm_crtc *crtc); 806 807 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 808 #endif /* __AMDGPU_DM_H__ */ 809