1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 61 struct common_irq_params { 62 struct amdgpu_device *adev; 63 enum dc_irq_source irq_src; 64 }; 65 66 /** 67 * struct irq_list_head - Linked-list for low context IRQ handlers. 68 * 69 * @head: The list_head within &struct handler_data 70 * @work: A work_struct containing the deferred handler work 71 */ 72 struct irq_list_head { 73 struct list_head head; 74 /* In case this interrupt needs post-processing, 'work' will be queued*/ 75 struct work_struct work; 76 }; 77 78 /** 79 * struct dm_compressor_info - Buffer info used by frame buffer compression 80 * @cpu_addr: MMIO cpu addr 81 * @bo_ptr: Pointer to the buffer object 82 * @gpu_addr: MMIO gpu addr 83 */ 84 struct dm_comressor_info { 85 void *cpu_addr; 86 struct amdgpu_bo *bo_ptr; 87 uint64_t gpu_addr; 88 }; 89 90 /** 91 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 92 * @min_input_signal: minimum possible input in range 0-255 93 * @max_input_signal: maximum possible input in range 0-255 94 * @caps_valid: true if these values are from the ACPI interface 95 */ 96 struct amdgpu_dm_backlight_caps { 97 int min_input_signal; 98 int max_input_signal; 99 bool caps_valid; 100 }; 101 102 /** 103 * struct amdgpu_display_manager - Central amdgpu display manager device 104 * 105 * @dc: Display Core control structure 106 * @adev: AMDGPU base driver structure 107 * @ddev: DRM base driver structure 108 * @display_indexes_num: Max number of display streams supported 109 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 110 * @backlight_dev: Backlight control device 111 * @backlight_link: Link on which to control backlight 112 * @backlight_caps: Capabilities of the backlight device 113 * @freesync_module: Module handling freesync calculations 114 * @fw_dmcu: Reference to DMCU firmware 115 * @dmcu_fw_version: Version of the DMCU firmware 116 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 117 * @cached_state: Caches device atomic state for suspend/resume 118 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 119 */ 120 struct amdgpu_display_manager { 121 122 struct dc *dc; 123 124 /** 125 * @cgs_device: 126 * 127 * The Common Graphics Services device. It provides an interface for 128 * accessing registers. 129 */ 130 struct cgs_device *cgs_device; 131 132 struct amdgpu_device *adev; 133 struct drm_device *ddev; 134 u16 display_indexes_num; 135 136 /** 137 * @atomic_obj: 138 * 139 * In combination with &dm_atomic_state it helps manage 140 * global atomic state that doesn't map cleanly into existing 141 * drm resources, like &dc_context. 142 */ 143 struct drm_private_obj atomic_obj; 144 145 /** 146 * @dc_lock: 147 * 148 * Guards access to DC functions that can issue register write 149 * sequences. 150 */ 151 struct mutex dc_lock; 152 153 /** 154 * @audio_lock: 155 * 156 * Guards access to audio instance changes. 157 */ 158 struct mutex audio_lock; 159 160 /** 161 * @audio_component: 162 * 163 * Used to notify ELD changes to sound driver. 164 */ 165 struct drm_audio_component *audio_component; 166 167 /** 168 * @audio_registered: 169 * 170 * True if the audio component has been registered 171 * successfully, false otherwise. 172 */ 173 bool audio_registered; 174 175 /** 176 * @irq_handler_list_low_tab: 177 * 178 * Low priority IRQ handler table. 179 * 180 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 181 * source. Low priority IRQ handlers are deferred to a workqueue to be 182 * processed. Hence, they can sleep. 183 * 184 * Note that handlers are called in the same order as they were 185 * registered (FIFO). 186 */ 187 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 188 189 /** 190 * @irq_handler_list_high_tab: 191 * 192 * High priority IRQ handler table. 193 * 194 * It is a n*m table, same as &irq_handler_list_low_tab. However, 195 * handlers in this table are not deferred and are called immediately. 196 */ 197 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 198 199 /** 200 * @pflip_params: 201 * 202 * Page flip IRQ parameters, passed to registered handlers when 203 * triggered. 204 */ 205 struct common_irq_params 206 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 207 208 /** 209 * @vblank_params: 210 * 211 * Vertical blanking IRQ parameters, passed to registered handlers when 212 * triggered. 213 */ 214 struct common_irq_params 215 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 216 217 /** 218 * @vupdate_params: 219 * 220 * Vertical update IRQ parameters, passed to registered handlers when 221 * triggered. 222 */ 223 struct common_irq_params 224 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 225 226 spinlock_t irq_handler_list_table_lock; 227 228 struct backlight_device *backlight_dev; 229 230 const struct dc_link *backlight_link; 231 struct amdgpu_dm_backlight_caps backlight_caps; 232 233 struct mod_freesync *freesync_module; 234 #ifdef CONFIG_DRM_AMD_DC_HDCP 235 struct hdcp_workqueue *hdcp_workqueue; 236 #endif 237 238 struct drm_atomic_state *cached_state; 239 240 struct dm_comressor_info compressor; 241 242 const struct firmware *fw_dmcu; 243 uint32_t dmcu_fw_version; 244 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 245 /** 246 * @soc_bounding_box: 247 * 248 * gpu_info FW provided soc bounding box struct or 0 if not 249 * available in FW 250 */ 251 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 252 #endif 253 }; 254 255 struct amdgpu_dm_connector { 256 257 struct drm_connector base; 258 uint32_t connector_id; 259 260 /* we need to mind the EDID between detect 261 and get modes due to analog/digital/tvencoder */ 262 struct edid *edid; 263 264 /* shared with amdgpu */ 265 struct amdgpu_hpd hpd; 266 267 /* number of modes generated from EDID at 'dc_sink' */ 268 int num_modes; 269 270 /* The 'old' sink - before an HPD. 271 * The 'current' sink is in dc_link->sink. */ 272 struct dc_sink *dc_sink; 273 struct dc_link *dc_link; 274 struct dc_sink *dc_em_sink; 275 276 /* DM only */ 277 struct drm_dp_mst_topology_mgr mst_mgr; 278 struct amdgpu_dm_dp_aux dm_dp_aux; 279 struct drm_dp_mst_port *port; 280 struct amdgpu_dm_connector *mst_port; 281 struct amdgpu_encoder *mst_encoder; 282 283 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 284 struct amdgpu_i2c_adapter *i2c; 285 286 /* Monitor range limits */ 287 int min_vfreq ; 288 int max_vfreq ; 289 int pixel_clock_mhz; 290 291 /* Audio instance - protected by audio_lock. */ 292 int audio_inst; 293 294 struct mutex hpd_lock; 295 296 bool fake_enable; 297 #ifdef CONFIG_DEBUG_FS 298 uint32_t debugfs_dpcd_address; 299 uint32_t debugfs_dpcd_size; 300 #endif 301 bool force_yuv420_output; 302 }; 303 304 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 305 306 extern const struct amdgpu_ip_block_version dm_ip_block; 307 308 struct amdgpu_framebuffer; 309 struct amdgpu_display_manager; 310 struct dc_validation_set; 311 struct dc_plane_state; 312 313 struct dm_plane_state { 314 struct drm_plane_state base; 315 struct dc_plane_state *dc_state; 316 }; 317 318 struct dm_crtc_state { 319 struct drm_crtc_state base; 320 struct dc_stream_state *stream; 321 322 bool cm_has_degamma; 323 bool cm_is_degamma_srgb; 324 325 int update_type; 326 int active_planes; 327 bool interrupts_enabled; 328 329 int crc_skip_count; 330 enum amdgpu_dm_pipe_crc_source crc_src; 331 332 bool freesync_timing_changed; 333 bool freesync_vrr_info_changed; 334 335 bool vrr_supported; 336 struct mod_freesync_config freesync_config; 337 struct mod_vrr_params vrr_params; 338 struct dc_info_packet vrr_infopacket; 339 340 int abm_level; 341 }; 342 343 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 344 345 struct dm_atomic_state { 346 struct drm_private_state base; 347 348 struct dc_state *context; 349 }; 350 351 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 352 353 struct dm_connector_state { 354 struct drm_connector_state base; 355 356 enum amdgpu_rmx_type scaling; 357 uint8_t underscan_vborder; 358 uint8_t underscan_hborder; 359 bool underscan_enable; 360 bool freesync_capable; 361 uint8_t abm_level; 362 }; 363 364 #define to_dm_connector_state(x)\ 365 container_of((x), struct dm_connector_state, base) 366 367 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 368 struct drm_connector_state * 369 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 370 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 371 struct drm_connector_state *state, 372 struct drm_property *property, 373 uint64_t val); 374 375 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 376 const struct drm_connector_state *state, 377 struct drm_property *property, 378 uint64_t *val); 379 380 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 381 382 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 383 struct amdgpu_dm_connector *aconnector, 384 int connector_type, 385 struct dc_link *link, 386 int link_index); 387 388 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 389 struct drm_display_mode *mode); 390 391 void dm_restore_drm_connector_state(struct drm_device *dev, 392 struct drm_connector *connector); 393 394 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 395 struct edid *edid); 396 397 #define MAX_COLOR_LUT_ENTRIES 4096 398 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 399 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 400 401 void amdgpu_dm_init_color_mod(void); 402 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 403 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 404 struct dc_plane_state *dc_plane_state); 405 406 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 407 408 #endif /* __AMDGPU_DM_H__ */ 409