1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic.h> 31 #include "dc.h" 32 33 /* 34 * This file contains the definition for amdgpu_display_manager 35 * and its API for amdgpu driver's use. 36 * This component provides all the display related functionality 37 * and this is the only component that calls DAL API. 38 * The API contained here intended for amdgpu driver use. 39 * The API that is called directly from KMS framework is located 40 * in amdgpu_dm_kms.h file 41 */ 42 43 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 44 /* 45 #include "include/amdgpu_dal_power_if.h" 46 #include "amdgpu_dm_irq.h" 47 */ 48 49 #include "irq_types.h" 50 #include "signal_types.h" 51 52 /* Forward declarations */ 53 struct amdgpu_device; 54 struct drm_device; 55 struct amdgpu_dm_irq_handler_data; 56 57 struct amdgpu_dm_prev_state { 58 struct drm_framebuffer *fb; 59 int32_t x; 60 int32_t y; 61 struct drm_display_mode mode; 62 }; 63 64 struct common_irq_params { 65 struct amdgpu_device *adev; 66 enum dc_irq_source irq_src; 67 }; 68 69 struct irq_list_head { 70 struct list_head head; 71 /* In case this interrupt needs post-processing, 'work' will be queued*/ 72 struct work_struct work; 73 }; 74 75 #if defined(CONFIG_DRM_AMD_DC_FBC) 76 struct dm_comressor_info { 77 void *cpu_addr; 78 struct amdgpu_bo *bo_ptr; 79 uint64_t gpu_addr; 80 }; 81 #endif 82 83 84 struct amdgpu_display_manager { 85 struct dal *dal; 86 struct dc *dc; 87 struct cgs_device *cgs_device; 88 /* lock to be used when DAL is called from SYNC IRQ context */ 89 spinlock_t dal_lock; 90 91 struct amdgpu_device *adev; /*AMD base driver*/ 92 struct drm_device *ddev; /*DRM base driver*/ 93 u16 display_indexes_num; 94 95 struct amdgpu_dm_prev_state prev_state; 96 97 /* 98 * 'irq_source_handler_table' holds a list of handlers 99 * per (DAL) IRQ source. 100 * 101 * Each IRQ source may need to be handled at different contexts. 102 * By 'context' we mean, for example: 103 * - The ISR context, which is the direct interrupt handler. 104 * - The 'deferred' context - this is the post-processing of the 105 * interrupt, but at a lower priority. 106 * 107 * Note that handlers are called in the same order as they were 108 * registered (FIFO). 109 */ 110 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 111 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 112 113 struct common_irq_params 114 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 115 116 struct common_irq_params 117 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 118 119 /* this spin lock synchronizes access to 'irq_handler_list_table' */ 120 spinlock_t irq_handler_list_table_lock; 121 122 /* Timer-related data. */ 123 struct list_head timer_handler_list; 124 struct workqueue_struct *timer_workqueue; 125 126 /* Use dal_mutex for any activity which is NOT syncronized by 127 * DRM mode setting locks. 128 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without* 129 * DRM mode setting locks being acquired. This is where dal_mutex 130 * is acquired before calling into DAL. */ 131 struct mutex dal_mutex; 132 133 struct backlight_device *backlight_dev; 134 135 const struct dc_link *backlight_link; 136 137 struct work_struct mst_hotplug_work; 138 139 struct mod_freesync *freesync_module; 140 141 /** 142 * Caches device atomic state for suspend/resume 143 */ 144 struct drm_atomic_state *cached_state; 145 #if defined(CONFIG_DRM_AMD_DC_FBC) 146 struct dm_comressor_info compressor; 147 #endif 148 }; 149 150 struct amdgpu_dm_connector { 151 152 struct drm_connector base; 153 uint32_t connector_id; 154 155 /* we need to mind the EDID between detect 156 and get modes due to analog/digital/tvencoder */ 157 struct edid *edid; 158 159 /* shared with amdgpu */ 160 struct amdgpu_hpd hpd; 161 162 /* number of modes generated from EDID at 'dc_sink' */ 163 int num_modes; 164 165 /* The 'old' sink - before an HPD. 166 * The 'current' sink is in dc_link->sink. */ 167 struct dc_sink *dc_sink; 168 struct dc_link *dc_link; 169 struct dc_sink *dc_em_sink; 170 171 /* DM only */ 172 struct drm_dp_mst_topology_mgr mst_mgr; 173 struct amdgpu_dm_dp_aux dm_dp_aux; 174 struct drm_dp_mst_port *port; 175 struct amdgpu_dm_connector *mst_port; 176 struct amdgpu_encoder *mst_encoder; 177 178 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 179 struct amdgpu_i2c_adapter *i2c; 180 181 /* Monitor range limits */ 182 int min_vfreq ; 183 int max_vfreq ; 184 int pixel_clock_mhz; 185 186 /*freesync caps*/ 187 struct mod_freesync_caps caps; 188 189 struct mutex hpd_lock; 190 191 bool fake_enable; 192 193 bool mst_connected; 194 }; 195 196 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 197 198 extern const struct amdgpu_ip_block_version dm_ip_block; 199 200 struct amdgpu_framebuffer; 201 struct amdgpu_display_manager; 202 struct dc_validation_set; 203 struct dc_plane_state; 204 205 struct dm_plane_state { 206 struct drm_plane_state base; 207 struct dc_plane_state *dc_state; 208 }; 209 210 struct dm_crtc_state { 211 struct drm_crtc_state base; 212 struct dc_stream_state *stream; 213 }; 214 215 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 216 217 struct dm_atomic_state { 218 struct drm_atomic_state base; 219 220 struct dc_state *context; 221 }; 222 223 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 224 225 struct dm_connector_state { 226 struct drm_connector_state base; 227 228 enum amdgpu_rmx_type scaling; 229 uint8_t underscan_vborder; 230 uint8_t underscan_hborder; 231 bool underscan_enable; 232 struct mod_freesync_user_enable user_enable; 233 }; 234 235 #define to_dm_connector_state(x)\ 236 container_of((x), struct dm_connector_state, base) 237 238 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 239 struct drm_connector_state * 240 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 241 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 242 struct drm_connector_state *state, 243 struct drm_property *property, 244 uint64_t val); 245 246 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 247 const struct drm_connector_state *state, 248 struct drm_property *property, 249 uint64_t *val); 250 251 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 252 253 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 254 struct amdgpu_dm_connector *aconnector, 255 int connector_type, 256 struct dc_link *link, 257 int link_index); 258 259 int amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 260 struct drm_display_mode *mode); 261 262 void dm_restore_drm_connector_state(struct drm_device *dev, 263 struct drm_connector *connector); 264 265 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 266 struct edid *edid); 267 268 void 269 amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector); 270 271 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 272 273 #endif /* __AMDGPU_DM_H__ */ 274