1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 #define AMDGPU_DM_MAX_NUM_EDP 2 50 /* 51 #include "include/amdgpu_dal_power_if.h" 52 #include "amdgpu_dm_irq.h" 53 */ 54 55 #include "irq_types.h" 56 #include "signal_types.h" 57 #include "amdgpu_dm_crc.h" 58 struct aux_payload; 59 enum aux_return_code_type; 60 61 /* Forward declarations */ 62 struct amdgpu_device; 63 struct drm_device; 64 struct dc; 65 struct amdgpu_bo; 66 struct dmub_srv; 67 struct dc_plane_state; 68 struct dmub_notification; 69 70 struct common_irq_params { 71 struct amdgpu_device *adev; 72 enum dc_irq_source irq_src; 73 atomic64_t previous_timestamp; 74 }; 75 76 /** 77 * struct dm_compressor_info - Buffer info used by frame buffer compression 78 * @cpu_addr: MMIO cpu addr 79 * @bo_ptr: Pointer to the buffer object 80 * @gpu_addr: MMIO gpu addr 81 */ 82 struct dm_compressor_info { 83 void *cpu_addr; 84 struct amdgpu_bo *bo_ptr; 85 uint64_t gpu_addr; 86 }; 87 88 /** 89 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 90 * @mall_work: work for mall stutter 91 * @dm: amdgpu display manager device 92 * @otg_inst: otg instance of which vblank is being set 93 * @enable: true if enable vblank 94 */ 95 struct vblank_workqueue { 96 struct work_struct mall_work; 97 struct amdgpu_display_manager *dm; 98 int otg_inst; 99 bool enable; 100 }; 101 102 /** 103 * struct amdgpu_dm_backlight_caps - Information about backlight 104 * 105 * Describe the backlight support for ACPI or eDP AUX. 106 */ 107 struct amdgpu_dm_backlight_caps { 108 /** 109 * @ext_caps: Keep the data struct with all the information about the 110 * display support for HDR. 111 */ 112 union dpcd_sink_ext_caps *ext_caps; 113 /** 114 * @aux_min_input_signal: Min brightness value supported by the display 115 */ 116 u32 aux_min_input_signal; 117 /** 118 * @aux_max_input_signal: Max brightness value supported by the display 119 * in nits. 120 */ 121 u32 aux_max_input_signal; 122 /** 123 * @min_input_signal: minimum possible input in range 0-255. 124 */ 125 int min_input_signal; 126 /** 127 * @max_input_signal: maximum possible input in range 0-255. 128 */ 129 int max_input_signal; 130 /** 131 * @caps_valid: true if these values are from the ACPI interface. 132 */ 133 bool caps_valid; 134 /** 135 * @aux_support: Describes if the display supports AUX backlight. 136 */ 137 bool aux_support; 138 }; 139 140 /** 141 * struct dal_allocation - Tracks mapped FB memory for SMU communication 142 */ 143 struct dal_allocation { 144 struct list_head list; 145 struct amdgpu_bo *bo; 146 void *cpu_ptr; 147 u64 gpu_addr; 148 }; 149 150 /** 151 * struct amdgpu_display_manager - Central amdgpu display manager device 152 * 153 * @dc: Display Core control structure 154 * @adev: AMDGPU base driver structure 155 * @ddev: DRM base driver structure 156 * @display_indexes_num: Max number of display streams supported 157 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 158 * @backlight_dev: Backlight control device 159 * @backlight_link: Link on which to control backlight 160 * @backlight_caps: Capabilities of the backlight device 161 * @freesync_module: Module handling freesync calculations 162 * @hdcp_workqueue: AMDGPU content protection queue 163 * @fw_dmcu: Reference to DMCU firmware 164 * @dmcu_fw_version: Version of the DMCU firmware 165 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 166 * @cached_state: Caches device atomic state for suspend/resume 167 * @cached_dc_state: Cached state of content streams 168 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 169 * @force_timing_sync: set via debugfs. When set, indicates that all connected 170 * displays will be forced to synchronize. 171 * @dmcub_trace_event_en: enable dmcub trace events 172 */ 173 struct amdgpu_display_manager { 174 175 struct dc *dc; 176 177 /** 178 * @dmub_srv: 179 * 180 * DMUB service, used for controlling the DMUB on hardware 181 * that supports it. The pointer to the dmub_srv will be 182 * NULL on hardware that does not support it. 183 */ 184 struct dmub_srv *dmub_srv; 185 186 struct dmub_notification *dmub_notify; 187 188 /** 189 * @dmub_fb_info: 190 * 191 * Framebuffer regions for the DMUB. 192 */ 193 struct dmub_srv_fb_info *dmub_fb_info; 194 195 /** 196 * @dmub_fw: 197 * 198 * DMUB firmware, required on hardware that has DMUB support. 199 */ 200 const struct firmware *dmub_fw; 201 202 /** 203 * @dmub_bo: 204 * 205 * Buffer object for the DMUB. 206 */ 207 struct amdgpu_bo *dmub_bo; 208 209 /** 210 * @dmub_bo_gpu_addr: 211 * 212 * GPU virtual address for the DMUB buffer object. 213 */ 214 u64 dmub_bo_gpu_addr; 215 216 /** 217 * @dmub_bo_cpu_addr: 218 * 219 * CPU address for the DMUB buffer object. 220 */ 221 void *dmub_bo_cpu_addr; 222 223 /** 224 * @dmcub_fw_version: 225 * 226 * DMCUB firmware version. 227 */ 228 uint32_t dmcub_fw_version; 229 230 /** 231 * @cgs_device: 232 * 233 * The Common Graphics Services device. It provides an interface for 234 * accessing registers. 235 */ 236 struct cgs_device *cgs_device; 237 238 struct amdgpu_device *adev; 239 struct drm_device *ddev; 240 u16 display_indexes_num; 241 242 /** 243 * @atomic_obj: 244 * 245 * In combination with &dm_atomic_state it helps manage 246 * global atomic state that doesn't map cleanly into existing 247 * drm resources, like &dc_context. 248 */ 249 struct drm_private_obj atomic_obj; 250 251 /** 252 * @dc_lock: 253 * 254 * Guards access to DC functions that can issue register write 255 * sequences. 256 */ 257 struct mutex dc_lock; 258 259 /** 260 * @audio_lock: 261 * 262 * Guards access to audio instance changes. 263 */ 264 struct mutex audio_lock; 265 266 #if defined(CONFIG_DRM_AMD_DC_DCN) 267 /** 268 * @vblank_lock: 269 * 270 * Guards access to deferred vblank work state. 271 */ 272 spinlock_t vblank_lock; 273 #endif 274 275 /** 276 * @audio_component: 277 * 278 * Used to notify ELD changes to sound driver. 279 */ 280 struct drm_audio_component *audio_component; 281 282 /** 283 * @audio_registered: 284 * 285 * True if the audio component has been registered 286 * successfully, false otherwise. 287 */ 288 bool audio_registered; 289 290 /** 291 * @irq_handler_list_low_tab: 292 * 293 * Low priority IRQ handler table. 294 * 295 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 296 * source. Low priority IRQ handlers are deferred to a workqueue to be 297 * processed. Hence, they can sleep. 298 * 299 * Note that handlers are called in the same order as they were 300 * registered (FIFO). 301 */ 302 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 303 304 /** 305 * @irq_handler_list_high_tab: 306 * 307 * High priority IRQ handler table. 308 * 309 * It is a n*m table, same as &irq_handler_list_low_tab. However, 310 * handlers in this table are not deferred and are called immediately. 311 */ 312 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 313 314 /** 315 * @pflip_params: 316 * 317 * Page flip IRQ parameters, passed to registered handlers when 318 * triggered. 319 */ 320 struct common_irq_params 321 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 322 323 /** 324 * @vblank_params: 325 * 326 * Vertical blanking IRQ parameters, passed to registered handlers when 327 * triggered. 328 */ 329 struct common_irq_params 330 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 331 332 /** 333 * @vline0_params: 334 * 335 * OTG vertical interrupt0 IRQ parameters, passed to registered 336 * handlers when triggered. 337 */ 338 struct common_irq_params 339 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 340 341 /** 342 * @vupdate_params: 343 * 344 * Vertical update IRQ parameters, passed to registered handlers when 345 * triggered. 346 */ 347 struct common_irq_params 348 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 349 350 /** 351 * @dmub_trace_params: 352 * 353 * DMUB trace event IRQ parameters, passed to registered handlers when 354 * triggered. 355 */ 356 struct common_irq_params 357 dmub_trace_params[1]; 358 359 struct common_irq_params 360 dmub_outbox_params[1]; 361 362 spinlock_t irq_handler_list_table_lock; 363 364 struct backlight_device *backlight_dev; 365 366 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 367 368 uint8_t num_of_edps; 369 370 struct amdgpu_dm_backlight_caps backlight_caps; 371 372 struct mod_freesync *freesync_module; 373 #ifdef CONFIG_DRM_AMD_DC_HDCP 374 struct hdcp_workqueue *hdcp_workqueue; 375 #endif 376 377 #if defined(CONFIG_DRM_AMD_DC_DCN) 378 /** 379 * @vblank_workqueue: 380 * 381 * amdgpu workqueue during vblank 382 */ 383 struct vblank_workqueue *vblank_workqueue; 384 #endif 385 386 struct drm_atomic_state *cached_state; 387 struct dc_state *cached_dc_state; 388 389 struct dm_compressor_info compressor; 390 391 const struct firmware *fw_dmcu; 392 uint32_t dmcu_fw_version; 393 /** 394 * @soc_bounding_box: 395 * 396 * gpu_info FW provided soc bounding box struct or 0 if not 397 * available in FW 398 */ 399 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 400 401 #if defined(CONFIG_DRM_AMD_DC_DCN) 402 /** 403 * @active_vblank_irq_count: 404 * 405 * number of currently active vblank irqs 406 */ 407 uint32_t active_vblank_irq_count; 408 #endif 409 410 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 411 /** 412 * @crc_rd_wrk: 413 * 414 * Work to be executed in a separate thread to communicate with PSP. 415 */ 416 struct crc_rd_work *crc_rd_wrk; 417 #endif 418 419 /** 420 * @mst_encoders: 421 * 422 * fake encoders used for DP MST. 423 */ 424 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 425 bool force_timing_sync; 426 bool disable_hpd_irq; 427 bool dmcub_trace_event_en; 428 /** 429 * @da_list: 430 * 431 * DAL fb memory allocation list, for communication with SMU. 432 */ 433 struct list_head da_list; 434 struct completion dmub_aux_transfer_done; 435 }; 436 437 enum dsc_clock_force_state { 438 DSC_CLK_FORCE_DEFAULT = 0, 439 DSC_CLK_FORCE_ENABLE, 440 DSC_CLK_FORCE_DISABLE, 441 }; 442 443 struct dsc_preferred_settings { 444 enum dsc_clock_force_state dsc_force_enable; 445 uint32_t dsc_num_slices_v; 446 uint32_t dsc_num_slices_h; 447 uint32_t dsc_bits_per_pixel; 448 }; 449 450 struct amdgpu_dm_connector { 451 452 struct drm_connector base; 453 uint32_t connector_id; 454 455 /* we need to mind the EDID between detect 456 and get modes due to analog/digital/tvencoder */ 457 struct edid *edid; 458 459 /* shared with amdgpu */ 460 struct amdgpu_hpd hpd; 461 462 /* number of modes generated from EDID at 'dc_sink' */ 463 int num_modes; 464 465 /* The 'old' sink - before an HPD. 466 * The 'current' sink is in dc_link->sink. */ 467 struct dc_sink *dc_sink; 468 struct dc_link *dc_link; 469 struct dc_sink *dc_em_sink; 470 471 /* DM only */ 472 struct drm_dp_mst_topology_mgr mst_mgr; 473 struct amdgpu_dm_dp_aux dm_dp_aux; 474 struct drm_dp_mst_port *port; 475 struct amdgpu_dm_connector *mst_port; 476 struct drm_dp_aux *dsc_aux; 477 478 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 479 struct amdgpu_i2c_adapter *i2c; 480 481 /* Monitor range limits */ 482 int min_vfreq ; 483 int max_vfreq ; 484 int pixel_clock_mhz; 485 486 /* Audio instance - protected by audio_lock. */ 487 int audio_inst; 488 489 struct mutex hpd_lock; 490 491 bool fake_enable; 492 #ifdef CONFIG_DEBUG_FS 493 uint32_t debugfs_dpcd_address; 494 uint32_t debugfs_dpcd_size; 495 #endif 496 bool force_yuv420_output; 497 struct dsc_preferred_settings dsc_settings; 498 /* Cached display modes */ 499 struct drm_display_mode freesync_vid_base; 500 }; 501 502 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 503 504 extern const struct amdgpu_ip_block_version dm_ip_block; 505 506 struct dm_plane_state { 507 struct drm_plane_state base; 508 struct dc_plane_state *dc_state; 509 }; 510 511 struct dm_crtc_state { 512 struct drm_crtc_state base; 513 struct dc_stream_state *stream; 514 515 bool cm_has_degamma; 516 bool cm_is_degamma_srgb; 517 518 int update_type; 519 int active_planes; 520 521 int crc_skip_count; 522 523 bool freesync_timing_changed; 524 bool freesync_vrr_info_changed; 525 526 bool dsc_force_changed; 527 bool vrr_supported; 528 struct mod_freesync_config freesync_config; 529 struct dc_info_packet vrr_infopacket; 530 531 int abm_level; 532 }; 533 534 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 535 536 struct dm_atomic_state { 537 struct drm_private_state base; 538 539 struct dc_state *context; 540 }; 541 542 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 543 544 struct dm_connector_state { 545 struct drm_connector_state base; 546 547 enum amdgpu_rmx_type scaling; 548 uint8_t underscan_vborder; 549 uint8_t underscan_hborder; 550 bool underscan_enable; 551 bool freesync_capable; 552 #ifdef CONFIG_DRM_AMD_DC_HDCP 553 bool update_hdcp; 554 #endif 555 uint8_t abm_level; 556 int vcpi_slots; 557 uint64_t pbn; 558 }; 559 560 struct amdgpu_hdmi_vsdb_info { 561 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 562 bool freesync_supported; /* FreeSync Supported */ 563 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 564 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 565 }; 566 567 568 #define to_dm_connector_state(x)\ 569 container_of((x), struct dm_connector_state, base) 570 571 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 572 struct drm_connector_state * 573 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 574 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 575 struct drm_connector_state *state, 576 struct drm_property *property, 577 uint64_t val); 578 579 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 580 const struct drm_connector_state *state, 581 struct drm_property *property, 582 uint64_t *val); 583 584 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 585 586 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 587 struct amdgpu_dm_connector *aconnector, 588 int connector_type, 589 struct dc_link *link, 590 int link_index); 591 592 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 593 struct drm_display_mode *mode); 594 595 void dm_restore_drm_connector_state(struct drm_device *dev, 596 struct drm_connector *connector); 597 598 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 599 struct edid *edid); 600 601 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 602 603 #define MAX_COLOR_LUT_ENTRIES 4096 604 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 605 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 606 607 void amdgpu_dm_init_color_mod(void); 608 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 609 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 610 struct dc_plane_state *dc_plane_state); 611 612 void amdgpu_dm_update_connector_after_detect( 613 struct amdgpu_dm_connector *aconnector); 614 615 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 616 617 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex, 618 struct aux_payload *payload, enum aux_return_code_type *operation_result); 619 #endif /* __AMDGPU_DM_H__ */ 620