1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 #define AMDGPU_DM_MAX_NUM_EDP 2 50 /* 51 #include "include/amdgpu_dal_power_if.h" 52 #include "amdgpu_dm_irq.h" 53 */ 54 55 #include "irq_types.h" 56 #include "signal_types.h" 57 #include "amdgpu_dm_crc.h" 58 59 /* Forward declarations */ 60 struct amdgpu_device; 61 struct drm_device; 62 struct dc; 63 struct amdgpu_bo; 64 struct dmub_srv; 65 struct dc_plane_state; 66 67 struct common_irq_params { 68 struct amdgpu_device *adev; 69 enum dc_irq_source irq_src; 70 atomic64_t previous_timestamp; 71 }; 72 73 /** 74 * struct dm_compressor_info - Buffer info used by frame buffer compression 75 * @cpu_addr: MMIO cpu addr 76 * @bo_ptr: Pointer to the buffer object 77 * @gpu_addr: MMIO gpu addr 78 */ 79 struct dm_compressor_info { 80 void *cpu_addr; 81 struct amdgpu_bo *bo_ptr; 82 uint64_t gpu_addr; 83 }; 84 85 /** 86 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 87 * @mall_work: work for mall stutter 88 * @dm: amdgpu display manager device 89 * @otg_inst: otg instance of which vblank is being set 90 * @enable: true if enable vblank 91 */ 92 struct vblank_workqueue { 93 struct work_struct mall_work; 94 struct amdgpu_display_manager *dm; 95 int otg_inst; 96 bool enable; 97 }; 98 99 /** 100 * struct amdgpu_dm_backlight_caps - Information about backlight 101 * 102 * Describe the backlight support for ACPI or eDP AUX. 103 */ 104 struct amdgpu_dm_backlight_caps { 105 /** 106 * @ext_caps: Keep the data struct with all the information about the 107 * display support for HDR. 108 */ 109 union dpcd_sink_ext_caps *ext_caps; 110 /** 111 * @aux_min_input_signal: Min brightness value supported by the display 112 */ 113 u32 aux_min_input_signal; 114 /** 115 * @aux_max_input_signal: Max brightness value supported by the display 116 * in nits. 117 */ 118 u32 aux_max_input_signal; 119 /** 120 * @min_input_signal: minimum possible input in range 0-255. 121 */ 122 int min_input_signal; 123 /** 124 * @max_input_signal: maximum possible input in range 0-255. 125 */ 126 int max_input_signal; 127 /** 128 * @caps_valid: true if these values are from the ACPI interface. 129 */ 130 bool caps_valid; 131 /** 132 * @aux_support: Describes if the display supports AUX backlight. 133 */ 134 bool aux_support; 135 }; 136 137 /** 138 * struct dal_allocation - Tracks mapped FB memory for SMU communication 139 */ 140 struct dal_allocation { 141 struct list_head list; 142 struct amdgpu_bo *bo; 143 void *cpu_ptr; 144 u64 gpu_addr; 145 }; 146 147 /** 148 * struct amdgpu_display_manager - Central amdgpu display manager device 149 * 150 * @dc: Display Core control structure 151 * @adev: AMDGPU base driver structure 152 * @ddev: DRM base driver structure 153 * @display_indexes_num: Max number of display streams supported 154 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 155 * @backlight_dev: Backlight control device 156 * @backlight_link: Link on which to control backlight 157 * @backlight_caps: Capabilities of the backlight device 158 * @freesync_module: Module handling freesync calculations 159 * @hdcp_workqueue: AMDGPU content protection queue 160 * @fw_dmcu: Reference to DMCU firmware 161 * @dmcu_fw_version: Version of the DMCU firmware 162 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 163 * @cached_state: Caches device atomic state for suspend/resume 164 * @cached_dc_state: Cached state of content streams 165 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 166 * @force_timing_sync: set via debugfs. When set, indicates that all connected 167 * displays will be forced to synchronize. 168 * @dmcub_trace_event_en: enable dmcub trace events 169 */ 170 struct amdgpu_display_manager { 171 172 struct dc *dc; 173 174 /** 175 * @dmub_srv: 176 * 177 * DMUB service, used for controlling the DMUB on hardware 178 * that supports it. The pointer to the dmub_srv will be 179 * NULL on hardware that does not support it. 180 */ 181 struct dmub_srv *dmub_srv; 182 183 /** 184 * @dmub_fb_info: 185 * 186 * Framebuffer regions for the DMUB. 187 */ 188 struct dmub_srv_fb_info *dmub_fb_info; 189 190 /** 191 * @dmub_fw: 192 * 193 * DMUB firmware, required on hardware that has DMUB support. 194 */ 195 const struct firmware *dmub_fw; 196 197 /** 198 * @dmub_bo: 199 * 200 * Buffer object for the DMUB. 201 */ 202 struct amdgpu_bo *dmub_bo; 203 204 /** 205 * @dmub_bo_gpu_addr: 206 * 207 * GPU virtual address for the DMUB buffer object. 208 */ 209 u64 dmub_bo_gpu_addr; 210 211 /** 212 * @dmub_bo_cpu_addr: 213 * 214 * CPU address for the DMUB buffer object. 215 */ 216 void *dmub_bo_cpu_addr; 217 218 /** 219 * @dmcub_fw_version: 220 * 221 * DMCUB firmware version. 222 */ 223 uint32_t dmcub_fw_version; 224 225 /** 226 * @cgs_device: 227 * 228 * The Common Graphics Services device. It provides an interface for 229 * accessing registers. 230 */ 231 struct cgs_device *cgs_device; 232 233 struct amdgpu_device *adev; 234 struct drm_device *ddev; 235 u16 display_indexes_num; 236 237 /** 238 * @atomic_obj: 239 * 240 * In combination with &dm_atomic_state it helps manage 241 * global atomic state that doesn't map cleanly into existing 242 * drm resources, like &dc_context. 243 */ 244 struct drm_private_obj atomic_obj; 245 246 /** 247 * @dc_lock: 248 * 249 * Guards access to DC functions that can issue register write 250 * sequences. 251 */ 252 struct mutex dc_lock; 253 254 /** 255 * @audio_lock: 256 * 257 * Guards access to audio instance changes. 258 */ 259 struct mutex audio_lock; 260 261 #if defined(CONFIG_DRM_AMD_DC_DCN) 262 /** 263 * @vblank_lock: 264 * 265 * Guards access to deferred vblank work state. 266 */ 267 spinlock_t vblank_lock; 268 #endif 269 270 /** 271 * @audio_component: 272 * 273 * Used to notify ELD changes to sound driver. 274 */ 275 struct drm_audio_component *audio_component; 276 277 /** 278 * @audio_registered: 279 * 280 * True if the audio component has been registered 281 * successfully, false otherwise. 282 */ 283 bool audio_registered; 284 285 /** 286 * @irq_handler_list_low_tab: 287 * 288 * Low priority IRQ handler table. 289 * 290 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 291 * source. Low priority IRQ handlers are deferred to a workqueue to be 292 * processed. Hence, they can sleep. 293 * 294 * Note that handlers are called in the same order as they were 295 * registered (FIFO). 296 */ 297 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 298 299 /** 300 * @irq_handler_list_high_tab: 301 * 302 * High priority IRQ handler table. 303 * 304 * It is a n*m table, same as &irq_handler_list_low_tab. However, 305 * handlers in this table are not deferred and are called immediately. 306 */ 307 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 308 309 /** 310 * @pflip_params: 311 * 312 * Page flip IRQ parameters, passed to registered handlers when 313 * triggered. 314 */ 315 struct common_irq_params 316 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 317 318 /** 319 * @vblank_params: 320 * 321 * Vertical blanking IRQ parameters, passed to registered handlers when 322 * triggered. 323 */ 324 struct common_irq_params 325 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 326 327 /** 328 * @vline0_params: 329 * 330 * OTG vertical interrupt0 IRQ parameters, passed to registered 331 * handlers when triggered. 332 */ 333 struct common_irq_params 334 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 335 336 /** 337 * @vupdate_params: 338 * 339 * Vertical update IRQ parameters, passed to registered handlers when 340 * triggered. 341 */ 342 struct common_irq_params 343 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 344 345 /** 346 * @dmub_trace_params: 347 * 348 * DMUB trace event IRQ parameters, passed to registered handlers when 349 * triggered. 350 */ 351 struct common_irq_params 352 dmub_trace_params[1]; 353 354 spinlock_t irq_handler_list_table_lock; 355 356 struct backlight_device *backlight_dev; 357 358 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 359 360 uint8_t num_of_edps; 361 362 struct amdgpu_dm_backlight_caps backlight_caps; 363 364 struct mod_freesync *freesync_module; 365 #ifdef CONFIG_DRM_AMD_DC_HDCP 366 struct hdcp_workqueue *hdcp_workqueue; 367 #endif 368 369 #if defined(CONFIG_DRM_AMD_DC_DCN) 370 /** 371 * @vblank_workqueue: 372 * 373 * amdgpu workqueue during vblank 374 */ 375 struct vblank_workqueue *vblank_workqueue; 376 #endif 377 378 struct drm_atomic_state *cached_state; 379 struct dc_state *cached_dc_state; 380 381 struct dm_compressor_info compressor; 382 383 const struct firmware *fw_dmcu; 384 uint32_t dmcu_fw_version; 385 /** 386 * @soc_bounding_box: 387 * 388 * gpu_info FW provided soc bounding box struct or 0 if not 389 * available in FW 390 */ 391 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 392 393 #if defined(CONFIG_DRM_AMD_DC_DCN) 394 /** 395 * @active_vblank_irq_count: 396 * 397 * number of currently active vblank irqs 398 */ 399 uint32_t active_vblank_irq_count; 400 #endif 401 402 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 403 /** 404 * @crc_rd_wrk: 405 * 406 * Work to be executed in a separate thread to communicate with PSP. 407 */ 408 struct crc_rd_work *crc_rd_wrk; 409 #endif 410 411 /** 412 * @mst_encoders: 413 * 414 * fake encoders used for DP MST. 415 */ 416 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 417 bool force_timing_sync; 418 bool disable_hpd_irq; 419 bool dmcub_trace_event_en; 420 /** 421 * @da_list: 422 * 423 * DAL fb memory allocation list, for communication with SMU. 424 */ 425 struct list_head da_list; 426 }; 427 428 enum dsc_clock_force_state { 429 DSC_CLK_FORCE_DEFAULT = 0, 430 DSC_CLK_FORCE_ENABLE, 431 DSC_CLK_FORCE_DISABLE, 432 }; 433 434 struct dsc_preferred_settings { 435 enum dsc_clock_force_state dsc_force_enable; 436 uint32_t dsc_num_slices_v; 437 uint32_t dsc_num_slices_h; 438 uint32_t dsc_bits_per_pixel; 439 }; 440 441 struct amdgpu_dm_connector { 442 443 struct drm_connector base; 444 uint32_t connector_id; 445 446 /* we need to mind the EDID between detect 447 and get modes due to analog/digital/tvencoder */ 448 struct edid *edid; 449 450 /* shared with amdgpu */ 451 struct amdgpu_hpd hpd; 452 453 /* number of modes generated from EDID at 'dc_sink' */ 454 int num_modes; 455 456 /* The 'old' sink - before an HPD. 457 * The 'current' sink is in dc_link->sink. */ 458 struct dc_sink *dc_sink; 459 struct dc_link *dc_link; 460 struct dc_sink *dc_em_sink; 461 462 /* DM only */ 463 struct drm_dp_mst_topology_mgr mst_mgr; 464 struct amdgpu_dm_dp_aux dm_dp_aux; 465 struct drm_dp_mst_port *port; 466 struct amdgpu_dm_connector *mst_port; 467 struct drm_dp_aux *dsc_aux; 468 469 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 470 struct amdgpu_i2c_adapter *i2c; 471 472 /* Monitor range limits */ 473 int min_vfreq ; 474 int max_vfreq ; 475 int pixel_clock_mhz; 476 477 /* Audio instance - protected by audio_lock. */ 478 int audio_inst; 479 480 struct mutex hpd_lock; 481 482 bool fake_enable; 483 #ifdef CONFIG_DEBUG_FS 484 uint32_t debugfs_dpcd_address; 485 uint32_t debugfs_dpcd_size; 486 #endif 487 bool force_yuv420_output; 488 struct dsc_preferred_settings dsc_settings; 489 /* Cached display modes */ 490 struct drm_display_mode freesync_vid_base; 491 }; 492 493 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 494 495 extern const struct amdgpu_ip_block_version dm_ip_block; 496 497 struct dm_plane_state { 498 struct drm_plane_state base; 499 struct dc_plane_state *dc_state; 500 }; 501 502 struct dm_crtc_state { 503 struct drm_crtc_state base; 504 struct dc_stream_state *stream; 505 506 bool cm_has_degamma; 507 bool cm_is_degamma_srgb; 508 509 int update_type; 510 int active_planes; 511 512 int crc_skip_count; 513 514 bool freesync_timing_changed; 515 bool freesync_vrr_info_changed; 516 517 bool dsc_force_changed; 518 bool vrr_supported; 519 struct mod_freesync_config freesync_config; 520 struct dc_info_packet vrr_infopacket; 521 522 int abm_level; 523 }; 524 525 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 526 527 struct dm_atomic_state { 528 struct drm_private_state base; 529 530 struct dc_state *context; 531 }; 532 533 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 534 535 struct dm_connector_state { 536 struct drm_connector_state base; 537 538 enum amdgpu_rmx_type scaling; 539 uint8_t underscan_vborder; 540 uint8_t underscan_hborder; 541 bool underscan_enable; 542 bool freesync_capable; 543 #ifdef CONFIG_DRM_AMD_DC_HDCP 544 bool update_hdcp; 545 #endif 546 uint8_t abm_level; 547 int vcpi_slots; 548 uint64_t pbn; 549 }; 550 551 struct amdgpu_hdmi_vsdb_info { 552 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 553 bool freesync_supported; /* FreeSync Supported */ 554 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 555 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 556 }; 557 558 559 #define to_dm_connector_state(x)\ 560 container_of((x), struct dm_connector_state, base) 561 562 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 563 struct drm_connector_state * 564 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 565 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 566 struct drm_connector_state *state, 567 struct drm_property *property, 568 uint64_t val); 569 570 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 571 const struct drm_connector_state *state, 572 struct drm_property *property, 573 uint64_t *val); 574 575 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 576 577 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 578 struct amdgpu_dm_connector *aconnector, 579 int connector_type, 580 struct dc_link *link, 581 int link_index); 582 583 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 584 struct drm_display_mode *mode); 585 586 void dm_restore_drm_connector_state(struct drm_device *dev, 587 struct drm_connector *connector); 588 589 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 590 struct edid *edid); 591 592 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 593 594 #define MAX_COLOR_LUT_ENTRIES 4096 595 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 596 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 597 598 void amdgpu_dm_init_color_mod(void); 599 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 600 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 601 struct dc_plane_state *dc_plane_state); 602 603 void amdgpu_dm_update_connector_after_detect( 604 struct amdgpu_dm_connector *aconnector); 605 606 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 607 608 #endif /* __AMDGPU_DM_H__ */ 609