1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct dc; 62 struct amdgpu_bo; 63 struct dmub_srv; 64 struct dc_plane_state; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 }; 70 71 /** 72 * struct dm_compressor_info - Buffer info used by frame buffer compression 73 * @cpu_addr: MMIO cpu addr 74 * @bo_ptr: Pointer to the buffer object 75 * @gpu_addr: MMIO gpu addr 76 */ 77 struct dm_compressor_info { 78 void *cpu_addr; 79 struct amdgpu_bo *bo_ptr; 80 uint64_t gpu_addr; 81 }; 82 83 /** 84 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 85 * @mall_work: work for mall stutter 86 * @dm: amdgpu display manager device 87 * @otg_inst: otg instance of which vblank is being set 88 * @enable: true if enable vblank 89 */ 90 struct vblank_workqueue { 91 struct work_struct mall_work; 92 struct amdgpu_display_manager *dm; 93 int otg_inst; 94 bool enable; 95 }; 96 97 /** 98 * struct amdgpu_dm_backlight_caps - Information about backlight 99 * 100 * Describe the backlight support for ACPI or eDP AUX. 101 */ 102 struct amdgpu_dm_backlight_caps { 103 /** 104 * @ext_caps: Keep the data struct with all the information about the 105 * display support for HDR. 106 */ 107 union dpcd_sink_ext_caps *ext_caps; 108 /** 109 * @aux_min_input_signal: Min brightness value supported by the display 110 */ 111 u32 aux_min_input_signal; 112 /** 113 * @aux_max_input_signal: Max brightness value supported by the display 114 * in nits. 115 */ 116 u32 aux_max_input_signal; 117 /** 118 * @min_input_signal: minimum possible input in range 0-255. 119 */ 120 int min_input_signal; 121 /** 122 * @max_input_signal: maximum possible input in range 0-255. 123 */ 124 int max_input_signal; 125 /** 126 * @caps_valid: true if these values are from the ACPI interface. 127 */ 128 bool caps_valid; 129 /** 130 * @aux_support: Describes if the display supports AUX backlight. 131 */ 132 bool aux_support; 133 }; 134 135 /** 136 * struct amdgpu_display_manager - Central amdgpu display manager device 137 * 138 * @dc: Display Core control structure 139 * @adev: AMDGPU base driver structure 140 * @ddev: DRM base driver structure 141 * @display_indexes_num: Max number of display streams supported 142 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 143 * @backlight_dev: Backlight control device 144 * @backlight_link: Link on which to control backlight 145 * @backlight_caps: Capabilities of the backlight device 146 * @freesync_module: Module handling freesync calculations 147 * @hdcp_workqueue: AMDGPU content protection queue 148 * @fw_dmcu: Reference to DMCU firmware 149 * @dmcu_fw_version: Version of the DMCU firmware 150 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 151 * @cached_state: Caches device atomic state for suspend/resume 152 * @cached_dc_state: Cached state of content streams 153 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 154 * @force_timing_sync: set via debugfs. When set, indicates that all connected 155 * displays will be forced to synchronize. 156 */ 157 struct amdgpu_display_manager { 158 159 struct dc *dc; 160 161 /** 162 * @dmub_srv: 163 * 164 * DMUB service, used for controlling the DMUB on hardware 165 * that supports it. The pointer to the dmub_srv will be 166 * NULL on hardware that does not support it. 167 */ 168 struct dmub_srv *dmub_srv; 169 170 /** 171 * @dmub_fb_info: 172 * 173 * Framebuffer regions for the DMUB. 174 */ 175 struct dmub_srv_fb_info *dmub_fb_info; 176 177 /** 178 * @dmub_fw: 179 * 180 * DMUB firmware, required on hardware that has DMUB support. 181 */ 182 const struct firmware *dmub_fw; 183 184 /** 185 * @dmub_bo: 186 * 187 * Buffer object for the DMUB. 188 */ 189 struct amdgpu_bo *dmub_bo; 190 191 /** 192 * @dmub_bo_gpu_addr: 193 * 194 * GPU virtual address for the DMUB buffer object. 195 */ 196 u64 dmub_bo_gpu_addr; 197 198 /** 199 * @dmub_bo_cpu_addr: 200 * 201 * CPU address for the DMUB buffer object. 202 */ 203 void *dmub_bo_cpu_addr; 204 205 /** 206 * @dmcub_fw_version: 207 * 208 * DMCUB firmware version. 209 */ 210 uint32_t dmcub_fw_version; 211 212 /** 213 * @cgs_device: 214 * 215 * The Common Graphics Services device. It provides an interface for 216 * accessing registers. 217 */ 218 struct cgs_device *cgs_device; 219 220 struct amdgpu_device *adev; 221 struct drm_device *ddev; 222 u16 display_indexes_num; 223 224 /** 225 * @atomic_obj: 226 * 227 * In combination with &dm_atomic_state it helps manage 228 * global atomic state that doesn't map cleanly into existing 229 * drm resources, like &dc_context. 230 */ 231 struct drm_private_obj atomic_obj; 232 233 /** 234 * @dc_lock: 235 * 236 * Guards access to DC functions that can issue register write 237 * sequences. 238 */ 239 struct mutex dc_lock; 240 241 /** 242 * @audio_lock: 243 * 244 * Guards access to audio instance changes. 245 */ 246 struct mutex audio_lock; 247 248 /** 249 * @vblank_work_lock: 250 * 251 * Guards access to deferred vblank work state. 252 */ 253 #if defined(CONFIG_DRM_AMD_DC_DCN) 254 spinlock_t vblank_lock; 255 #endif 256 257 /** 258 * @audio_component: 259 * 260 * Used to notify ELD changes to sound driver. 261 */ 262 struct drm_audio_component *audio_component; 263 264 /** 265 * @audio_registered: 266 * 267 * True if the audio component has been registered 268 * successfully, false otherwise. 269 */ 270 bool audio_registered; 271 272 /** 273 * @irq_handler_list_low_tab: 274 * 275 * Low priority IRQ handler table. 276 * 277 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 278 * source. Low priority IRQ handlers are deferred to a workqueue to be 279 * processed. Hence, they can sleep. 280 * 281 * Note that handlers are called in the same order as they were 282 * registered (FIFO). 283 */ 284 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 285 286 /** 287 * @irq_handler_list_high_tab: 288 * 289 * High priority IRQ handler table. 290 * 291 * It is a n*m table, same as &irq_handler_list_low_tab. However, 292 * handlers in this table are not deferred and are called immediately. 293 */ 294 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 295 296 /** 297 * @pflip_params: 298 * 299 * Page flip IRQ parameters, passed to registered handlers when 300 * triggered. 301 */ 302 struct common_irq_params 303 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 304 305 /** 306 * @vblank_params: 307 * 308 * Vertical blanking IRQ parameters, passed to registered handlers when 309 * triggered. 310 */ 311 struct common_irq_params 312 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 313 314 /** 315 * @vline0_params: 316 * 317 * OTG vertical interrupt0 IRQ parameters, passed to registered 318 * handlers when triggered. 319 */ 320 struct common_irq_params 321 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 322 323 /** 324 * @vupdate_params: 325 * 326 * Vertical update IRQ parameters, passed to registered handlers when 327 * triggered. 328 */ 329 struct common_irq_params 330 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 331 332 spinlock_t irq_handler_list_table_lock; 333 334 struct backlight_device *backlight_dev; 335 336 const struct dc_link *backlight_link; 337 struct amdgpu_dm_backlight_caps backlight_caps; 338 339 struct mod_freesync *freesync_module; 340 #ifdef CONFIG_DRM_AMD_DC_HDCP 341 struct hdcp_workqueue *hdcp_workqueue; 342 #endif 343 344 #if defined(CONFIG_DRM_AMD_DC_DCN) 345 struct vblank_workqueue *vblank_workqueue; 346 #endif 347 348 struct drm_atomic_state *cached_state; 349 struct dc_state *cached_dc_state; 350 351 struct dm_compressor_info compressor; 352 353 const struct firmware *fw_dmcu; 354 uint32_t dmcu_fw_version; 355 /** 356 * @soc_bounding_box: 357 * 358 * gpu_info FW provided soc bounding box struct or 0 if not 359 * available in FW 360 */ 361 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 362 363 /** 364 * @active_vblank_irq_count: 365 * 366 * number of currently active vblank irqs 367 */ 368 uint32_t active_vblank_irq_count; 369 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 370 struct crc_rd_work *crc_rd_wrk; 371 #endif 372 373 /** 374 * @mst_encoders: 375 * 376 * fake encoders used for DP MST. 377 */ 378 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 379 bool force_timing_sync; 380 }; 381 382 enum dsc_clock_force_state { 383 DSC_CLK_FORCE_DEFAULT = 0, 384 DSC_CLK_FORCE_ENABLE, 385 DSC_CLK_FORCE_DISABLE, 386 }; 387 388 struct dsc_preferred_settings { 389 enum dsc_clock_force_state dsc_force_enable; 390 uint32_t dsc_num_slices_v; 391 uint32_t dsc_num_slices_h; 392 uint32_t dsc_bits_per_pixel; 393 }; 394 395 struct amdgpu_dm_connector { 396 397 struct drm_connector base; 398 uint32_t connector_id; 399 400 /* we need to mind the EDID between detect 401 and get modes due to analog/digital/tvencoder */ 402 struct edid *edid; 403 404 /* shared with amdgpu */ 405 struct amdgpu_hpd hpd; 406 407 /* number of modes generated from EDID at 'dc_sink' */ 408 int num_modes; 409 410 /* The 'old' sink - before an HPD. 411 * The 'current' sink is in dc_link->sink. */ 412 struct dc_sink *dc_sink; 413 struct dc_link *dc_link; 414 struct dc_sink *dc_em_sink; 415 416 /* DM only */ 417 struct drm_dp_mst_topology_mgr mst_mgr; 418 struct amdgpu_dm_dp_aux dm_dp_aux; 419 struct drm_dp_mst_port *port; 420 struct amdgpu_dm_connector *mst_port; 421 struct drm_dp_aux *dsc_aux; 422 423 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 424 struct amdgpu_i2c_adapter *i2c; 425 426 /* Monitor range limits */ 427 int min_vfreq ; 428 int max_vfreq ; 429 int pixel_clock_mhz; 430 431 /* Audio instance - protected by audio_lock. */ 432 int audio_inst; 433 434 struct mutex hpd_lock; 435 436 bool fake_enable; 437 #ifdef CONFIG_DEBUG_FS 438 uint32_t debugfs_dpcd_address; 439 uint32_t debugfs_dpcd_size; 440 #endif 441 bool force_yuv420_output; 442 struct dsc_preferred_settings dsc_settings; 443 /* Cached display modes */ 444 struct drm_display_mode freesync_vid_base; 445 }; 446 447 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 448 449 extern const struct amdgpu_ip_block_version dm_ip_block; 450 451 struct dm_plane_state { 452 struct drm_plane_state base; 453 struct dc_plane_state *dc_state; 454 }; 455 456 struct dm_crtc_state { 457 struct drm_crtc_state base; 458 struct dc_stream_state *stream; 459 460 bool cm_has_degamma; 461 bool cm_is_degamma_srgb; 462 463 int update_type; 464 int active_planes; 465 466 int crc_skip_count; 467 468 bool freesync_timing_changed; 469 bool freesync_vrr_info_changed; 470 471 bool dsc_force_changed; 472 bool vrr_supported; 473 struct mod_freesync_config freesync_config; 474 struct dc_info_packet vrr_infopacket; 475 476 int abm_level; 477 }; 478 479 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 480 481 struct dm_atomic_state { 482 struct drm_private_state base; 483 484 struct dc_state *context; 485 }; 486 487 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 488 489 struct dm_connector_state { 490 struct drm_connector_state base; 491 492 enum amdgpu_rmx_type scaling; 493 uint8_t underscan_vborder; 494 uint8_t underscan_hborder; 495 bool underscan_enable; 496 bool freesync_capable; 497 #ifdef CONFIG_DRM_AMD_DC_HDCP 498 bool update_hdcp; 499 #endif 500 uint8_t abm_level; 501 int vcpi_slots; 502 uint64_t pbn; 503 }; 504 505 struct amdgpu_hdmi_vsdb_info { 506 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 507 bool freesync_supported; /* FreeSync Supported */ 508 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 509 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 510 }; 511 512 513 #define to_dm_connector_state(x)\ 514 container_of((x), struct dm_connector_state, base) 515 516 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 517 struct drm_connector_state * 518 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 519 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 520 struct drm_connector_state *state, 521 struct drm_property *property, 522 uint64_t val); 523 524 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 525 const struct drm_connector_state *state, 526 struct drm_property *property, 527 uint64_t *val); 528 529 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 530 531 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 532 struct amdgpu_dm_connector *aconnector, 533 int connector_type, 534 struct dc_link *link, 535 int link_index); 536 537 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 538 struct drm_display_mode *mode); 539 540 void dm_restore_drm_connector_state(struct drm_device *dev, 541 struct drm_connector *connector); 542 543 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 544 struct edid *edid); 545 546 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 547 548 #define MAX_COLOR_LUT_ENTRIES 4096 549 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 550 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 551 552 void amdgpu_dm_init_color_mod(void); 553 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 554 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 555 struct dc_plane_state *dc_plane_state); 556 557 void amdgpu_dm_update_connector_after_detect( 558 struct amdgpu_dm_connector *aconnector); 559 560 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 561 562 #endif /* __AMDGPU_DM_H__ */ 563