1 /*
2  * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
28 
29 #include <drm/drm_atomic.h>
30 #include <drm/drm_connector.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_dp_mst_helper.h>
33 #include <drm/drm_plane.h>
34 
35 /*
36  * This file contains the definition for amdgpu_display_manager
37  * and its API for amdgpu driver's use.
38  * This component provides all the display related functionality
39  * and this is the only component that calls DAL API.
40  * The API contained here intended for amdgpu driver use.
41  * The API that is called directly from KMS framework is located
42  * in amdgpu_dm_kms.h file
43  */
44 
45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
46 
47 #define AMDGPU_DM_MAX_CRTC 6
48 
49 #define AMDGPU_DM_MAX_NUM_EDP 2
50 /*
51 #include "include/amdgpu_dal_power_if.h"
52 #include "amdgpu_dm_irq.h"
53 */
54 
55 #include "irq_types.h"
56 #include "signal_types.h"
57 #include "amdgpu_dm_crc.h"
58 struct aux_payload;
59 enum aux_return_code_type;
60 
61 /* Forward declarations */
62 struct amdgpu_device;
63 struct drm_device;
64 struct dc;
65 struct amdgpu_bo;
66 struct dmub_srv;
67 struct dc_plane_state;
68 struct dmub_notification;
69 
70 struct common_irq_params {
71 	struct amdgpu_device *adev;
72 	enum dc_irq_source irq_src;
73 	atomic64_t previous_timestamp;
74 };
75 
76 /**
77  * struct dm_compressor_info - Buffer info used by frame buffer compression
78  * @cpu_addr: MMIO cpu addr
79  * @bo_ptr: Pointer to the buffer object
80  * @gpu_addr: MMIO gpu addr
81  */
82 struct dm_compressor_info {
83 	void *cpu_addr;
84 	struct amdgpu_bo *bo_ptr;
85 	uint64_t gpu_addr;
86 };
87 
88 /**
89  * struct vblank_workqueue - Works to be executed in a separate thread during vblank
90  * @mall_work: work for mall stutter
91  * @dm: amdgpu display manager device
92  * @otg_inst: otg instance of which vblank is being set
93  * @enable: true if enable vblank
94  */
95 struct vblank_workqueue {
96 	struct work_struct mall_work;
97 	struct amdgpu_display_manager *dm;
98 	int otg_inst;
99 	bool enable;
100 };
101 
102 /**
103  * struct amdgpu_dm_backlight_caps - Information about backlight
104  *
105  * Describe the backlight support for ACPI or eDP AUX.
106  */
107 struct amdgpu_dm_backlight_caps {
108 	/**
109 	 * @ext_caps: Keep the data struct with all the information about the
110 	 * display support for HDR.
111 	 */
112 	union dpcd_sink_ext_caps *ext_caps;
113 	/**
114 	 * @aux_min_input_signal: Min brightness value supported by the display
115 	 */
116 	u32 aux_min_input_signal;
117 	/**
118 	 * @aux_max_input_signal: Max brightness value supported by the display
119 	 * in nits.
120 	 */
121 	u32 aux_max_input_signal;
122 	/**
123 	 * @min_input_signal: minimum possible input in range 0-255.
124 	 */
125 	int min_input_signal;
126 	/**
127 	 * @max_input_signal: maximum possible input in range 0-255.
128 	 */
129 	int max_input_signal;
130 	/**
131 	 * @caps_valid: true if these values are from the ACPI interface.
132 	 */
133 	bool caps_valid;
134 	/**
135 	 * @aux_support: Describes if the display supports AUX backlight.
136 	 */
137 	bool aux_support;
138 };
139 
140 /**
141  * struct dal_allocation - Tracks mapped FB memory for SMU communication
142  * @list: list of dal allocations
143  * @bo: GPU buffer object
144  * @cpu_ptr: CPU virtual address of the GPU buffer object
145  * @gpu_addr: GPU virtual address of the GPU buffer object
146  */
147 struct dal_allocation {
148 	struct list_head list;
149 	struct amdgpu_bo *bo;
150 	void *cpu_ptr;
151 	u64 gpu_addr;
152 };
153 
154 /**
155  * struct amdgpu_display_manager - Central amdgpu display manager device
156  *
157  * @dc: Display Core control structure
158  * @adev: AMDGPU base driver structure
159  * @ddev: DRM base driver structure
160  * @display_indexes_num: Max number of display streams supported
161  * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
162  * @backlight_dev: Backlight control device
163  * @backlight_link: Link on which to control backlight
164  * @backlight_caps: Capabilities of the backlight device
165  * @freesync_module: Module handling freesync calculations
166  * @hdcp_workqueue: AMDGPU content protection queue
167  * @fw_dmcu: Reference to DMCU firmware
168  * @dmcu_fw_version: Version of the DMCU firmware
169  * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
170  * @cached_state: Caches device atomic state for suspend/resume
171  * @cached_dc_state: Cached state of content streams
172  * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
173  * @force_timing_sync: set via debugfs. When set, indicates that all connected
174  *		       displays will be forced to synchronize.
175  * @dmcub_trace_event_en: enable dmcub trace events
176  */
177 struct amdgpu_display_manager {
178 
179 	struct dc *dc;
180 
181 	/**
182 	 * @dmub_srv:
183 	 *
184 	 * DMUB service, used for controlling the DMUB on hardware
185 	 * that supports it. The pointer to the dmub_srv will be
186 	 * NULL on hardware that does not support it.
187 	 */
188 	struct dmub_srv *dmub_srv;
189 
190 	struct dmub_notification *dmub_notify;
191 
192 	/**
193 	 * @dmub_fb_info:
194 	 *
195 	 * Framebuffer regions for the DMUB.
196 	 */
197 	struct dmub_srv_fb_info *dmub_fb_info;
198 
199 	/**
200 	 * @dmub_fw:
201 	 *
202 	 * DMUB firmware, required on hardware that has DMUB support.
203 	 */
204 	const struct firmware *dmub_fw;
205 
206 	/**
207 	 * @dmub_bo:
208 	 *
209 	 * Buffer object for the DMUB.
210 	 */
211 	struct amdgpu_bo *dmub_bo;
212 
213 	/**
214 	 * @dmub_bo_gpu_addr:
215 	 *
216 	 * GPU virtual address for the DMUB buffer object.
217 	 */
218 	u64 dmub_bo_gpu_addr;
219 
220 	/**
221 	 * @dmub_bo_cpu_addr:
222 	 *
223 	 * CPU address for the DMUB buffer object.
224 	 */
225 	void *dmub_bo_cpu_addr;
226 
227 	/**
228 	 * @dmcub_fw_version:
229 	 *
230 	 * DMCUB firmware version.
231 	 */
232 	uint32_t dmcub_fw_version;
233 
234 	/**
235 	 * @cgs_device:
236 	 *
237 	 * The Common Graphics Services device. It provides an interface for
238 	 * accessing registers.
239 	 */
240 	struct cgs_device *cgs_device;
241 
242 	struct amdgpu_device *adev;
243 	struct drm_device *ddev;
244 	u16 display_indexes_num;
245 
246 	/**
247 	 * @atomic_obj:
248 	 *
249 	 * In combination with &dm_atomic_state it helps manage
250 	 * global atomic state that doesn't map cleanly into existing
251 	 * drm resources, like &dc_context.
252 	 */
253 	struct drm_private_obj atomic_obj;
254 
255 	/**
256 	 * @dc_lock:
257 	 *
258 	 * Guards access to DC functions that can issue register write
259 	 * sequences.
260 	 */
261 	struct mutex dc_lock;
262 
263 	/**
264 	 * @audio_lock:
265 	 *
266 	 * Guards access to audio instance changes.
267 	 */
268 	struct mutex audio_lock;
269 
270 #if defined(CONFIG_DRM_AMD_DC_DCN)
271 	/**
272 	 * @vblank_lock:
273 	 *
274 	 * Guards access to deferred vblank work state.
275 	 */
276 	spinlock_t vblank_lock;
277 #endif
278 
279 	/**
280 	 * @audio_component:
281 	 *
282 	 * Used to notify ELD changes to sound driver.
283 	 */
284 	struct drm_audio_component *audio_component;
285 
286 	/**
287 	 * @audio_registered:
288 	 *
289 	 * True if the audio component has been registered
290 	 * successfully, false otherwise.
291 	 */
292 	bool audio_registered;
293 
294 	/**
295 	 * @irq_handler_list_low_tab:
296 	 *
297 	 * Low priority IRQ handler table.
298 	 *
299 	 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
300 	 * source. Low priority IRQ handlers are deferred to a workqueue to be
301 	 * processed. Hence, they can sleep.
302 	 *
303 	 * Note that handlers are called in the same order as they were
304 	 * registered (FIFO).
305 	 */
306 	struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
307 
308 	/**
309 	 * @irq_handler_list_high_tab:
310 	 *
311 	 * High priority IRQ handler table.
312 	 *
313 	 * It is a n*m table, same as &irq_handler_list_low_tab. However,
314 	 * handlers in this table are not deferred and are called immediately.
315 	 */
316 	struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
317 
318 	/**
319 	 * @pflip_params:
320 	 *
321 	 * Page flip IRQ parameters, passed to registered handlers when
322 	 * triggered.
323 	 */
324 	struct common_irq_params
325 	pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
326 
327 	/**
328 	 * @vblank_params:
329 	 *
330 	 * Vertical blanking IRQ parameters, passed to registered handlers when
331 	 * triggered.
332 	 */
333 	struct common_irq_params
334 	vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
335 
336 	/**
337 	 * @vline0_params:
338 	 *
339 	 * OTG vertical interrupt0 IRQ parameters, passed to registered
340 	 * handlers when triggered.
341 	 */
342 	struct common_irq_params
343 	vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
344 
345 	/**
346 	 * @vupdate_params:
347 	 *
348 	 * Vertical update IRQ parameters, passed to registered handlers when
349 	 * triggered.
350 	 */
351 	struct common_irq_params
352 	vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
353 
354 	/**
355 	 * @dmub_trace_params:
356 	 *
357 	 * DMUB trace event IRQ parameters, passed to registered handlers when
358 	 * triggered.
359 	 */
360 	struct common_irq_params
361 	dmub_trace_params[1];
362 
363 	struct common_irq_params
364 	dmub_outbox_params[1];
365 
366 	spinlock_t irq_handler_list_table_lock;
367 
368 	struct backlight_device *backlight_dev;
369 
370 	const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
371 
372 	uint8_t num_of_edps;
373 
374 	struct amdgpu_dm_backlight_caps backlight_caps;
375 
376 	struct mod_freesync *freesync_module;
377 #ifdef CONFIG_DRM_AMD_DC_HDCP
378 	struct hdcp_workqueue *hdcp_workqueue;
379 #endif
380 
381 #if defined(CONFIG_DRM_AMD_DC_DCN)
382 	/**
383 	 * @vblank_workqueue:
384 	 *
385 	 * amdgpu workqueue during vblank
386 	 */
387 	struct vblank_workqueue *vblank_workqueue;
388 #endif
389 
390 	struct drm_atomic_state *cached_state;
391 	struct dc_state *cached_dc_state;
392 
393 	struct dm_compressor_info compressor;
394 
395 	const struct firmware *fw_dmcu;
396 	uint32_t dmcu_fw_version;
397 	/**
398 	 * @soc_bounding_box:
399 	 *
400 	 * gpu_info FW provided soc bounding box struct or 0 if not
401 	 * available in FW
402 	 */
403 	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
404 
405 #if defined(CONFIG_DRM_AMD_DC_DCN)
406 	/**
407 	 * @active_vblank_irq_count:
408 	 *
409 	 * number of currently active vblank irqs
410 	 */
411 	uint32_t active_vblank_irq_count;
412 #endif
413 
414 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
415 	/**
416 	 * @crc_rd_wrk:
417 	 *
418 	 * Work to be executed in a separate thread to communicate with PSP.
419 	 */
420 	struct crc_rd_work *crc_rd_wrk;
421 #endif
422 
423 	/**
424 	 * @mst_encoders:
425 	 *
426 	 * fake encoders used for DP MST.
427 	 */
428 	struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
429 	bool force_timing_sync;
430 	bool disable_hpd_irq;
431 	bool dmcub_trace_event_en;
432 	/**
433 	 * @da_list:
434 	 *
435 	 * DAL fb memory allocation list, for communication with SMU.
436 	 */
437 	struct list_head da_list;
438 	struct completion dmub_aux_transfer_done;
439 
440 	/**
441 	 * @brightness:
442 	 *
443 	 * cached backlight values.
444 	 */
445 	u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
446 };
447 
448 enum dsc_clock_force_state {
449 	DSC_CLK_FORCE_DEFAULT = 0,
450 	DSC_CLK_FORCE_ENABLE,
451 	DSC_CLK_FORCE_DISABLE,
452 };
453 
454 struct dsc_preferred_settings {
455 	enum dsc_clock_force_state dsc_force_enable;
456 	uint32_t dsc_num_slices_v;
457 	uint32_t dsc_num_slices_h;
458 	uint32_t dsc_bits_per_pixel;
459 };
460 
461 struct amdgpu_dm_connector {
462 
463 	struct drm_connector base;
464 	uint32_t connector_id;
465 
466 	/* we need to mind the EDID between detect
467 	   and get modes due to analog/digital/tvencoder */
468 	struct edid *edid;
469 
470 	/* shared with amdgpu */
471 	struct amdgpu_hpd hpd;
472 
473 	/* number of modes generated from EDID at 'dc_sink' */
474 	int num_modes;
475 
476 	/* The 'old' sink - before an HPD.
477 	 * The 'current' sink is in dc_link->sink. */
478 	struct dc_sink *dc_sink;
479 	struct dc_link *dc_link;
480 	struct dc_sink *dc_em_sink;
481 
482 	/* DM only */
483 	struct drm_dp_mst_topology_mgr mst_mgr;
484 	struct amdgpu_dm_dp_aux dm_dp_aux;
485 	struct drm_dp_mst_port *port;
486 	struct amdgpu_dm_connector *mst_port;
487 	struct drm_dp_aux *dsc_aux;
488 
489 	/* TODO see if we can merge with ddc_bus or make a dm_connector */
490 	struct amdgpu_i2c_adapter *i2c;
491 
492 	/* Monitor range limits */
493 	int min_vfreq ;
494 	int max_vfreq ;
495 	int pixel_clock_mhz;
496 
497 	/* Audio instance - protected by audio_lock. */
498 	int audio_inst;
499 
500 	struct mutex hpd_lock;
501 
502 	bool fake_enable;
503 #ifdef CONFIG_DEBUG_FS
504 	uint32_t debugfs_dpcd_address;
505 	uint32_t debugfs_dpcd_size;
506 #endif
507 	bool force_yuv420_output;
508 	struct dsc_preferred_settings dsc_settings;
509 	/* Cached display modes */
510 	struct drm_display_mode freesync_vid_base;
511 };
512 
513 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
514 
515 extern const struct amdgpu_ip_block_version dm_ip_block;
516 
517 struct dm_plane_state {
518 	struct drm_plane_state base;
519 	struct dc_plane_state *dc_state;
520 };
521 
522 struct dm_crtc_state {
523 	struct drm_crtc_state base;
524 	struct dc_stream_state *stream;
525 
526 	bool cm_has_degamma;
527 	bool cm_is_degamma_srgb;
528 
529 	int update_type;
530 	int active_planes;
531 
532 	int crc_skip_count;
533 
534 	bool freesync_timing_changed;
535 	bool freesync_vrr_info_changed;
536 
537 	bool dsc_force_changed;
538 	bool vrr_supported;
539 	struct mod_freesync_config freesync_config;
540 	struct dc_info_packet vrr_infopacket;
541 
542 	int abm_level;
543 };
544 
545 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
546 
547 struct dm_atomic_state {
548 	struct drm_private_state base;
549 
550 	struct dc_state *context;
551 };
552 
553 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
554 
555 struct dm_connector_state {
556 	struct drm_connector_state base;
557 
558 	enum amdgpu_rmx_type scaling;
559 	uint8_t underscan_vborder;
560 	uint8_t underscan_hborder;
561 	bool underscan_enable;
562 	bool freesync_capable;
563 #ifdef CONFIG_DRM_AMD_DC_HDCP
564 	bool update_hdcp;
565 #endif
566 	uint8_t abm_level;
567 	int vcpi_slots;
568 	uint64_t pbn;
569 };
570 
571 struct amdgpu_hdmi_vsdb_info {
572 	unsigned int amd_vsdb_version;		/* VSDB version, should be used to determine which VSIF to send */
573 	bool freesync_supported;		/* FreeSync Supported */
574 	unsigned int min_refresh_rate_hz;	/* FreeSync Minimum Refresh Rate in Hz */
575 	unsigned int max_refresh_rate_hz;	/* FreeSync Maximum Refresh Rate in Hz */
576 };
577 
578 
579 #define to_dm_connector_state(x)\
580 	container_of((x), struct dm_connector_state, base)
581 
582 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
583 struct drm_connector_state *
584 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
585 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
586 					    struct drm_connector_state *state,
587 					    struct drm_property *property,
588 					    uint64_t val);
589 
590 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
591 					    const struct drm_connector_state *state,
592 					    struct drm_property *property,
593 					    uint64_t *val);
594 
595 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
596 
597 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
598 				     struct amdgpu_dm_connector *aconnector,
599 				     int connector_type,
600 				     struct dc_link *link,
601 				     int link_index);
602 
603 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
604 				   struct drm_display_mode *mode);
605 
606 void dm_restore_drm_connector_state(struct drm_device *dev,
607 				    struct drm_connector *connector);
608 
609 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
610 					struct edid *edid);
611 
612 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
613 
614 #define MAX_COLOR_LUT_ENTRIES 4096
615 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
616 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
617 
618 void amdgpu_dm_init_color_mod(void);
619 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
620 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
621 				      struct dc_plane_state *dc_plane_state);
622 
623 void amdgpu_dm_update_connector_after_detect(
624 		struct amdgpu_dm_connector *aconnector);
625 
626 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
627 
628 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int linkIndex,
629 					struct aux_payload *payload, enum aux_return_code_type *operation_result);
630 #endif /* __AMDGPU_DM_H__ */
631