1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 36 /* 37 * This file contains the definition for amdgpu_display_manager 38 * and its API for amdgpu driver's use. 39 * This component provides all the display related functionality 40 * and this is the only component that calls DAL API. 41 * The API contained here intended for amdgpu driver use. 42 * The API that is called directly from KMS framework is located 43 * in amdgpu_dm_kms.h file 44 */ 45 46 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 47 48 #define AMDGPU_DM_MAX_CRTC 6 49 50 #define AMDGPU_DM_MAX_NUM_EDP 2 51 52 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 53 54 /* 55 #include "include/amdgpu_dal_power_if.h" 56 #include "amdgpu_dm_irq.h" 57 */ 58 59 #include "irq_types.h" 60 #include "signal_types.h" 61 #include "amdgpu_dm_crc.h" 62 struct aux_payload; 63 struct set_config_cmd_payload; 64 enum aux_return_code_type; 65 enum set_config_status; 66 67 /* Forward declarations */ 68 struct amdgpu_device; 69 struct amdgpu_crtc; 70 struct drm_device; 71 struct dc; 72 struct amdgpu_bo; 73 struct dmub_srv; 74 struct dc_plane_state; 75 struct dmub_notification; 76 77 struct common_irq_params { 78 struct amdgpu_device *adev; 79 enum dc_irq_source irq_src; 80 atomic64_t previous_timestamp; 81 }; 82 83 /** 84 * struct dm_compressor_info - Buffer info used by frame buffer compression 85 * @cpu_addr: MMIO cpu addr 86 * @bo_ptr: Pointer to the buffer object 87 * @gpu_addr: MMIO gpu addr 88 */ 89 struct dm_compressor_info { 90 void *cpu_addr; 91 struct amdgpu_bo *bo_ptr; 92 uint64_t gpu_addr; 93 }; 94 95 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 96 97 /** 98 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 99 * 100 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 101 * @dmub_notify: notification for callback function 102 * @adev: amdgpu_device pointer 103 */ 104 struct dmub_hpd_work { 105 struct work_struct handle_hpd_work; 106 struct dmub_notification *dmub_notify; 107 struct amdgpu_device *adev; 108 }; 109 110 /** 111 * struct vblank_control_work - Work data for vblank control 112 * @work: Kernel work data for the work event 113 * @dm: amdgpu display manager device 114 * @acrtc: amdgpu CRTC instance for which the event has occurred 115 * @stream: DC stream for which the event has occurred 116 * @enable: true if enabling vblank 117 */ 118 struct vblank_control_work { 119 struct work_struct work; 120 struct amdgpu_display_manager *dm; 121 struct amdgpu_crtc *acrtc; 122 struct dc_stream_state *stream; 123 bool enable; 124 }; 125 126 /** 127 * struct amdgpu_dm_backlight_caps - Information about backlight 128 * 129 * Describe the backlight support for ACPI or eDP AUX. 130 */ 131 struct amdgpu_dm_backlight_caps { 132 /** 133 * @ext_caps: Keep the data struct with all the information about the 134 * display support for HDR. 135 */ 136 union dpcd_sink_ext_caps *ext_caps; 137 /** 138 * @aux_min_input_signal: Min brightness value supported by the display 139 */ 140 u32 aux_min_input_signal; 141 /** 142 * @aux_max_input_signal: Max brightness value supported by the display 143 * in nits. 144 */ 145 u32 aux_max_input_signal; 146 /** 147 * @min_input_signal: minimum possible input in range 0-255. 148 */ 149 int min_input_signal; 150 /** 151 * @max_input_signal: maximum possible input in range 0-255. 152 */ 153 int max_input_signal; 154 /** 155 * @caps_valid: true if these values are from the ACPI interface. 156 */ 157 bool caps_valid; 158 /** 159 * @aux_support: Describes if the display supports AUX backlight. 160 */ 161 bool aux_support; 162 }; 163 164 /** 165 * struct dal_allocation - Tracks mapped FB memory for SMU communication 166 * @list: list of dal allocations 167 * @bo: GPU buffer object 168 * @cpu_ptr: CPU virtual address of the GPU buffer object 169 * @gpu_addr: GPU virtual address of the GPU buffer object 170 */ 171 struct dal_allocation { 172 struct list_head list; 173 struct amdgpu_bo *bo; 174 void *cpu_ptr; 175 u64 gpu_addr; 176 }; 177 178 /** 179 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 180 * offload work 181 */ 182 struct hpd_rx_irq_offload_work_queue { 183 /** 184 * @wq: workqueue structure to queue offload work. 185 */ 186 struct workqueue_struct *wq; 187 /** 188 * @offload_lock: To protect fields of offload work queue. 189 */ 190 spinlock_t offload_lock; 191 /** 192 * @is_handling_link_loss: Used to prevent inserting link loss event when 193 * we're handling link loss 194 */ 195 bool is_handling_link_loss; 196 /** 197 * @aconnector: The aconnector that this work queue is attached to 198 */ 199 struct amdgpu_dm_connector *aconnector; 200 }; 201 202 /** 203 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 204 */ 205 struct hpd_rx_irq_offload_work { 206 /** 207 * @work: offload work 208 */ 209 struct work_struct work; 210 /** 211 * @data: reference irq data which is used while handling offload work 212 */ 213 union hpd_irq_data data; 214 /** 215 * @offload_wq: offload work queue that this work is queued to 216 */ 217 struct hpd_rx_irq_offload_work_queue *offload_wq; 218 }; 219 220 /** 221 * struct amdgpu_display_manager - Central amdgpu display manager device 222 * 223 * @dc: Display Core control structure 224 * @adev: AMDGPU base driver structure 225 * @ddev: DRM base driver structure 226 * @display_indexes_num: Max number of display streams supported 227 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 228 * @backlight_dev: Backlight control device 229 * @backlight_link: Link on which to control backlight 230 * @backlight_caps: Capabilities of the backlight device 231 * @freesync_module: Module handling freesync calculations 232 * @hdcp_workqueue: AMDGPU content protection queue 233 * @fw_dmcu: Reference to DMCU firmware 234 * @dmcu_fw_version: Version of the DMCU firmware 235 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 236 * @cached_state: Caches device atomic state for suspend/resume 237 * @cached_dc_state: Cached state of content streams 238 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 239 * @force_timing_sync: set via debugfs. When set, indicates that all connected 240 * displays will be forced to synchronize. 241 * @dmcub_trace_event_en: enable dmcub trace events 242 * @dmub_outbox_params: DMUB Outbox parameters 243 * @num_of_edps: number of backlight eDPs 244 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 245 * driver when true 246 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 247 * transfers are done 248 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 249 */ 250 struct amdgpu_display_manager { 251 252 struct dc *dc; 253 254 /** 255 * @dmub_srv: 256 * 257 * DMUB service, used for controlling the DMUB on hardware 258 * that supports it. The pointer to the dmub_srv will be 259 * NULL on hardware that does not support it. 260 */ 261 struct dmub_srv *dmub_srv; 262 263 /** 264 * @dmub_notify: 265 * 266 * Notification from DMUB. 267 */ 268 269 struct dmub_notification *dmub_notify; 270 271 /** 272 * @dmub_callback: 273 * 274 * Callback functions to handle notification from DMUB. 275 */ 276 277 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 278 279 /** 280 * @dmub_thread_offload: 281 * 282 * Flag to indicate if callback is offload. 283 */ 284 285 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 286 287 /** 288 * @dmub_fb_info: 289 * 290 * Framebuffer regions for the DMUB. 291 */ 292 struct dmub_srv_fb_info *dmub_fb_info; 293 294 /** 295 * @dmub_fw: 296 * 297 * DMUB firmware, required on hardware that has DMUB support. 298 */ 299 const struct firmware *dmub_fw; 300 301 /** 302 * @dmub_bo: 303 * 304 * Buffer object for the DMUB. 305 */ 306 struct amdgpu_bo *dmub_bo; 307 308 /** 309 * @dmub_bo_gpu_addr: 310 * 311 * GPU virtual address for the DMUB buffer object. 312 */ 313 u64 dmub_bo_gpu_addr; 314 315 /** 316 * @dmub_bo_cpu_addr: 317 * 318 * CPU address for the DMUB buffer object. 319 */ 320 void *dmub_bo_cpu_addr; 321 322 /** 323 * @dmcub_fw_version: 324 * 325 * DMCUB firmware version. 326 */ 327 uint32_t dmcub_fw_version; 328 329 /** 330 * @cgs_device: 331 * 332 * The Common Graphics Services device. It provides an interface for 333 * accessing registers. 334 */ 335 struct cgs_device *cgs_device; 336 337 struct amdgpu_device *adev; 338 struct drm_device *ddev; 339 u16 display_indexes_num; 340 341 /** 342 * @atomic_obj: 343 * 344 * In combination with &dm_atomic_state it helps manage 345 * global atomic state that doesn't map cleanly into existing 346 * drm resources, like &dc_context. 347 */ 348 struct drm_private_obj atomic_obj; 349 350 /** 351 * @dc_lock: 352 * 353 * Guards access to DC functions that can issue register write 354 * sequences. 355 */ 356 struct mutex dc_lock; 357 358 /** 359 * @audio_lock: 360 * 361 * Guards access to audio instance changes. 362 */ 363 struct mutex audio_lock; 364 365 /** 366 * @audio_component: 367 * 368 * Used to notify ELD changes to sound driver. 369 */ 370 struct drm_audio_component *audio_component; 371 372 /** 373 * @audio_registered: 374 * 375 * True if the audio component has been registered 376 * successfully, false otherwise. 377 */ 378 bool audio_registered; 379 380 /** 381 * @irq_handler_list_low_tab: 382 * 383 * Low priority IRQ handler table. 384 * 385 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 386 * source. Low priority IRQ handlers are deferred to a workqueue to be 387 * processed. Hence, they can sleep. 388 * 389 * Note that handlers are called in the same order as they were 390 * registered (FIFO). 391 */ 392 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 393 394 /** 395 * @irq_handler_list_high_tab: 396 * 397 * High priority IRQ handler table. 398 * 399 * It is a n*m table, same as &irq_handler_list_low_tab. However, 400 * handlers in this table are not deferred and are called immediately. 401 */ 402 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 403 404 /** 405 * @pflip_params: 406 * 407 * Page flip IRQ parameters, passed to registered handlers when 408 * triggered. 409 */ 410 struct common_irq_params 411 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 412 413 /** 414 * @vblank_params: 415 * 416 * Vertical blanking IRQ parameters, passed to registered handlers when 417 * triggered. 418 */ 419 struct common_irq_params 420 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 421 422 /** 423 * @vline0_params: 424 * 425 * OTG vertical interrupt0 IRQ parameters, passed to registered 426 * handlers when triggered. 427 */ 428 struct common_irq_params 429 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 430 431 /** 432 * @vupdate_params: 433 * 434 * Vertical update IRQ parameters, passed to registered handlers when 435 * triggered. 436 */ 437 struct common_irq_params 438 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 439 440 /** 441 * @dmub_trace_params: 442 * 443 * DMUB trace event IRQ parameters, passed to registered handlers when 444 * triggered. 445 */ 446 struct common_irq_params 447 dmub_trace_params[1]; 448 449 struct common_irq_params 450 dmub_outbox_params[1]; 451 452 spinlock_t irq_handler_list_table_lock; 453 454 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 455 456 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 457 458 uint8_t num_of_edps; 459 460 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 461 462 struct mod_freesync *freesync_module; 463 #ifdef CONFIG_DRM_AMD_DC_HDCP 464 struct hdcp_workqueue *hdcp_workqueue; 465 #endif 466 467 /** 468 * @vblank_control_workqueue: 469 * 470 * Deferred work for vblank control events. 471 */ 472 struct workqueue_struct *vblank_control_workqueue; 473 474 struct drm_atomic_state *cached_state; 475 struct dc_state *cached_dc_state; 476 477 struct dm_compressor_info compressor; 478 479 const struct firmware *fw_dmcu; 480 uint32_t dmcu_fw_version; 481 /** 482 * @soc_bounding_box: 483 * 484 * gpu_info FW provided soc bounding box struct or 0 if not 485 * available in FW 486 */ 487 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 488 489 /** 490 * @active_vblank_irq_count: 491 * 492 * number of currently active vblank irqs 493 */ 494 uint32_t active_vblank_irq_count; 495 496 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 497 /** 498 * @secure_display_ctxs: 499 * 500 * Store the ROI information and the work_struct to command dmub and psp for 501 * all crtcs. 502 */ 503 struct secure_display_context *secure_display_ctxs; 504 #endif 505 /** 506 * @hpd_rx_offload_wq: 507 * 508 * Work queue to offload works of hpd_rx_irq 509 */ 510 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 511 /** 512 * @mst_encoders: 513 * 514 * fake encoders used for DP MST. 515 */ 516 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 517 bool force_timing_sync; 518 bool disable_hpd_irq; 519 bool dmcub_trace_event_en; 520 /** 521 * @da_list: 522 * 523 * DAL fb memory allocation list, for communication with SMU. 524 */ 525 struct list_head da_list; 526 struct completion dmub_aux_transfer_done; 527 struct workqueue_struct *delayed_hpd_wq; 528 529 /** 530 * @brightness: 531 * 532 * cached backlight values. 533 */ 534 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 535 /** 536 * @actual_brightness: 537 * 538 * last successfully applied backlight values. 539 */ 540 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 541 542 /** 543 * @aux_hpd_discon_quirk: 544 * 545 * quirk for hpd discon while aux is on-going. 546 * occurred on certain intel platform 547 */ 548 bool aux_hpd_discon_quirk; 549 550 /** 551 * @dpia_aux_lock: 552 * 553 * Guards access to DPIA AUX 554 */ 555 struct mutex dpia_aux_lock; 556 }; 557 558 enum dsc_clock_force_state { 559 DSC_CLK_FORCE_DEFAULT = 0, 560 DSC_CLK_FORCE_ENABLE, 561 DSC_CLK_FORCE_DISABLE, 562 }; 563 564 struct dsc_preferred_settings { 565 enum dsc_clock_force_state dsc_force_enable; 566 uint32_t dsc_num_slices_v; 567 uint32_t dsc_num_slices_h; 568 uint32_t dsc_bits_per_pixel; 569 bool dsc_force_disable_passthrough; 570 }; 571 572 enum mst_progress_status { 573 MST_STATUS_DEFAULT = 0, 574 MST_PROBE = BIT(0), 575 MST_REMOTE_EDID = BIT(1), 576 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 577 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 578 }; 579 580 struct amdgpu_dm_connector { 581 582 struct drm_connector base; 583 uint32_t connector_id; 584 585 /* we need to mind the EDID between detect 586 and get modes due to analog/digital/tvencoder */ 587 struct edid *edid; 588 589 /* shared with amdgpu */ 590 struct amdgpu_hpd hpd; 591 592 /* number of modes generated from EDID at 'dc_sink' */ 593 int num_modes; 594 595 /* The 'old' sink - before an HPD. 596 * The 'current' sink is in dc_link->sink. */ 597 struct dc_sink *dc_sink; 598 struct dc_link *dc_link; 599 600 /** 601 * @dc_em_sink: Reference to the emulated (virtual) sink. 602 */ 603 struct dc_sink *dc_em_sink; 604 605 /* DM only */ 606 struct drm_dp_mst_topology_mgr mst_mgr; 607 struct amdgpu_dm_dp_aux dm_dp_aux; 608 struct drm_dp_mst_port *mst_output_port; 609 struct amdgpu_dm_connector *mst_root; 610 struct drm_dp_aux *dsc_aux; 611 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 612 struct amdgpu_i2c_adapter *i2c; 613 614 /* Monitor range limits */ 615 /** 616 * @min_vfreq: Minimal frequency supported by the display in Hz. This 617 * value is set to zero when there is no FreeSync support. 618 */ 619 int min_vfreq; 620 621 /** 622 * @max_vfreq: Maximum frequency supported by the display in Hz. This 623 * value is set to zero when there is no FreeSync support. 624 */ 625 int max_vfreq ; 626 int pixel_clock_mhz; 627 628 /* Audio instance - protected by audio_lock. */ 629 int audio_inst; 630 631 struct mutex hpd_lock; 632 633 bool fake_enable; 634 #ifdef CONFIG_DEBUG_FS 635 uint32_t debugfs_dpcd_address; 636 uint32_t debugfs_dpcd_size; 637 #endif 638 bool force_yuv420_output; 639 struct dsc_preferred_settings dsc_settings; 640 union dp_downstream_port_present mst_downstream_port_present; 641 /* Cached display modes */ 642 struct drm_display_mode freesync_vid_base; 643 644 int psr_skip_count; 645 646 /* Record progress status of mst*/ 647 uint8_t mst_status; 648 649 /* Automated testing */ 650 bool timing_changed; 651 struct dc_crtc_timing *timing_requested; 652 }; 653 654 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 655 uint8_t flags, bool set) 656 { 657 if (set) 658 *status |= flags; 659 else 660 *status &= ~flags; 661 } 662 663 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 664 665 extern const struct amdgpu_ip_block_version dm_ip_block; 666 667 struct dm_plane_state { 668 struct drm_plane_state base; 669 struct dc_plane_state *dc_state; 670 }; 671 672 struct dm_crtc_state { 673 struct drm_crtc_state base; 674 struct dc_stream_state *stream; 675 676 bool cm_has_degamma; 677 bool cm_is_degamma_srgb; 678 679 bool mpo_requested; 680 681 int update_type; 682 int active_planes; 683 684 int crc_skip_count; 685 686 bool freesync_vrr_info_changed; 687 688 bool dsc_force_changed; 689 bool vrr_supported; 690 struct mod_freesync_config freesync_config; 691 struct dc_info_packet vrr_infopacket; 692 693 int abm_level; 694 }; 695 696 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 697 698 struct dm_atomic_state { 699 struct drm_private_state base; 700 701 struct dc_state *context; 702 }; 703 704 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 705 706 struct dm_connector_state { 707 struct drm_connector_state base; 708 709 enum amdgpu_rmx_type scaling; 710 uint8_t underscan_vborder; 711 uint8_t underscan_hborder; 712 bool underscan_enable; 713 bool freesync_capable; 714 #ifdef CONFIG_DRM_AMD_DC_HDCP 715 bool update_hdcp; 716 #endif 717 uint8_t abm_level; 718 int vcpi_slots; 719 uint64_t pbn; 720 }; 721 722 /** 723 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 724 * 725 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 726 * struct is useful to keep track of the display-specific information about 727 * FreeSync. 728 */ 729 struct amdgpu_hdmi_vsdb_info { 730 /** 731 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 732 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 733 */ 734 unsigned int amd_vsdb_version; 735 736 /** 737 * @freesync_supported: FreeSync Supported. 738 */ 739 bool freesync_supported; 740 741 /** 742 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 743 */ 744 unsigned int min_refresh_rate_hz; 745 746 /** 747 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 748 */ 749 unsigned int max_refresh_rate_hz; 750 }; 751 752 753 #define to_dm_connector_state(x)\ 754 container_of((x), struct dm_connector_state, base) 755 756 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 757 struct drm_connector_state * 758 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 759 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 760 struct drm_connector_state *state, 761 struct drm_property *property, 762 uint64_t val); 763 764 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 765 const struct drm_connector_state *state, 766 struct drm_property *property, 767 uint64_t *val); 768 769 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 770 771 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 772 struct amdgpu_dm_connector *aconnector, 773 int connector_type, 774 struct dc_link *link, 775 int link_index); 776 777 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 778 struct drm_display_mode *mode); 779 780 void dm_restore_drm_connector_state(struct drm_device *dev, 781 struct drm_connector *connector); 782 783 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 784 struct edid *edid); 785 786 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 787 788 #define MAX_COLOR_LUT_ENTRIES 4096 789 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 790 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 791 792 void amdgpu_dm_init_color_mod(void); 793 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 794 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 795 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 796 struct dc_plane_state *dc_plane_state); 797 798 void amdgpu_dm_update_connector_after_detect( 799 struct amdgpu_dm_connector *aconnector); 800 801 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 802 803 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 804 struct aux_payload *payload, enum aux_return_code_type *operation_result); 805 806 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 807 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 808 809 bool check_seamless_boot_capability(struct amdgpu_device *adev); 810 811 struct dc_stream_state * 812 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 813 const struct drm_display_mode *drm_mode, 814 const struct dm_connector_state *dm_state, 815 const struct dc_stream_state *old_stream); 816 817 int dm_atomic_get_state(struct drm_atomic_state *state, 818 struct dm_atomic_state **dm_state); 819 820 struct amdgpu_dm_connector * 821 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 822 struct drm_crtc *crtc); 823 824 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 825 #endif /* __AMDGPU_DM_H__ */ 826