1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct amdgpu_dm_irq_handler_data; 62 struct dc; 63 struct amdgpu_bo; 64 struct dmub_srv; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 }; 70 71 /** 72 * struct irq_list_head - Linked-list for low context IRQ handlers. 73 * 74 * @head: The list_head within &struct handler_data 75 * @work: A work_struct containing the deferred handler work 76 */ 77 struct irq_list_head { 78 struct list_head head; 79 /* In case this interrupt needs post-processing, 'work' will be queued*/ 80 struct work_struct work; 81 }; 82 83 /** 84 * struct dm_compressor_info - Buffer info used by frame buffer compression 85 * @cpu_addr: MMIO cpu addr 86 * @bo_ptr: Pointer to the buffer object 87 * @gpu_addr: MMIO gpu addr 88 */ 89 struct dm_comressor_info { 90 void *cpu_addr; 91 struct amdgpu_bo *bo_ptr; 92 uint64_t gpu_addr; 93 }; 94 95 /** 96 * struct amdgpu_dm_backlight_caps - Information about backlight 97 * 98 * Describe the backlight support for ACPI or eDP AUX. 99 */ 100 struct amdgpu_dm_backlight_caps { 101 /** 102 * @ext_caps: Keep the data struct with all the information about the 103 * display support for HDR. 104 */ 105 union dpcd_sink_ext_caps *ext_caps; 106 /** 107 * @aux_min_input_signal: Min brightness value supported by the display 108 */ 109 u32 aux_min_input_signal; 110 /** 111 * @aux_max_input_signal: Max brightness value supported by the display 112 * in nits. 113 */ 114 u32 aux_max_input_signal; 115 /** 116 * @min_input_signal: minimum possible input in range 0-255. 117 */ 118 int min_input_signal; 119 /** 120 * @max_input_signal: maximum possible input in range 0-255. 121 */ 122 int max_input_signal; 123 /** 124 * @caps_valid: true if these values are from the ACPI interface. 125 */ 126 bool caps_valid; 127 /** 128 * @aux_support: Describes if the display supports AUX backlight. 129 */ 130 bool aux_support; 131 }; 132 133 /** 134 * struct amdgpu_display_manager - Central amdgpu display manager device 135 * 136 * @dc: Display Core control structure 137 * @adev: AMDGPU base driver structure 138 * @ddev: DRM base driver structure 139 * @display_indexes_num: Max number of display streams supported 140 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 141 * @backlight_dev: Backlight control device 142 * @backlight_link: Link on which to control backlight 143 * @backlight_caps: Capabilities of the backlight device 144 * @freesync_module: Module handling freesync calculations 145 * @fw_dmcu: Reference to DMCU firmware 146 * @dmcu_fw_version: Version of the DMCU firmware 147 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 148 * @cached_state: Caches device atomic state for suspend/resume 149 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 150 */ 151 struct amdgpu_display_manager { 152 153 struct dc *dc; 154 155 /** 156 * @dmub_srv: 157 * 158 * DMUB service, used for controlling the DMUB on hardware 159 * that supports it. The pointer to the dmub_srv will be 160 * NULL on hardware that does not support it. 161 */ 162 struct dmub_srv *dmub_srv; 163 164 /** 165 * @dmub_fb_info: 166 * 167 * Framebuffer regions for the DMUB. 168 */ 169 struct dmub_srv_fb_info *dmub_fb_info; 170 171 /** 172 * @dmub_fw: 173 * 174 * DMUB firmware, required on hardware that has DMUB support. 175 */ 176 const struct firmware *dmub_fw; 177 178 /** 179 * @dmub_bo: 180 * 181 * Buffer object for the DMUB. 182 */ 183 struct amdgpu_bo *dmub_bo; 184 185 /** 186 * @dmub_bo_gpu_addr: 187 * 188 * GPU virtual address for the DMUB buffer object. 189 */ 190 u64 dmub_bo_gpu_addr; 191 192 /** 193 * @dmub_bo_cpu_addr: 194 * 195 * CPU address for the DMUB buffer object. 196 */ 197 void *dmub_bo_cpu_addr; 198 199 /** 200 * @dmcub_fw_version: 201 * 202 * DMCUB firmware version. 203 */ 204 uint32_t dmcub_fw_version; 205 206 /** 207 * @cgs_device: 208 * 209 * The Common Graphics Services device. It provides an interface for 210 * accessing registers. 211 */ 212 struct cgs_device *cgs_device; 213 214 struct amdgpu_device *adev; 215 struct drm_device *ddev; 216 u16 display_indexes_num; 217 218 /** 219 * @atomic_obj: 220 * 221 * In combination with &dm_atomic_state it helps manage 222 * global atomic state that doesn't map cleanly into existing 223 * drm resources, like &dc_context. 224 */ 225 struct drm_private_obj atomic_obj; 226 227 /** 228 * @dc_lock: 229 * 230 * Guards access to DC functions that can issue register write 231 * sequences. 232 */ 233 struct mutex dc_lock; 234 235 /** 236 * @audio_lock: 237 * 238 * Guards access to audio instance changes. 239 */ 240 struct mutex audio_lock; 241 242 /** 243 * @audio_component: 244 * 245 * Used to notify ELD changes to sound driver. 246 */ 247 struct drm_audio_component *audio_component; 248 249 /** 250 * @audio_registered: 251 * 252 * True if the audio component has been registered 253 * successfully, false otherwise. 254 */ 255 bool audio_registered; 256 257 /** 258 * @irq_handler_list_low_tab: 259 * 260 * Low priority IRQ handler table. 261 * 262 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 263 * source. Low priority IRQ handlers are deferred to a workqueue to be 264 * processed. Hence, they can sleep. 265 * 266 * Note that handlers are called in the same order as they were 267 * registered (FIFO). 268 */ 269 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 270 271 /** 272 * @irq_handler_list_high_tab: 273 * 274 * High priority IRQ handler table. 275 * 276 * It is a n*m table, same as &irq_handler_list_low_tab. However, 277 * handlers in this table are not deferred and are called immediately. 278 */ 279 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 280 281 /** 282 * @pflip_params: 283 * 284 * Page flip IRQ parameters, passed to registered handlers when 285 * triggered. 286 */ 287 struct common_irq_params 288 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 289 290 /** 291 * @vblank_params: 292 * 293 * Vertical blanking IRQ parameters, passed to registered handlers when 294 * triggered. 295 */ 296 struct common_irq_params 297 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 298 299 /** 300 * @vupdate_params: 301 * 302 * Vertical update IRQ parameters, passed to registered handlers when 303 * triggered. 304 */ 305 struct common_irq_params 306 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 307 308 spinlock_t irq_handler_list_table_lock; 309 310 struct backlight_device *backlight_dev; 311 312 const struct dc_link *backlight_link; 313 struct amdgpu_dm_backlight_caps backlight_caps; 314 315 struct mod_freesync *freesync_module; 316 #ifdef CONFIG_DRM_AMD_DC_HDCP 317 struct hdcp_workqueue *hdcp_workqueue; 318 #endif 319 320 struct drm_atomic_state *cached_state; 321 struct dc_state *cached_dc_state; 322 323 struct dm_comressor_info compressor; 324 325 const struct firmware *fw_dmcu; 326 uint32_t dmcu_fw_version; 327 /** 328 * @soc_bounding_box: 329 * 330 * gpu_info FW provided soc bounding box struct or 0 if not 331 * available in FW 332 */ 333 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 334 335 /** 336 * @mst_encoders: 337 * 338 * fake encoders used for DP MST. 339 */ 340 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 341 }; 342 343 struct amdgpu_dm_connector { 344 345 struct drm_connector base; 346 uint32_t connector_id; 347 348 /* we need to mind the EDID between detect 349 and get modes due to analog/digital/tvencoder */ 350 struct edid *edid; 351 352 /* shared with amdgpu */ 353 struct amdgpu_hpd hpd; 354 355 /* number of modes generated from EDID at 'dc_sink' */ 356 int num_modes; 357 358 /* The 'old' sink - before an HPD. 359 * The 'current' sink is in dc_link->sink. */ 360 struct dc_sink *dc_sink; 361 struct dc_link *dc_link; 362 struct dc_sink *dc_em_sink; 363 364 /* DM only */ 365 struct drm_dp_mst_topology_mgr mst_mgr; 366 struct amdgpu_dm_dp_aux dm_dp_aux; 367 struct drm_dp_mst_port *port; 368 struct amdgpu_dm_connector *mst_port; 369 struct drm_dp_aux *dsc_aux; 370 371 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 372 struct amdgpu_i2c_adapter *i2c; 373 374 /* Monitor range limits */ 375 int min_vfreq ; 376 int max_vfreq ; 377 int pixel_clock_mhz; 378 379 /* Audio instance - protected by audio_lock. */ 380 int audio_inst; 381 382 struct mutex hpd_lock; 383 384 bool fake_enable; 385 #ifdef CONFIG_DEBUG_FS 386 uint32_t debugfs_dpcd_address; 387 uint32_t debugfs_dpcd_size; 388 #endif 389 bool force_yuv420_output; 390 }; 391 392 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 393 394 extern const struct amdgpu_ip_block_version dm_ip_block; 395 396 struct amdgpu_framebuffer; 397 struct amdgpu_display_manager; 398 struct dc_validation_set; 399 struct dc_plane_state; 400 401 struct dm_plane_state { 402 struct drm_plane_state base; 403 struct dc_plane_state *dc_state; 404 }; 405 406 struct dm_crtc_state { 407 struct drm_crtc_state base; 408 struct dc_stream_state *stream; 409 410 bool cm_has_degamma; 411 bool cm_is_degamma_srgb; 412 413 int update_type; 414 int active_planes; 415 bool interrupts_enabled; 416 417 int crc_skip_count; 418 enum amdgpu_dm_pipe_crc_source crc_src; 419 420 bool freesync_timing_changed; 421 bool freesync_vrr_info_changed; 422 423 bool vrr_supported; 424 struct mod_freesync_config freesync_config; 425 struct mod_vrr_params vrr_params; 426 struct dc_info_packet vrr_infopacket; 427 428 int abm_level; 429 }; 430 431 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 432 433 struct dm_atomic_state { 434 struct drm_private_state base; 435 436 struct dc_state *context; 437 }; 438 439 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 440 441 struct dm_connector_state { 442 struct drm_connector_state base; 443 444 enum amdgpu_rmx_type scaling; 445 uint8_t underscan_vborder; 446 uint8_t underscan_hborder; 447 bool underscan_enable; 448 bool freesync_capable; 449 uint8_t abm_level; 450 int vcpi_slots; 451 uint64_t pbn; 452 }; 453 454 #define to_dm_connector_state(x)\ 455 container_of((x), struct dm_connector_state, base) 456 457 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 458 struct drm_connector_state * 459 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 460 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 461 struct drm_connector_state *state, 462 struct drm_property *property, 463 uint64_t val); 464 465 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 466 const struct drm_connector_state *state, 467 struct drm_property *property, 468 uint64_t *val); 469 470 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 471 472 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 473 struct amdgpu_dm_connector *aconnector, 474 int connector_type, 475 struct dc_link *link, 476 int link_index); 477 478 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 479 struct drm_display_mode *mode); 480 481 void dm_restore_drm_connector_state(struct drm_device *dev, 482 struct drm_connector *connector); 483 484 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 485 struct edid *edid); 486 487 #define MAX_COLOR_LUT_ENTRIES 4096 488 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 489 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 490 491 void amdgpu_dm_init_color_mod(void); 492 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 493 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 494 struct dc_plane_state *dc_plane_state); 495 496 void amdgpu_dm_update_connector_after_detect( 497 struct amdgpu_dm_connector *aconnector); 498 499 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 500 501 #endif /* __AMDGPU_DM_H__ */ 502