1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 /* 30 #include "linux/switch.h" 31 */ 32 33 /* 34 * This file contains the definition for amdgpu_display_manager 35 * and its API for amdgpu driver's use. 36 * This component provides all the display related functionality 37 * and this is the only component that calls DAL API. 38 * The API contained here intended for amdgpu driver use. 39 * The API that is called directly from KMS framework is located 40 * in amdgpu_dm_kms.h file 41 */ 42 43 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 44 /* 45 #include "include/amdgpu_dal_power_if.h" 46 #include "amdgpu_dm_irq.h" 47 */ 48 49 #include "irq_types.h" 50 #include "signal_types.h" 51 52 /* Forward declarations */ 53 struct amdgpu_device; 54 struct drm_device; 55 struct amdgpu_dm_irq_handler_data; 56 57 struct amdgpu_dm_prev_state { 58 struct drm_framebuffer *fb; 59 int32_t x; 60 int32_t y; 61 struct drm_display_mode mode; 62 }; 63 64 struct common_irq_params { 65 struct amdgpu_device *adev; 66 enum dc_irq_source irq_src; 67 }; 68 69 struct irq_list_head { 70 struct list_head head; 71 /* In case this interrupt needs post-processing, 'work' will be queued*/ 72 struct work_struct work; 73 }; 74 75 struct amdgpu_display_manager { 76 struct dal *dal; 77 struct dc *dc; 78 struct cgs_device *cgs_device; 79 /* lock to be used when DAL is called from SYNC IRQ context */ 80 spinlock_t dal_lock; 81 82 struct amdgpu_device *adev; /*AMD base driver*/ 83 struct drm_device *ddev; /*DRM base driver*/ 84 u16 display_indexes_num; 85 86 struct amdgpu_dm_prev_state prev_state; 87 88 /* 89 * 'irq_source_handler_table' holds a list of handlers 90 * per (DAL) IRQ source. 91 * 92 * Each IRQ source may need to be handled at different contexts. 93 * By 'context' we mean, for example: 94 * - The ISR context, which is the direct interrupt handler. 95 * - The 'deferred' context - this is the post-processing of the 96 * interrupt, but at a lower priority. 97 * 98 * Note that handlers are called in the same order as they were 99 * registered (FIFO). 100 */ 101 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 102 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 103 104 struct common_irq_params 105 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 106 107 struct common_irq_params 108 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 109 110 /* this spin lock synchronizes access to 'irq_handler_list_table' */ 111 spinlock_t irq_handler_list_table_lock; 112 113 /* Timer-related data. */ 114 struct list_head timer_handler_list; 115 struct workqueue_struct *timer_workqueue; 116 117 /* Use dal_mutex for any activity which is NOT syncronized by 118 * DRM mode setting locks. 119 * For example: amdgpu_dm_hpd_low_irq() calls into DAL *without* 120 * DRM mode setting locks being acquired. This is where dal_mutex 121 * is acquired before calling into DAL. */ 122 struct mutex dal_mutex; 123 124 struct backlight_device *backlight_dev; 125 126 const struct dc_link *backlight_link; 127 128 struct work_struct mst_hotplug_work; 129 130 struct mod_freesync *freesync_module; 131 132 /** 133 * Caches device atomic state for suspend/resume 134 */ 135 struct drm_atomic_state *cached_state; 136 }; 137 138 /* basic init/fini API */ 139 int amdgpu_dm_init(struct amdgpu_device *adev); 140 141 void amdgpu_dm_fini(struct amdgpu_device *adev); 142 143 void amdgpu_dm_destroy(void); 144 145 /* initializes drm_device display related structures, based on the information 146 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 147 * drm_encoder, drm_mode_config 148 * 149 * Returns 0 on success 150 */ 151 int amdgpu_dm_initialize_drm_device( 152 struct amdgpu_device *adev); 153 154 /* removes and deallocates the drm structures, created by the above function */ 155 void amdgpu_dm_destroy_drm_device( 156 struct amdgpu_display_manager *dm); 157 158 /* Locking/Mutex */ 159 bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm); 160 161 bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm); 162 163 /* Register "Backlight device" accessible by user-mode. */ 164 void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm); 165 166 extern const struct amdgpu_ip_block_version dm_ip_block; 167 168 void amdgpu_dm_update_connector_after_detect( 169 struct amdgpu_connector *aconnector); 170 171 struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( 172 struct drm_atomic_state *state, 173 struct drm_crtc *crtc, 174 bool from_state_var); 175 176 #endif /* __AMDGPU_DM_H__ */ 177