1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 struct amdgpu_bo; 61 struct dmub_srv; 62 63 struct common_irq_params { 64 struct amdgpu_device *adev; 65 enum dc_irq_source irq_src; 66 }; 67 68 /** 69 * struct irq_list_head - Linked-list for low context IRQ handlers. 70 * 71 * @head: The list_head within &struct handler_data 72 * @work: A work_struct containing the deferred handler work 73 */ 74 struct irq_list_head { 75 struct list_head head; 76 /* In case this interrupt needs post-processing, 'work' will be queued*/ 77 struct work_struct work; 78 }; 79 80 /** 81 * struct dm_compressor_info - Buffer info used by frame buffer compression 82 * @cpu_addr: MMIO cpu addr 83 * @bo_ptr: Pointer to the buffer object 84 * @gpu_addr: MMIO gpu addr 85 */ 86 struct dm_comressor_info { 87 void *cpu_addr; 88 struct amdgpu_bo *bo_ptr; 89 uint64_t gpu_addr; 90 }; 91 92 /** 93 * struct amdgpu_dm_backlight_caps - Information about backlight 94 * 95 * Describe the backlight support for ACPI or eDP AUX. 96 */ 97 struct amdgpu_dm_backlight_caps { 98 /** 99 * @ext_caps: Keep the data struct with all the information about the 100 * display support for HDR. 101 */ 102 union dpcd_sink_ext_caps *ext_caps; 103 /** 104 * @aux_min_input_signal: Min brightness value supported by the display 105 */ 106 u32 aux_min_input_signal; 107 /** 108 * @aux_max_input_signal: Max brightness value supported by the display 109 * in nits. 110 */ 111 u32 aux_max_input_signal; 112 /** 113 * @min_input_signal: minimum possible input in range 0-255. 114 */ 115 int min_input_signal; 116 /** 117 * @max_input_signal: maximum possible input in range 0-255. 118 */ 119 int max_input_signal; 120 /** 121 * @caps_valid: true if these values are from the ACPI interface. 122 */ 123 bool caps_valid; 124 /** 125 * @aux_support: Describes if the display supports AUX backlight. 126 */ 127 bool aux_support; 128 }; 129 130 /** 131 * struct amdgpu_display_manager - Central amdgpu display manager device 132 * 133 * @dc: Display Core control structure 134 * @adev: AMDGPU base driver structure 135 * @ddev: DRM base driver structure 136 * @display_indexes_num: Max number of display streams supported 137 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 138 * @backlight_dev: Backlight control device 139 * @backlight_link: Link on which to control backlight 140 * @backlight_caps: Capabilities of the backlight device 141 * @freesync_module: Module handling freesync calculations 142 * @hdcp_workqueue: AMDGPU content protection queue 143 * @fw_dmcu: Reference to DMCU firmware 144 * @dmcu_fw_version: Version of the DMCU firmware 145 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 146 * @cached_state: Caches device atomic state for suspend/resume 147 * @cached_dc_state: Cached state of content streams 148 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 149 */ 150 struct amdgpu_display_manager { 151 152 struct dc *dc; 153 154 /** 155 * @dmub_srv: 156 * 157 * DMUB service, used for controlling the DMUB on hardware 158 * that supports it. The pointer to the dmub_srv will be 159 * NULL on hardware that does not support it. 160 */ 161 struct dmub_srv *dmub_srv; 162 163 /** 164 * @dmub_fb_info: 165 * 166 * Framebuffer regions for the DMUB. 167 */ 168 struct dmub_srv_fb_info *dmub_fb_info; 169 170 /** 171 * @dmub_fw: 172 * 173 * DMUB firmware, required on hardware that has DMUB support. 174 */ 175 const struct firmware *dmub_fw; 176 177 /** 178 * @dmub_bo: 179 * 180 * Buffer object for the DMUB. 181 */ 182 struct amdgpu_bo *dmub_bo; 183 184 /** 185 * @dmub_bo_gpu_addr: 186 * 187 * GPU virtual address for the DMUB buffer object. 188 */ 189 u64 dmub_bo_gpu_addr; 190 191 /** 192 * @dmub_bo_cpu_addr: 193 * 194 * CPU address for the DMUB buffer object. 195 */ 196 void *dmub_bo_cpu_addr; 197 198 /** 199 * @dmcub_fw_version: 200 * 201 * DMCUB firmware version. 202 */ 203 uint32_t dmcub_fw_version; 204 205 /** 206 * @cgs_device: 207 * 208 * The Common Graphics Services device. It provides an interface for 209 * accessing registers. 210 */ 211 struct cgs_device *cgs_device; 212 213 struct amdgpu_device *adev; 214 struct drm_device *ddev; 215 u16 display_indexes_num; 216 217 /** 218 * @atomic_obj: 219 * 220 * In combination with &dm_atomic_state it helps manage 221 * global atomic state that doesn't map cleanly into existing 222 * drm resources, like &dc_context. 223 */ 224 struct drm_private_obj atomic_obj; 225 226 /** 227 * @dc_lock: 228 * 229 * Guards access to DC functions that can issue register write 230 * sequences. 231 */ 232 struct mutex dc_lock; 233 234 /** 235 * @audio_lock: 236 * 237 * Guards access to audio instance changes. 238 */ 239 struct mutex audio_lock; 240 241 /** 242 * @audio_component: 243 * 244 * Used to notify ELD changes to sound driver. 245 */ 246 struct drm_audio_component *audio_component; 247 248 /** 249 * @audio_registered: 250 * 251 * True if the audio component has been registered 252 * successfully, false otherwise. 253 */ 254 bool audio_registered; 255 256 /** 257 * @irq_handler_list_low_tab: 258 * 259 * Low priority IRQ handler table. 260 * 261 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 262 * source. Low priority IRQ handlers are deferred to a workqueue to be 263 * processed. Hence, they can sleep. 264 * 265 * Note that handlers are called in the same order as they were 266 * registered (FIFO). 267 */ 268 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 269 270 /** 271 * @irq_handler_list_high_tab: 272 * 273 * High priority IRQ handler table. 274 * 275 * It is a n*m table, same as &irq_handler_list_low_tab. However, 276 * handlers in this table are not deferred and are called immediately. 277 */ 278 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 279 280 /** 281 * @pflip_params: 282 * 283 * Page flip IRQ parameters, passed to registered handlers when 284 * triggered. 285 */ 286 struct common_irq_params 287 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 288 289 /** 290 * @vblank_params: 291 * 292 * Vertical blanking IRQ parameters, passed to registered handlers when 293 * triggered. 294 */ 295 struct common_irq_params 296 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 297 298 /** 299 * @vupdate_params: 300 * 301 * Vertical update IRQ parameters, passed to registered handlers when 302 * triggered. 303 */ 304 struct common_irq_params 305 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 306 307 spinlock_t irq_handler_list_table_lock; 308 309 struct backlight_device *backlight_dev; 310 311 const struct dc_link *backlight_link; 312 struct amdgpu_dm_backlight_caps backlight_caps; 313 314 struct mod_freesync *freesync_module; 315 #ifdef CONFIG_DRM_AMD_DC_HDCP 316 struct hdcp_workqueue *hdcp_workqueue; 317 #endif 318 319 struct drm_atomic_state *cached_state; 320 struct dc_state *cached_dc_state; 321 322 struct dm_comressor_info compressor; 323 324 const struct firmware *fw_dmcu; 325 uint32_t dmcu_fw_version; 326 /** 327 * @soc_bounding_box: 328 * 329 * gpu_info FW provided soc bounding box struct or 0 if not 330 * available in FW 331 */ 332 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 333 }; 334 335 struct amdgpu_dm_connector { 336 337 struct drm_connector base; 338 uint32_t connector_id; 339 340 /* we need to mind the EDID between detect 341 and get modes due to analog/digital/tvencoder */ 342 struct edid *edid; 343 344 /* shared with amdgpu */ 345 struct amdgpu_hpd hpd; 346 347 /* number of modes generated from EDID at 'dc_sink' */ 348 int num_modes; 349 350 /* The 'old' sink - before an HPD. 351 * The 'current' sink is in dc_link->sink. */ 352 struct dc_sink *dc_sink; 353 struct dc_link *dc_link; 354 struct dc_sink *dc_em_sink; 355 356 /* DM only */ 357 struct drm_dp_mst_topology_mgr mst_mgr; 358 struct amdgpu_dm_dp_aux dm_dp_aux; 359 struct drm_dp_mst_port *port; 360 struct amdgpu_dm_connector *mst_port; 361 struct amdgpu_encoder *mst_encoder; 362 struct drm_dp_aux *dsc_aux; 363 364 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 365 struct amdgpu_i2c_adapter *i2c; 366 367 /* Monitor range limits */ 368 int min_vfreq ; 369 int max_vfreq ; 370 int pixel_clock_mhz; 371 372 /* Audio instance - protected by audio_lock. */ 373 int audio_inst; 374 375 struct mutex hpd_lock; 376 377 bool fake_enable; 378 #ifdef CONFIG_DEBUG_FS 379 uint32_t debugfs_dpcd_address; 380 uint32_t debugfs_dpcd_size; 381 #endif 382 bool force_yuv420_output; 383 }; 384 385 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 386 387 extern const struct amdgpu_ip_block_version dm_ip_block; 388 389 struct amdgpu_framebuffer; 390 struct amdgpu_display_manager; 391 struct dc_validation_set; 392 struct dc_plane_state; 393 394 struct dm_plane_state { 395 struct drm_plane_state base; 396 struct dc_plane_state *dc_state; 397 }; 398 399 struct dm_crtc_state { 400 struct drm_crtc_state base; 401 struct dc_stream_state *stream; 402 403 bool cm_has_degamma; 404 bool cm_is_degamma_srgb; 405 406 int update_type; 407 int active_planes; 408 bool interrupts_enabled; 409 410 int crc_skip_count; 411 enum amdgpu_dm_pipe_crc_source crc_src; 412 413 bool freesync_timing_changed; 414 bool freesync_vrr_info_changed; 415 416 bool vrr_supported; 417 struct mod_freesync_config freesync_config; 418 struct mod_vrr_params vrr_params; 419 struct dc_info_packet vrr_infopacket; 420 421 int abm_level; 422 }; 423 424 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 425 426 struct dm_atomic_state { 427 struct drm_private_state base; 428 429 struct dc_state *context; 430 }; 431 432 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 433 434 struct dm_connector_state { 435 struct drm_connector_state base; 436 437 enum amdgpu_rmx_type scaling; 438 uint8_t underscan_vborder; 439 uint8_t underscan_hborder; 440 bool underscan_enable; 441 bool freesync_capable; 442 uint8_t abm_level; 443 int vcpi_slots; 444 uint64_t pbn; 445 }; 446 447 #define to_dm_connector_state(x)\ 448 container_of((x), struct dm_connector_state, base) 449 450 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 451 struct drm_connector_state * 452 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 453 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 454 struct drm_connector_state *state, 455 struct drm_property *property, 456 uint64_t val); 457 458 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 459 const struct drm_connector_state *state, 460 struct drm_property *property, 461 uint64_t *val); 462 463 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 464 465 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 466 struct amdgpu_dm_connector *aconnector, 467 int connector_type, 468 struct dc_link *link, 469 int link_index); 470 471 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 472 struct drm_display_mode *mode); 473 474 void dm_restore_drm_connector_state(struct drm_device *dev, 475 struct drm_connector *connector); 476 477 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 478 struct edid *edid); 479 480 #define MAX_COLOR_LUT_ENTRIES 4096 481 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 482 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 483 484 void amdgpu_dm_init_color_mod(void); 485 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 486 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 487 struct dc_plane_state *dc_plane_state); 488 489 void amdgpu_dm_update_connector_after_detect( 490 struct amdgpu_dm_connector *aconnector); 491 492 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 493 494 #endif /* __AMDGPU_DM_H__ */ 495