1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic.h> 31 32 /* 33 * This file contains the definition for amdgpu_display_manager 34 * and its API for amdgpu driver's use. 35 * This component provides all the display related functionality 36 * and this is the only component that calls DAL API. 37 * The API contained here intended for amdgpu driver use. 38 * The API that is called directly from KMS framework is located 39 * in amdgpu_dm_kms.h file 40 */ 41 42 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 43 /* 44 #include "include/amdgpu_dal_power_if.h" 45 #include "amdgpu_dm_irq.h" 46 */ 47 48 #include "irq_types.h" 49 #include "signal_types.h" 50 51 /* Forward declarations */ 52 struct amdgpu_device; 53 struct drm_device; 54 struct amdgpu_dm_irq_handler_data; 55 struct dc; 56 57 struct common_irq_params { 58 struct amdgpu_device *adev; 59 enum dc_irq_source irq_src; 60 }; 61 62 /** 63 * struct irq_list_head - Linked-list for low context IRQ handlers. 64 * 65 * @head: The list_head within &struct handler_data 66 * @work: A work_struct containing the deferred handler work 67 */ 68 struct irq_list_head { 69 struct list_head head; 70 /* In case this interrupt needs post-processing, 'work' will be queued*/ 71 struct work_struct work; 72 }; 73 74 /** 75 * struct dm_compressor_info - Buffer info used by frame buffer compression 76 * @cpu_addr: MMIO cpu addr 77 * @bo_ptr: Pointer to the buffer object 78 * @gpu_addr: MMIO gpu addr 79 */ 80 struct dm_comressor_info { 81 void *cpu_addr; 82 struct amdgpu_bo *bo_ptr; 83 uint64_t gpu_addr; 84 }; 85 86 /** 87 * struct amdgpu_display_manager - Central amdgpu display manager device 88 * 89 * @dc: Display Core control structure 90 * @adev: AMDGPU base driver structure 91 * @ddev: DRM base driver structure 92 * @display_indexes_num: Max number of display streams supported 93 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 94 * @backlight_dev: Backlight control device 95 * @cached_state: Caches device atomic state for suspend/resume 96 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 97 */ 98 struct amdgpu_display_manager { 99 100 struct dc *dc; 101 102 /** 103 * @cgs_device: 104 * 105 * The Common Graphics Services device. It provides an interface for 106 * accessing registers. 107 */ 108 struct cgs_device *cgs_device; 109 110 struct amdgpu_device *adev; 111 struct drm_device *ddev; 112 u16 display_indexes_num; 113 114 /** 115 * @irq_handler_list_low_tab: 116 * 117 * Low priority IRQ handler table. 118 * 119 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 120 * source. Low priority IRQ handlers are deferred to a workqueue to be 121 * processed. Hence, they can sleep. 122 * 123 * Note that handlers are called in the same order as they were 124 * registered (FIFO). 125 */ 126 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 127 128 /** 129 * @irq_handler_list_high_tab: 130 * 131 * High priority IRQ handler table. 132 * 133 * It is a n*m table, same as &irq_handler_list_low_tab. However, 134 * handlers in this table are not deferred and are called immediately. 135 */ 136 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 137 138 /** 139 * @pflip_params: 140 * 141 * Page flip IRQ parameters, passed to registered handlers when 142 * triggered. 143 */ 144 struct common_irq_params 145 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 146 147 /** 148 * @vblank_params: 149 * 150 * Vertical blanking IRQ parameters, passed to registered handlers when 151 * triggered. 152 */ 153 struct common_irq_params 154 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 155 156 spinlock_t irq_handler_list_table_lock; 157 158 struct backlight_device *backlight_dev; 159 160 const struct dc_link *backlight_link; 161 162 struct mod_freesync *freesync_module; 163 164 struct drm_atomic_state *cached_state; 165 166 struct dm_comressor_info compressor; 167 168 const struct firmware *fw_dmcu; 169 uint32_t dmcu_fw_version; 170 }; 171 172 struct amdgpu_dm_connector { 173 174 struct drm_connector base; 175 uint32_t connector_id; 176 177 /* we need to mind the EDID between detect 178 and get modes due to analog/digital/tvencoder */ 179 struct edid *edid; 180 181 /* shared with amdgpu */ 182 struct amdgpu_hpd hpd; 183 184 /* number of modes generated from EDID at 'dc_sink' */ 185 int num_modes; 186 187 /* The 'old' sink - before an HPD. 188 * The 'current' sink is in dc_link->sink. */ 189 struct dc_sink *dc_sink; 190 struct dc_link *dc_link; 191 struct dc_sink *dc_em_sink; 192 193 /* DM only */ 194 struct drm_dp_mst_topology_mgr mst_mgr; 195 struct amdgpu_dm_dp_aux dm_dp_aux; 196 struct drm_dp_mst_port *port; 197 struct amdgpu_dm_connector *mst_port; 198 struct amdgpu_encoder *mst_encoder; 199 200 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 201 struct amdgpu_i2c_adapter *i2c; 202 203 /* Monitor range limits */ 204 int min_vfreq ; 205 int max_vfreq ; 206 int pixel_clock_mhz; 207 208 struct mutex hpd_lock; 209 210 bool fake_enable; 211 }; 212 213 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 214 215 extern const struct amdgpu_ip_block_version dm_ip_block; 216 217 struct amdgpu_framebuffer; 218 struct amdgpu_display_manager; 219 struct dc_validation_set; 220 struct dc_plane_state; 221 222 struct dm_plane_state { 223 struct drm_plane_state base; 224 struct dc_plane_state *dc_state; 225 }; 226 227 struct dm_crtc_state { 228 struct drm_crtc_state base; 229 struct dc_stream_state *stream; 230 231 int crc_skip_count; 232 bool crc_enabled; 233 234 bool freesync_enabled; 235 struct dc_crtc_timing_adjust adjust; 236 struct dc_info_packet vrr_infopacket; 237 }; 238 239 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 240 241 struct dm_atomic_state { 242 struct drm_atomic_state base; 243 244 struct dc_state *context; 245 }; 246 247 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 248 249 struct dm_connector_state { 250 struct drm_connector_state base; 251 252 enum amdgpu_rmx_type scaling; 253 uint8_t underscan_vborder; 254 uint8_t underscan_hborder; 255 bool underscan_enable; 256 bool freesync_enable; 257 bool freesync_capable; 258 }; 259 260 #define to_dm_connector_state(x)\ 261 container_of((x), struct dm_connector_state, base) 262 263 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 264 struct drm_connector_state * 265 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 266 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 267 struct drm_connector_state *state, 268 struct drm_property *property, 269 uint64_t val); 270 271 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 272 const struct drm_connector_state *state, 273 struct drm_property *property, 274 uint64_t *val); 275 276 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 277 278 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 279 struct amdgpu_dm_connector *aconnector, 280 int connector_type, 281 struct dc_link *link, 282 int link_index); 283 284 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 285 struct drm_display_mode *mode); 286 287 void dm_restore_drm_connector_state(struct drm_device *dev, 288 struct drm_connector *connector); 289 290 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 291 struct edid *edid); 292 293 /* amdgpu_dm_crc.c */ 294 #ifdef CONFIG_DEBUG_FS 295 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); 296 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, 297 const char *src_name, 298 size_t *values_cnt); 299 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 300 #else 301 #define amdgpu_dm_crtc_set_crc_source NULL 302 #define amdgpu_dm_crtc_verify_crc_source NULL 303 #define amdgpu_dm_crtc_handle_crc_irq(x) 304 #endif 305 306 #define MAX_COLOR_LUT_ENTRIES 4096 307 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 308 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 309 310 void amdgpu_dm_init_color_mod(void); 311 int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, 312 struct dc_plane_state *dc_plane_state); 313 void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); 314 int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); 315 316 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 317 318 #endif /* __AMDGPU_DM_H__ */ 319