1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 61 struct common_irq_params { 62 struct amdgpu_device *adev; 63 enum dc_irq_source irq_src; 64 }; 65 66 /** 67 * struct irq_list_head - Linked-list for low context IRQ handlers. 68 * 69 * @head: The list_head within &struct handler_data 70 * @work: A work_struct containing the deferred handler work 71 */ 72 struct irq_list_head { 73 struct list_head head; 74 /* In case this interrupt needs post-processing, 'work' will be queued*/ 75 struct work_struct work; 76 }; 77 78 /** 79 * struct dm_compressor_info - Buffer info used by frame buffer compression 80 * @cpu_addr: MMIO cpu addr 81 * @bo_ptr: Pointer to the buffer object 82 * @gpu_addr: MMIO gpu addr 83 */ 84 struct dm_comressor_info { 85 void *cpu_addr; 86 struct amdgpu_bo *bo_ptr; 87 uint64_t gpu_addr; 88 }; 89 90 /** 91 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 92 * @min_input_signal: minimum possible input in range 0-255 93 * @max_input_signal: maximum possible input in range 0-255 94 * @caps_valid: true if these values are from the ACPI interface 95 */ 96 struct amdgpu_dm_backlight_caps { 97 int min_input_signal; 98 int max_input_signal; 99 bool caps_valid; 100 }; 101 102 /** 103 * struct amdgpu_display_manager - Central amdgpu display manager device 104 * 105 * @dc: Display Core control structure 106 * @adev: AMDGPU base driver structure 107 * @ddev: DRM base driver structure 108 * @display_indexes_num: Max number of display streams supported 109 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 110 * @backlight_dev: Backlight control device 111 * @cached_state: Caches device atomic state for suspend/resume 112 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 113 */ 114 struct amdgpu_display_manager { 115 116 struct dc *dc; 117 118 /** 119 * @cgs_device: 120 * 121 * The Common Graphics Services device. It provides an interface for 122 * accessing registers. 123 */ 124 struct cgs_device *cgs_device; 125 126 struct amdgpu_device *adev; 127 struct drm_device *ddev; 128 u16 display_indexes_num; 129 130 /** 131 * @atomic_obj 132 * 133 * In combination with &dm_atomic_state it helps manage 134 * global atomic state that doesn't map cleanly into existing 135 * drm resources, like &dc_context. 136 */ 137 struct drm_private_obj atomic_obj; 138 139 /** 140 * @dc_lock: 141 * 142 * Guards access to DC functions that can issue register write 143 * sequences. 144 */ 145 struct mutex dc_lock; 146 147 /** 148 * @audio_lock: 149 * 150 * Guards access to audio instance changes. 151 */ 152 struct mutex audio_lock; 153 154 /** 155 * @audio_component: 156 * 157 * Used to notify ELD changes to sound driver. 158 */ 159 struct drm_audio_component *audio_component; 160 161 /** 162 * @audio_registered: 163 * 164 * True if the audio component has been registered 165 * successfully, false otherwise. 166 */ 167 bool audio_registered; 168 169 /** 170 * @irq_handler_list_low_tab: 171 * 172 * Low priority IRQ handler table. 173 * 174 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 175 * source. Low priority IRQ handlers are deferred to a workqueue to be 176 * processed. Hence, they can sleep. 177 * 178 * Note that handlers are called in the same order as they were 179 * registered (FIFO). 180 */ 181 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 182 183 /** 184 * @irq_handler_list_high_tab: 185 * 186 * High priority IRQ handler table. 187 * 188 * It is a n*m table, same as &irq_handler_list_low_tab. However, 189 * handlers in this table are not deferred and are called immediately. 190 */ 191 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 192 193 /** 194 * @pflip_params: 195 * 196 * Page flip IRQ parameters, passed to registered handlers when 197 * triggered. 198 */ 199 struct common_irq_params 200 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 201 202 /** 203 * @vblank_params: 204 * 205 * Vertical blanking IRQ parameters, passed to registered handlers when 206 * triggered. 207 */ 208 struct common_irq_params 209 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 210 211 /** 212 * @vupdate_params: 213 * 214 * Vertical update IRQ parameters, passed to registered handlers when 215 * triggered. 216 */ 217 struct common_irq_params 218 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 219 220 spinlock_t irq_handler_list_table_lock; 221 222 struct backlight_device *backlight_dev; 223 224 const struct dc_link *backlight_link; 225 struct amdgpu_dm_backlight_caps backlight_caps; 226 227 struct mod_freesync *freesync_module; 228 229 struct drm_atomic_state *cached_state; 230 231 struct dm_comressor_info compressor; 232 233 const struct firmware *fw_dmcu; 234 uint32_t dmcu_fw_version; 235 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 236 /** 237 * gpu_info FW provided soc bounding box struct or 0 if not 238 * available in FW 239 */ 240 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 241 #endif 242 }; 243 244 struct amdgpu_dm_connector { 245 246 struct drm_connector base; 247 uint32_t connector_id; 248 249 /* we need to mind the EDID between detect 250 and get modes due to analog/digital/tvencoder */ 251 struct edid *edid; 252 253 /* shared with amdgpu */ 254 struct amdgpu_hpd hpd; 255 256 /* number of modes generated from EDID at 'dc_sink' */ 257 int num_modes; 258 259 /* The 'old' sink - before an HPD. 260 * The 'current' sink is in dc_link->sink. */ 261 struct dc_sink *dc_sink; 262 struct dc_link *dc_link; 263 struct dc_sink *dc_em_sink; 264 265 /* DM only */ 266 struct drm_dp_mst_topology_mgr mst_mgr; 267 struct amdgpu_dm_dp_aux dm_dp_aux; 268 struct drm_dp_mst_port *port; 269 struct amdgpu_dm_connector *mst_port; 270 struct amdgpu_encoder *mst_encoder; 271 272 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 273 struct amdgpu_i2c_adapter *i2c; 274 275 /* Monitor range limits */ 276 int min_vfreq ; 277 int max_vfreq ; 278 int pixel_clock_mhz; 279 280 /* Audio instance - protected by audio_lock. */ 281 int audio_inst; 282 283 struct mutex hpd_lock; 284 285 bool fake_enable; 286 #ifdef CONFIG_DEBUG_FS 287 uint32_t debugfs_dpcd_address; 288 uint32_t debugfs_dpcd_size; 289 #endif 290 }; 291 292 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 293 294 extern const struct amdgpu_ip_block_version dm_ip_block; 295 296 struct amdgpu_framebuffer; 297 struct amdgpu_display_manager; 298 struct dc_validation_set; 299 struct dc_plane_state; 300 301 struct dm_plane_state { 302 struct drm_plane_state base; 303 struct dc_plane_state *dc_state; 304 }; 305 306 struct dm_crtc_state { 307 struct drm_crtc_state base; 308 struct dc_stream_state *stream; 309 310 bool cm_has_degamma; 311 bool cm_is_degamma_srgb; 312 313 int update_type; 314 int active_planes; 315 bool interrupts_enabled; 316 317 int crc_skip_count; 318 enum amdgpu_dm_pipe_crc_source crc_src; 319 320 bool freesync_timing_changed; 321 bool freesync_vrr_info_changed; 322 323 bool vrr_supported; 324 struct mod_freesync_config freesync_config; 325 struct mod_vrr_params vrr_params; 326 struct dc_info_packet vrr_infopacket; 327 328 int abm_level; 329 }; 330 331 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 332 333 struct dm_atomic_state { 334 struct drm_private_state base; 335 336 struct dc_state *context; 337 }; 338 339 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 340 341 struct dm_connector_state { 342 struct drm_connector_state base; 343 344 enum amdgpu_rmx_type scaling; 345 uint8_t underscan_vborder; 346 uint8_t underscan_hborder; 347 bool underscan_enable; 348 bool freesync_capable; 349 uint8_t abm_level; 350 }; 351 352 #define to_dm_connector_state(x)\ 353 container_of((x), struct dm_connector_state, base) 354 355 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 356 struct drm_connector_state * 357 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 358 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 359 struct drm_connector_state *state, 360 struct drm_property *property, 361 uint64_t val); 362 363 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 364 const struct drm_connector_state *state, 365 struct drm_property *property, 366 uint64_t *val); 367 368 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 369 370 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 371 struct amdgpu_dm_connector *aconnector, 372 int connector_type, 373 struct dc_link *link, 374 int link_index); 375 376 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 377 struct drm_display_mode *mode); 378 379 void dm_restore_drm_connector_state(struct drm_device *dev, 380 struct drm_connector *connector); 381 382 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 383 struct edid *edid); 384 385 #define MAX_COLOR_LUT_ENTRIES 4096 386 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 387 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 388 389 void amdgpu_dm_init_color_mod(void); 390 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 391 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 392 struct dc_plane_state *dc_plane_state); 393 394 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 395 396 #endif /* __AMDGPU_DM_H__ */ 397