1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct dc; 62 struct amdgpu_bo; 63 struct dmub_srv; 64 struct dc_plane_state; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 }; 70 71 /** 72 * struct dm_compressor_info - Buffer info used by frame buffer compression 73 * @cpu_addr: MMIO cpu addr 74 * @bo_ptr: Pointer to the buffer object 75 * @gpu_addr: MMIO gpu addr 76 */ 77 struct dm_compressor_info { 78 void *cpu_addr; 79 struct amdgpu_bo *bo_ptr; 80 uint64_t gpu_addr; 81 }; 82 83 /** 84 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 85 * @mall_work: work for mall stutter 86 * @dm: amdgpu display manager device 87 * @otg_inst: otg instance of which vblank is being set 88 * @enable: true if enable vblank 89 */ 90 struct vblank_workqueue { 91 struct work_struct mall_work; 92 struct amdgpu_display_manager *dm; 93 int otg_inst; 94 bool enable; 95 }; 96 97 /** 98 * struct amdgpu_dm_backlight_caps - Information about backlight 99 * 100 * Describe the backlight support for ACPI or eDP AUX. 101 */ 102 struct amdgpu_dm_backlight_caps { 103 /** 104 * @ext_caps: Keep the data struct with all the information about the 105 * display support for HDR. 106 */ 107 union dpcd_sink_ext_caps *ext_caps; 108 /** 109 * @aux_min_input_signal: Min brightness value supported by the display 110 */ 111 u32 aux_min_input_signal; 112 /** 113 * @aux_max_input_signal: Max brightness value supported by the display 114 * in nits. 115 */ 116 u32 aux_max_input_signal; 117 /** 118 * @min_input_signal: minimum possible input in range 0-255. 119 */ 120 int min_input_signal; 121 /** 122 * @max_input_signal: maximum possible input in range 0-255. 123 */ 124 int max_input_signal; 125 /** 126 * @caps_valid: true if these values are from the ACPI interface. 127 */ 128 bool caps_valid; 129 /** 130 * @aux_support: Describes if the display supports AUX backlight. 131 */ 132 bool aux_support; 133 }; 134 135 /** 136 * struct dal_allocation - Tracks mapped FB memory for SMU communication 137 */ 138 struct dal_allocation { 139 struct list_head list; 140 struct amdgpu_bo *bo; 141 void *cpu_ptr; 142 u64 gpu_addr; 143 }; 144 145 /** 146 * struct amdgpu_display_manager - Central amdgpu display manager device 147 * 148 * @dc: Display Core control structure 149 * @adev: AMDGPU base driver structure 150 * @ddev: DRM base driver structure 151 * @display_indexes_num: Max number of display streams supported 152 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 153 * @backlight_dev: Backlight control device 154 * @backlight_link: Link on which to control backlight 155 * @backlight_caps: Capabilities of the backlight device 156 * @freesync_module: Module handling freesync calculations 157 * @hdcp_workqueue: AMDGPU content protection queue 158 * @fw_dmcu: Reference to DMCU firmware 159 * @dmcu_fw_version: Version of the DMCU firmware 160 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 161 * @cached_state: Caches device atomic state for suspend/resume 162 * @cached_dc_state: Cached state of content streams 163 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 164 * @force_timing_sync: set via debugfs. When set, indicates that all connected 165 * displays will be forced to synchronize. 166 */ 167 struct amdgpu_display_manager { 168 169 struct dc *dc; 170 171 /** 172 * @dmub_srv: 173 * 174 * DMUB service, used for controlling the DMUB on hardware 175 * that supports it. The pointer to the dmub_srv will be 176 * NULL on hardware that does not support it. 177 */ 178 struct dmub_srv *dmub_srv; 179 180 /** 181 * @dmub_fb_info: 182 * 183 * Framebuffer regions for the DMUB. 184 */ 185 struct dmub_srv_fb_info *dmub_fb_info; 186 187 /** 188 * @dmub_fw: 189 * 190 * DMUB firmware, required on hardware that has DMUB support. 191 */ 192 const struct firmware *dmub_fw; 193 194 /** 195 * @dmub_bo: 196 * 197 * Buffer object for the DMUB. 198 */ 199 struct amdgpu_bo *dmub_bo; 200 201 /** 202 * @dmub_bo_gpu_addr: 203 * 204 * GPU virtual address for the DMUB buffer object. 205 */ 206 u64 dmub_bo_gpu_addr; 207 208 /** 209 * @dmub_bo_cpu_addr: 210 * 211 * CPU address for the DMUB buffer object. 212 */ 213 void *dmub_bo_cpu_addr; 214 215 /** 216 * @dmcub_fw_version: 217 * 218 * DMCUB firmware version. 219 */ 220 uint32_t dmcub_fw_version; 221 222 /** 223 * @cgs_device: 224 * 225 * The Common Graphics Services device. It provides an interface for 226 * accessing registers. 227 */ 228 struct cgs_device *cgs_device; 229 230 struct amdgpu_device *adev; 231 struct drm_device *ddev; 232 u16 display_indexes_num; 233 234 /** 235 * @atomic_obj: 236 * 237 * In combination with &dm_atomic_state it helps manage 238 * global atomic state that doesn't map cleanly into existing 239 * drm resources, like &dc_context. 240 */ 241 struct drm_private_obj atomic_obj; 242 243 /** 244 * @dc_lock: 245 * 246 * Guards access to DC functions that can issue register write 247 * sequences. 248 */ 249 struct mutex dc_lock; 250 251 /** 252 * @audio_lock: 253 * 254 * Guards access to audio instance changes. 255 */ 256 struct mutex audio_lock; 257 258 #if defined(CONFIG_DRM_AMD_DC_DCN) 259 /** 260 * @vblank_lock: 261 * 262 * Guards access to deferred vblank work state. 263 */ 264 spinlock_t vblank_lock; 265 #endif 266 267 /** 268 * @audio_component: 269 * 270 * Used to notify ELD changes to sound driver. 271 */ 272 struct drm_audio_component *audio_component; 273 274 /** 275 * @audio_registered: 276 * 277 * True if the audio component has been registered 278 * successfully, false otherwise. 279 */ 280 bool audio_registered; 281 282 /** 283 * @irq_handler_list_low_tab: 284 * 285 * Low priority IRQ handler table. 286 * 287 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 288 * source. Low priority IRQ handlers are deferred to a workqueue to be 289 * processed. Hence, they can sleep. 290 * 291 * Note that handlers are called in the same order as they were 292 * registered (FIFO). 293 */ 294 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 295 296 /** 297 * @irq_handler_list_high_tab: 298 * 299 * High priority IRQ handler table. 300 * 301 * It is a n*m table, same as &irq_handler_list_low_tab. However, 302 * handlers in this table are not deferred and are called immediately. 303 */ 304 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 305 306 /** 307 * @pflip_params: 308 * 309 * Page flip IRQ parameters, passed to registered handlers when 310 * triggered. 311 */ 312 struct common_irq_params 313 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 314 315 /** 316 * @vblank_params: 317 * 318 * Vertical blanking IRQ parameters, passed to registered handlers when 319 * triggered. 320 */ 321 struct common_irq_params 322 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 323 324 /** 325 * @vline0_params: 326 * 327 * OTG vertical interrupt0 IRQ parameters, passed to registered 328 * handlers when triggered. 329 */ 330 struct common_irq_params 331 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 332 333 /** 334 * @vupdate_params: 335 * 336 * Vertical update IRQ parameters, passed to registered handlers when 337 * triggered. 338 */ 339 struct common_irq_params 340 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 341 342 spinlock_t irq_handler_list_table_lock; 343 344 struct backlight_device *backlight_dev; 345 346 const struct dc_link *backlight_link; 347 struct amdgpu_dm_backlight_caps backlight_caps; 348 349 struct mod_freesync *freesync_module; 350 #ifdef CONFIG_DRM_AMD_DC_HDCP 351 struct hdcp_workqueue *hdcp_workqueue; 352 #endif 353 354 #if defined(CONFIG_DRM_AMD_DC_DCN) 355 /** 356 * @vblank_workqueue: 357 * 358 * amdgpu workqueue during vblank 359 */ 360 struct vblank_workqueue *vblank_workqueue; 361 #endif 362 363 struct drm_atomic_state *cached_state; 364 struct dc_state *cached_dc_state; 365 366 struct dm_compressor_info compressor; 367 368 const struct firmware *fw_dmcu; 369 uint32_t dmcu_fw_version; 370 /** 371 * @soc_bounding_box: 372 * 373 * gpu_info FW provided soc bounding box struct or 0 if not 374 * available in FW 375 */ 376 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 377 378 #if defined(CONFIG_DRM_AMD_DC_DCN) 379 /** 380 * @active_vblank_irq_count: 381 * 382 * number of currently active vblank irqs 383 */ 384 uint32_t active_vblank_irq_count; 385 #endif 386 387 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 388 struct crc_rd_work *crc_rd_wrk; 389 #endif 390 391 /** 392 * @mst_encoders: 393 * 394 * fake encoders used for DP MST. 395 */ 396 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 397 bool force_timing_sync; 398 bool dmcub_trace_event_en; 399 /** 400 * @da_list: 401 * 402 * DAL fb memory allocation list, for communication with SMU. 403 */ 404 struct list_head da_list; 405 }; 406 407 enum dsc_clock_force_state { 408 DSC_CLK_FORCE_DEFAULT = 0, 409 DSC_CLK_FORCE_ENABLE, 410 DSC_CLK_FORCE_DISABLE, 411 }; 412 413 struct dsc_preferred_settings { 414 enum dsc_clock_force_state dsc_force_enable; 415 uint32_t dsc_num_slices_v; 416 uint32_t dsc_num_slices_h; 417 uint32_t dsc_bits_per_pixel; 418 }; 419 420 struct amdgpu_dm_connector { 421 422 struct drm_connector base; 423 uint32_t connector_id; 424 425 /* we need to mind the EDID between detect 426 and get modes due to analog/digital/tvencoder */ 427 struct edid *edid; 428 429 /* shared with amdgpu */ 430 struct amdgpu_hpd hpd; 431 432 /* number of modes generated from EDID at 'dc_sink' */ 433 int num_modes; 434 435 /* The 'old' sink - before an HPD. 436 * The 'current' sink is in dc_link->sink. */ 437 struct dc_sink *dc_sink; 438 struct dc_link *dc_link; 439 struct dc_sink *dc_em_sink; 440 441 /* DM only */ 442 struct drm_dp_mst_topology_mgr mst_mgr; 443 struct amdgpu_dm_dp_aux dm_dp_aux; 444 struct drm_dp_mst_port *port; 445 struct amdgpu_dm_connector *mst_port; 446 struct drm_dp_aux *dsc_aux; 447 448 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 449 struct amdgpu_i2c_adapter *i2c; 450 451 /* Monitor range limits */ 452 int min_vfreq ; 453 int max_vfreq ; 454 int pixel_clock_mhz; 455 456 /* Audio instance - protected by audio_lock. */ 457 int audio_inst; 458 459 struct mutex hpd_lock; 460 461 bool fake_enable; 462 #ifdef CONFIG_DEBUG_FS 463 uint32_t debugfs_dpcd_address; 464 uint32_t debugfs_dpcd_size; 465 #endif 466 bool force_yuv420_output; 467 struct dsc_preferred_settings dsc_settings; 468 /* Cached display modes */ 469 struct drm_display_mode freesync_vid_base; 470 }; 471 472 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 473 474 extern const struct amdgpu_ip_block_version dm_ip_block; 475 476 struct dm_plane_state { 477 struct drm_plane_state base; 478 struct dc_plane_state *dc_state; 479 }; 480 481 struct dm_crtc_state { 482 struct drm_crtc_state base; 483 struct dc_stream_state *stream; 484 485 bool cm_has_degamma; 486 bool cm_is_degamma_srgb; 487 488 int update_type; 489 int active_planes; 490 491 int crc_skip_count; 492 493 bool freesync_timing_changed; 494 bool freesync_vrr_info_changed; 495 496 bool dsc_force_changed; 497 bool vrr_supported; 498 struct mod_freesync_config freesync_config; 499 struct dc_info_packet vrr_infopacket; 500 501 int abm_level; 502 }; 503 504 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 505 506 struct dm_atomic_state { 507 struct drm_private_state base; 508 509 struct dc_state *context; 510 }; 511 512 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 513 514 struct dm_connector_state { 515 struct drm_connector_state base; 516 517 enum amdgpu_rmx_type scaling; 518 uint8_t underscan_vborder; 519 uint8_t underscan_hborder; 520 bool underscan_enable; 521 bool freesync_capable; 522 #ifdef CONFIG_DRM_AMD_DC_HDCP 523 bool update_hdcp; 524 #endif 525 uint8_t abm_level; 526 int vcpi_slots; 527 uint64_t pbn; 528 }; 529 530 struct amdgpu_hdmi_vsdb_info { 531 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 532 bool freesync_supported; /* FreeSync Supported */ 533 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 534 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 535 }; 536 537 538 #define to_dm_connector_state(x)\ 539 container_of((x), struct dm_connector_state, base) 540 541 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 542 struct drm_connector_state * 543 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 544 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 545 struct drm_connector_state *state, 546 struct drm_property *property, 547 uint64_t val); 548 549 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 550 const struct drm_connector_state *state, 551 struct drm_property *property, 552 uint64_t *val); 553 554 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 555 556 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 557 struct amdgpu_dm_connector *aconnector, 558 int connector_type, 559 struct dc_link *link, 560 int link_index); 561 562 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 563 struct drm_display_mode *mode); 564 565 void dm_restore_drm_connector_state(struct drm_device *dev, 566 struct drm_connector *connector); 567 568 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 569 struct edid *edid); 570 571 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 572 573 #define MAX_COLOR_LUT_ENTRIES 4096 574 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 575 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 576 577 void amdgpu_dm_init_color_mod(void); 578 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 579 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 580 struct dc_plane_state *dc_plane_state); 581 582 void amdgpu_dm_update_connector_after_detect( 583 struct amdgpu_dm_connector *aconnector); 584 585 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 586 587 #endif /* __AMDGPU_DM_H__ */ 588