1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct dc; 62 struct amdgpu_bo; 63 struct dmub_srv; 64 struct dc_plane_state; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 }; 70 71 /** 72 * struct irq_list_head - Linked-list for low context IRQ handlers. 73 * 74 * @head: The list_head within &struct handler_data 75 * @work: A work_struct containing the deferred handler work 76 */ 77 struct irq_list_head { 78 struct list_head head; 79 /* In case this interrupt needs post-processing, 'work' will be queued*/ 80 struct work_struct work; 81 }; 82 83 /** 84 * struct dm_compressor_info - Buffer info used by frame buffer compression 85 * @cpu_addr: MMIO cpu addr 86 * @bo_ptr: Pointer to the buffer object 87 * @gpu_addr: MMIO gpu addr 88 */ 89 struct dm_compressor_info { 90 void *cpu_addr; 91 struct amdgpu_bo *bo_ptr; 92 uint64_t gpu_addr; 93 }; 94 95 /** 96 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 97 * @mall_work: work for mall stutter 98 * @dm: amdgpu display manager device 99 * @otg_inst: otg instance of which vblank is being set 100 * @enable: true if enable vblank 101 */ 102 struct vblank_workqueue { 103 struct work_struct mall_work; 104 struct amdgpu_display_manager *dm; 105 int otg_inst; 106 bool enable; 107 }; 108 109 /** 110 * struct amdgpu_dm_backlight_caps - Information about backlight 111 * 112 * Describe the backlight support for ACPI or eDP AUX. 113 */ 114 struct amdgpu_dm_backlight_caps { 115 /** 116 * @ext_caps: Keep the data struct with all the information about the 117 * display support for HDR. 118 */ 119 union dpcd_sink_ext_caps *ext_caps; 120 /** 121 * @aux_min_input_signal: Min brightness value supported by the display 122 */ 123 u32 aux_min_input_signal; 124 /** 125 * @aux_max_input_signal: Max brightness value supported by the display 126 * in nits. 127 */ 128 u32 aux_max_input_signal; 129 /** 130 * @min_input_signal: minimum possible input in range 0-255. 131 */ 132 int min_input_signal; 133 /** 134 * @max_input_signal: maximum possible input in range 0-255. 135 */ 136 int max_input_signal; 137 /** 138 * @caps_valid: true if these values are from the ACPI interface. 139 */ 140 bool caps_valid; 141 /** 142 * @aux_support: Describes if the display supports AUX backlight. 143 */ 144 bool aux_support; 145 }; 146 147 /** 148 * struct amdgpu_display_manager - Central amdgpu display manager device 149 * 150 * @dc: Display Core control structure 151 * @adev: AMDGPU base driver structure 152 * @ddev: DRM base driver structure 153 * @display_indexes_num: Max number of display streams supported 154 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 155 * @backlight_dev: Backlight control device 156 * @backlight_link: Link on which to control backlight 157 * @backlight_caps: Capabilities of the backlight device 158 * @freesync_module: Module handling freesync calculations 159 * @hdcp_workqueue: AMDGPU content protection queue 160 * @fw_dmcu: Reference to DMCU firmware 161 * @dmcu_fw_version: Version of the DMCU firmware 162 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 163 * @cached_state: Caches device atomic state for suspend/resume 164 * @cached_dc_state: Cached state of content streams 165 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 166 * @force_timing_sync: set via debugfs. When set, indicates that all connected 167 * displays will be forced to synchronize. 168 */ 169 struct amdgpu_display_manager { 170 171 struct dc *dc; 172 173 /** 174 * @dmub_srv: 175 * 176 * DMUB service, used for controlling the DMUB on hardware 177 * that supports it. The pointer to the dmub_srv will be 178 * NULL on hardware that does not support it. 179 */ 180 struct dmub_srv *dmub_srv; 181 182 /** 183 * @dmub_fb_info: 184 * 185 * Framebuffer regions for the DMUB. 186 */ 187 struct dmub_srv_fb_info *dmub_fb_info; 188 189 /** 190 * @dmub_fw: 191 * 192 * DMUB firmware, required on hardware that has DMUB support. 193 */ 194 const struct firmware *dmub_fw; 195 196 /** 197 * @dmub_bo: 198 * 199 * Buffer object for the DMUB. 200 */ 201 struct amdgpu_bo *dmub_bo; 202 203 /** 204 * @dmub_bo_gpu_addr: 205 * 206 * GPU virtual address for the DMUB buffer object. 207 */ 208 u64 dmub_bo_gpu_addr; 209 210 /** 211 * @dmub_bo_cpu_addr: 212 * 213 * CPU address for the DMUB buffer object. 214 */ 215 void *dmub_bo_cpu_addr; 216 217 /** 218 * @dmcub_fw_version: 219 * 220 * DMCUB firmware version. 221 */ 222 uint32_t dmcub_fw_version; 223 224 /** 225 * @cgs_device: 226 * 227 * The Common Graphics Services device. It provides an interface for 228 * accessing registers. 229 */ 230 struct cgs_device *cgs_device; 231 232 struct amdgpu_device *adev; 233 struct drm_device *ddev; 234 u16 display_indexes_num; 235 236 /** 237 * @atomic_obj: 238 * 239 * In combination with &dm_atomic_state it helps manage 240 * global atomic state that doesn't map cleanly into existing 241 * drm resources, like &dc_context. 242 */ 243 struct drm_private_obj atomic_obj; 244 245 /** 246 * @dc_lock: 247 * 248 * Guards access to DC functions that can issue register write 249 * sequences. 250 */ 251 struct mutex dc_lock; 252 253 /** 254 * @audio_lock: 255 * 256 * Guards access to audio instance changes. 257 */ 258 struct mutex audio_lock; 259 260 /** 261 * @vblank_work_lock: 262 * 263 * Guards access to deferred vblank work state. 264 */ 265 #if defined(CONFIG_DRM_AMD_DC_DCN) 266 spinlock_t vblank_lock; 267 #endif 268 269 /** 270 * @audio_component: 271 * 272 * Used to notify ELD changes to sound driver. 273 */ 274 struct drm_audio_component *audio_component; 275 276 /** 277 * @audio_registered: 278 * 279 * True if the audio component has been registered 280 * successfully, false otherwise. 281 */ 282 bool audio_registered; 283 284 /** 285 * @irq_handler_list_low_tab: 286 * 287 * Low priority IRQ handler table. 288 * 289 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 290 * source. Low priority IRQ handlers are deferred to a workqueue to be 291 * processed. Hence, they can sleep. 292 * 293 * Note that handlers are called in the same order as they were 294 * registered (FIFO). 295 */ 296 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 297 298 /** 299 * @irq_handler_list_high_tab: 300 * 301 * High priority IRQ handler table. 302 * 303 * It is a n*m table, same as &irq_handler_list_low_tab. However, 304 * handlers in this table are not deferred and are called immediately. 305 */ 306 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 307 308 /** 309 * @pflip_params: 310 * 311 * Page flip IRQ parameters, passed to registered handlers when 312 * triggered. 313 */ 314 struct common_irq_params 315 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 316 317 /** 318 * @vblank_params: 319 * 320 * Vertical blanking IRQ parameters, passed to registered handlers when 321 * triggered. 322 */ 323 struct common_irq_params 324 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 325 326 /** 327 * @vupdate_params: 328 * 329 * Vertical update IRQ parameters, passed to registered handlers when 330 * triggered. 331 */ 332 struct common_irq_params 333 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 334 335 spinlock_t irq_handler_list_table_lock; 336 337 struct backlight_device *backlight_dev; 338 339 const struct dc_link *backlight_link; 340 struct amdgpu_dm_backlight_caps backlight_caps; 341 342 struct mod_freesync *freesync_module; 343 #ifdef CONFIG_DRM_AMD_DC_HDCP 344 struct hdcp_workqueue *hdcp_workqueue; 345 #endif 346 347 #if defined(CONFIG_DRM_AMD_DC_DCN) 348 struct vblank_workqueue *vblank_workqueue; 349 #endif 350 351 struct drm_atomic_state *cached_state; 352 struct dc_state *cached_dc_state; 353 354 struct dm_compressor_info compressor; 355 356 const struct firmware *fw_dmcu; 357 uint32_t dmcu_fw_version; 358 /** 359 * @soc_bounding_box: 360 * 361 * gpu_info FW provided soc bounding box struct or 0 if not 362 * available in FW 363 */ 364 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 365 366 /** 367 * @active_vblank_irq_count: 368 * 369 * number of currently active vblank irqs 370 */ 371 uint32_t active_vblank_irq_count; 372 373 /** 374 * @mst_encoders: 375 * 376 * fake encoders used for DP MST. 377 */ 378 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 379 bool force_timing_sync; 380 }; 381 382 enum dsc_clock_force_state { 383 DSC_CLK_FORCE_DEFAULT = 0, 384 DSC_CLK_FORCE_ENABLE, 385 DSC_CLK_FORCE_DISABLE, 386 }; 387 388 struct dsc_preferred_settings { 389 enum dsc_clock_force_state dsc_force_enable; 390 uint32_t dsc_num_slices_v; 391 uint32_t dsc_num_slices_h; 392 uint32_t dsc_bits_per_pixel; 393 }; 394 395 struct amdgpu_dm_connector { 396 397 struct drm_connector base; 398 uint32_t connector_id; 399 400 /* we need to mind the EDID between detect 401 and get modes due to analog/digital/tvencoder */ 402 struct edid *edid; 403 404 /* shared with amdgpu */ 405 struct amdgpu_hpd hpd; 406 407 /* number of modes generated from EDID at 'dc_sink' */ 408 int num_modes; 409 410 /* The 'old' sink - before an HPD. 411 * The 'current' sink is in dc_link->sink. */ 412 struct dc_sink *dc_sink; 413 struct dc_link *dc_link; 414 struct dc_sink *dc_em_sink; 415 416 /* DM only */ 417 struct drm_dp_mst_topology_mgr mst_mgr; 418 struct amdgpu_dm_dp_aux dm_dp_aux; 419 struct drm_dp_mst_port *port; 420 struct amdgpu_dm_connector *mst_port; 421 struct drm_dp_aux *dsc_aux; 422 423 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 424 struct amdgpu_i2c_adapter *i2c; 425 426 /* Monitor range limits */ 427 int min_vfreq ; 428 int max_vfreq ; 429 int pixel_clock_mhz; 430 431 /* Audio instance - protected by audio_lock. */ 432 int audio_inst; 433 434 struct mutex hpd_lock; 435 436 bool fake_enable; 437 #ifdef CONFIG_DEBUG_FS 438 uint32_t debugfs_dpcd_address; 439 uint32_t debugfs_dpcd_size; 440 #endif 441 bool force_yuv420_output; 442 struct dsc_preferred_settings dsc_settings; 443 }; 444 445 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 446 447 extern const struct amdgpu_ip_block_version dm_ip_block; 448 449 struct dm_plane_state { 450 struct drm_plane_state base; 451 struct dc_plane_state *dc_state; 452 }; 453 454 struct dm_crtc_state { 455 struct drm_crtc_state base; 456 struct dc_stream_state *stream; 457 458 bool cm_has_degamma; 459 bool cm_is_degamma_srgb; 460 461 int update_type; 462 int active_planes; 463 464 int crc_skip_count; 465 enum amdgpu_dm_pipe_crc_source crc_src; 466 467 bool freesync_timing_changed; 468 bool freesync_vrr_info_changed; 469 470 bool dsc_force_changed; 471 bool vrr_supported; 472 struct mod_freesync_config freesync_config; 473 struct dc_info_packet vrr_infopacket; 474 475 int abm_level; 476 }; 477 478 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 479 480 struct dm_atomic_state { 481 struct drm_private_state base; 482 483 struct dc_state *context; 484 }; 485 486 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 487 488 struct dm_connector_state { 489 struct drm_connector_state base; 490 491 enum amdgpu_rmx_type scaling; 492 uint8_t underscan_vborder; 493 uint8_t underscan_hborder; 494 bool underscan_enable; 495 bool freesync_capable; 496 #ifdef CONFIG_DRM_AMD_DC_HDCP 497 bool update_hdcp; 498 #endif 499 uint8_t abm_level; 500 int vcpi_slots; 501 uint64_t pbn; 502 }; 503 504 #define to_dm_connector_state(x)\ 505 container_of((x), struct dm_connector_state, base) 506 507 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 508 struct drm_connector_state * 509 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 510 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 511 struct drm_connector_state *state, 512 struct drm_property *property, 513 uint64_t val); 514 515 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 516 const struct drm_connector_state *state, 517 struct drm_property *property, 518 uint64_t *val); 519 520 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 521 522 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 523 struct amdgpu_dm_connector *aconnector, 524 int connector_type, 525 struct dc_link *link, 526 int link_index); 527 528 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 529 struct drm_display_mode *mode); 530 531 void dm_restore_drm_connector_state(struct drm_device *dev, 532 struct drm_connector *connector); 533 534 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 535 struct edid *edid); 536 537 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 538 539 #define MAX_COLOR_LUT_ENTRIES 4096 540 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 541 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 542 543 void amdgpu_dm_init_color_mod(void); 544 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 545 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 546 struct dc_plane_state *dc_plane_state); 547 548 void amdgpu_dm_update_connector_after_detect( 549 struct amdgpu_dm_connector *aconnector); 550 551 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 552 553 #endif /* __AMDGPU_DM_H__ */ 554