1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 #include "amdgpu_dm_crc.h" 54 55 /* Forward declarations */ 56 struct amdgpu_device; 57 struct drm_device; 58 struct amdgpu_dm_irq_handler_data; 59 struct dc; 60 struct amdgpu_bo; 61 struct dmub_srv; 62 63 struct common_irq_params { 64 struct amdgpu_device *adev; 65 enum dc_irq_source irq_src; 66 }; 67 68 /** 69 * struct irq_list_head - Linked-list for low context IRQ handlers. 70 * 71 * @head: The list_head within &struct handler_data 72 * @work: A work_struct containing the deferred handler work 73 */ 74 struct irq_list_head { 75 struct list_head head; 76 /* In case this interrupt needs post-processing, 'work' will be queued*/ 77 struct work_struct work; 78 }; 79 80 /** 81 * struct dm_compressor_info - Buffer info used by frame buffer compression 82 * @cpu_addr: MMIO cpu addr 83 * @bo_ptr: Pointer to the buffer object 84 * @gpu_addr: MMIO gpu addr 85 */ 86 struct dm_comressor_info { 87 void *cpu_addr; 88 struct amdgpu_bo *bo_ptr; 89 uint64_t gpu_addr; 90 }; 91 92 /** 93 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 94 * @min_input_signal: minimum possible input in range 0-255 95 * @max_input_signal: maximum possible input in range 0-255 96 * @caps_valid: true if these values are from the ACPI interface 97 */ 98 struct amdgpu_dm_backlight_caps { 99 int min_input_signal; 100 int max_input_signal; 101 bool caps_valid; 102 }; 103 104 /** 105 * struct amdgpu_display_manager - Central amdgpu display manager device 106 * 107 * @dc: Display Core control structure 108 * @adev: AMDGPU base driver structure 109 * @ddev: DRM base driver structure 110 * @display_indexes_num: Max number of display streams supported 111 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 112 * @backlight_dev: Backlight control device 113 * @backlight_link: Link on which to control backlight 114 * @backlight_caps: Capabilities of the backlight device 115 * @freesync_module: Module handling freesync calculations 116 * @fw_dmcu: Reference to DMCU firmware 117 * @dmcu_fw_version: Version of the DMCU firmware 118 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 119 * @cached_state: Caches device atomic state for suspend/resume 120 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 121 */ 122 struct amdgpu_display_manager { 123 124 struct dc *dc; 125 126 /** 127 * @dmub_srv: 128 * 129 * DMUB service, used for controlling the DMUB on hardware 130 * that supports it. The pointer to the dmub_srv will be 131 * NULL on hardware that does not support it. 132 */ 133 struct dmub_srv *dmub_srv; 134 135 /** 136 * @dmub_fw: 137 * 138 * DMUB firmware, required on hardware that has DMUB support. 139 */ 140 const struct firmware *dmub_fw; 141 142 /** 143 * @dmub_bo: 144 * 145 * Buffer object for the DMUB. 146 */ 147 struct amdgpu_bo *dmub_bo; 148 149 /** 150 * @dmub_bo_gpu_addr: 151 * 152 * GPU virtual address for the DMUB buffer object. 153 */ 154 u64 dmub_bo_gpu_addr; 155 156 /** 157 * @dmub_bo_cpu_addr: 158 * 159 * CPU address for the DMUB buffer object. 160 */ 161 void *dmub_bo_cpu_addr; 162 163 /** 164 * @dmcub_fw_version: 165 * 166 * DMCUB firmware version. 167 */ 168 uint32_t dmcub_fw_version; 169 170 /** 171 * @cgs_device: 172 * 173 * The Common Graphics Services device. It provides an interface for 174 * accessing registers. 175 */ 176 struct cgs_device *cgs_device; 177 178 struct amdgpu_device *adev; 179 struct drm_device *ddev; 180 u16 display_indexes_num; 181 182 /** 183 * @atomic_obj: 184 * 185 * In combination with &dm_atomic_state it helps manage 186 * global atomic state that doesn't map cleanly into existing 187 * drm resources, like &dc_context. 188 */ 189 struct drm_private_obj atomic_obj; 190 191 /** 192 * @dc_lock: 193 * 194 * Guards access to DC functions that can issue register write 195 * sequences. 196 */ 197 struct mutex dc_lock; 198 199 /** 200 * @audio_lock: 201 * 202 * Guards access to audio instance changes. 203 */ 204 struct mutex audio_lock; 205 206 /** 207 * @audio_component: 208 * 209 * Used to notify ELD changes to sound driver. 210 */ 211 struct drm_audio_component *audio_component; 212 213 /** 214 * @audio_registered: 215 * 216 * True if the audio component has been registered 217 * successfully, false otherwise. 218 */ 219 bool audio_registered; 220 221 /** 222 * @irq_handler_list_low_tab: 223 * 224 * Low priority IRQ handler table. 225 * 226 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 227 * source. Low priority IRQ handlers are deferred to a workqueue to be 228 * processed. Hence, they can sleep. 229 * 230 * Note that handlers are called in the same order as they were 231 * registered (FIFO). 232 */ 233 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 234 235 /** 236 * @irq_handler_list_high_tab: 237 * 238 * High priority IRQ handler table. 239 * 240 * It is a n*m table, same as &irq_handler_list_low_tab. However, 241 * handlers in this table are not deferred and are called immediately. 242 */ 243 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 244 245 /** 246 * @pflip_params: 247 * 248 * Page flip IRQ parameters, passed to registered handlers when 249 * triggered. 250 */ 251 struct common_irq_params 252 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 253 254 /** 255 * @vblank_params: 256 * 257 * Vertical blanking IRQ parameters, passed to registered handlers when 258 * triggered. 259 */ 260 struct common_irq_params 261 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 262 263 /** 264 * @vupdate_params: 265 * 266 * Vertical update IRQ parameters, passed to registered handlers when 267 * triggered. 268 */ 269 struct common_irq_params 270 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 271 272 spinlock_t irq_handler_list_table_lock; 273 274 struct backlight_device *backlight_dev; 275 276 const struct dc_link *backlight_link; 277 struct amdgpu_dm_backlight_caps backlight_caps; 278 279 struct mod_freesync *freesync_module; 280 #ifdef CONFIG_DRM_AMD_DC_HDCP 281 struct hdcp_workqueue *hdcp_workqueue; 282 #endif 283 284 struct drm_atomic_state *cached_state; 285 286 struct dm_comressor_info compressor; 287 288 const struct firmware *fw_dmcu; 289 uint32_t dmcu_fw_version; 290 /** 291 * @soc_bounding_box: 292 * 293 * gpu_info FW provided soc bounding box struct or 0 if not 294 * available in FW 295 */ 296 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 297 }; 298 299 struct amdgpu_dm_connector { 300 301 struct drm_connector base; 302 uint32_t connector_id; 303 304 /* we need to mind the EDID between detect 305 and get modes due to analog/digital/tvencoder */ 306 struct edid *edid; 307 308 /* shared with amdgpu */ 309 struct amdgpu_hpd hpd; 310 311 /* number of modes generated from EDID at 'dc_sink' */ 312 int num_modes; 313 314 /* The 'old' sink - before an HPD. 315 * The 'current' sink is in dc_link->sink. */ 316 struct dc_sink *dc_sink; 317 struct dc_link *dc_link; 318 struct dc_sink *dc_em_sink; 319 320 /* DM only */ 321 struct drm_dp_mst_topology_mgr mst_mgr; 322 struct amdgpu_dm_dp_aux dm_dp_aux; 323 struct drm_dp_mst_port *port; 324 struct amdgpu_dm_connector *mst_port; 325 struct amdgpu_encoder *mst_encoder; 326 327 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 328 struct amdgpu_i2c_adapter *i2c; 329 330 /* Monitor range limits */ 331 int min_vfreq ; 332 int max_vfreq ; 333 int pixel_clock_mhz; 334 335 /* Audio instance - protected by audio_lock. */ 336 int audio_inst; 337 338 struct mutex hpd_lock; 339 340 bool fake_enable; 341 #ifdef CONFIG_DEBUG_FS 342 uint32_t debugfs_dpcd_address; 343 uint32_t debugfs_dpcd_size; 344 #endif 345 bool force_yuv420_output; 346 }; 347 348 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 349 350 extern const struct amdgpu_ip_block_version dm_ip_block; 351 352 struct amdgpu_framebuffer; 353 struct amdgpu_display_manager; 354 struct dc_validation_set; 355 struct dc_plane_state; 356 357 struct dm_plane_state { 358 struct drm_plane_state base; 359 struct dc_plane_state *dc_state; 360 }; 361 362 struct dm_crtc_state { 363 struct drm_crtc_state base; 364 struct dc_stream_state *stream; 365 366 bool cm_has_degamma; 367 bool cm_is_degamma_srgb; 368 369 int update_type; 370 int active_planes; 371 bool interrupts_enabled; 372 373 int crc_skip_count; 374 enum amdgpu_dm_pipe_crc_source crc_src; 375 376 bool freesync_timing_changed; 377 bool freesync_vrr_info_changed; 378 379 bool vrr_supported; 380 struct mod_freesync_config freesync_config; 381 struct mod_vrr_params vrr_params; 382 struct dc_info_packet vrr_infopacket; 383 384 int abm_level; 385 }; 386 387 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 388 389 struct dm_atomic_state { 390 struct drm_private_state base; 391 392 struct dc_state *context; 393 }; 394 395 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 396 397 struct dm_connector_state { 398 struct drm_connector_state base; 399 400 enum amdgpu_rmx_type scaling; 401 uint8_t underscan_vborder; 402 uint8_t underscan_hborder; 403 bool underscan_enable; 404 bool freesync_capable; 405 uint8_t abm_level; 406 int vcpi_slots; 407 uint64_t pbn; 408 }; 409 410 #define to_dm_connector_state(x)\ 411 container_of((x), struct dm_connector_state, base) 412 413 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 414 struct drm_connector_state * 415 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 416 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 417 struct drm_connector_state *state, 418 struct drm_property *property, 419 uint64_t val); 420 421 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 422 const struct drm_connector_state *state, 423 struct drm_property *property, 424 uint64_t *val); 425 426 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 427 428 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 429 struct amdgpu_dm_connector *aconnector, 430 int connector_type, 431 struct dc_link *link, 432 int link_index); 433 434 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 435 struct drm_display_mode *mode); 436 437 void dm_restore_drm_connector_state(struct drm_device *dev, 438 struct drm_connector *connector); 439 440 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 441 struct edid *edid); 442 443 #define MAX_COLOR_LUT_ENTRIES 4096 444 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 445 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 446 447 void amdgpu_dm_init_color_mod(void); 448 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 449 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 450 struct dc_plane_state *dc_plane_state); 451 452 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 453 454 #endif /* __AMDGPU_DM_H__ */ 455