1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct dc; 62 struct amdgpu_bo; 63 struct dmub_srv; 64 struct dc_plane_state; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 atomic64_t previous_timestamp; 70 }; 71 72 /** 73 * struct dm_compressor_info - Buffer info used by frame buffer compression 74 * @cpu_addr: MMIO cpu addr 75 * @bo_ptr: Pointer to the buffer object 76 * @gpu_addr: MMIO gpu addr 77 */ 78 struct dm_compressor_info { 79 void *cpu_addr; 80 struct amdgpu_bo *bo_ptr; 81 uint64_t gpu_addr; 82 }; 83 84 /** 85 * struct vblank_workqueue - Works to be executed in a separate thread during vblank 86 * @mall_work: work for mall stutter 87 * @dm: amdgpu display manager device 88 * @otg_inst: otg instance of which vblank is being set 89 * @enable: true if enable vblank 90 */ 91 struct vblank_workqueue { 92 struct work_struct mall_work; 93 struct amdgpu_display_manager *dm; 94 int otg_inst; 95 bool enable; 96 }; 97 98 /** 99 * struct amdgpu_dm_backlight_caps - Information about backlight 100 * 101 * Describe the backlight support for ACPI or eDP AUX. 102 */ 103 struct amdgpu_dm_backlight_caps { 104 /** 105 * @ext_caps: Keep the data struct with all the information about the 106 * display support for HDR. 107 */ 108 union dpcd_sink_ext_caps *ext_caps; 109 /** 110 * @aux_min_input_signal: Min brightness value supported by the display 111 */ 112 u32 aux_min_input_signal; 113 /** 114 * @aux_max_input_signal: Max brightness value supported by the display 115 * in nits. 116 */ 117 u32 aux_max_input_signal; 118 /** 119 * @min_input_signal: minimum possible input in range 0-255. 120 */ 121 int min_input_signal; 122 /** 123 * @max_input_signal: maximum possible input in range 0-255. 124 */ 125 int max_input_signal; 126 /** 127 * @caps_valid: true if these values are from the ACPI interface. 128 */ 129 bool caps_valid; 130 /** 131 * @aux_support: Describes if the display supports AUX backlight. 132 */ 133 bool aux_support; 134 }; 135 136 /** 137 * struct dal_allocation - Tracks mapped FB memory for SMU communication 138 */ 139 struct dal_allocation { 140 struct list_head list; 141 struct amdgpu_bo *bo; 142 void *cpu_ptr; 143 u64 gpu_addr; 144 }; 145 146 /** 147 * struct amdgpu_display_manager - Central amdgpu display manager device 148 * 149 * @dc: Display Core control structure 150 * @adev: AMDGPU base driver structure 151 * @ddev: DRM base driver structure 152 * @display_indexes_num: Max number of display streams supported 153 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 154 * @backlight_dev: Backlight control device 155 * @backlight_link: Link on which to control backlight 156 * @backlight_caps: Capabilities of the backlight device 157 * @freesync_module: Module handling freesync calculations 158 * @hdcp_workqueue: AMDGPU content protection queue 159 * @fw_dmcu: Reference to DMCU firmware 160 * @dmcu_fw_version: Version of the DMCU firmware 161 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 162 * @cached_state: Caches device atomic state for suspend/resume 163 * @cached_dc_state: Cached state of content streams 164 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 165 * @force_timing_sync: set via debugfs. When set, indicates that all connected 166 * displays will be forced to synchronize. 167 */ 168 struct amdgpu_display_manager { 169 170 struct dc *dc; 171 172 /** 173 * @dmub_srv: 174 * 175 * DMUB service, used for controlling the DMUB on hardware 176 * that supports it. The pointer to the dmub_srv will be 177 * NULL on hardware that does not support it. 178 */ 179 struct dmub_srv *dmub_srv; 180 181 /** 182 * @dmub_fb_info: 183 * 184 * Framebuffer regions for the DMUB. 185 */ 186 struct dmub_srv_fb_info *dmub_fb_info; 187 188 /** 189 * @dmub_fw: 190 * 191 * DMUB firmware, required on hardware that has DMUB support. 192 */ 193 const struct firmware *dmub_fw; 194 195 /** 196 * @dmub_bo: 197 * 198 * Buffer object for the DMUB. 199 */ 200 struct amdgpu_bo *dmub_bo; 201 202 /** 203 * @dmub_bo_gpu_addr: 204 * 205 * GPU virtual address for the DMUB buffer object. 206 */ 207 u64 dmub_bo_gpu_addr; 208 209 /** 210 * @dmub_bo_cpu_addr: 211 * 212 * CPU address for the DMUB buffer object. 213 */ 214 void *dmub_bo_cpu_addr; 215 216 /** 217 * @dmcub_fw_version: 218 * 219 * DMCUB firmware version. 220 */ 221 uint32_t dmcub_fw_version; 222 223 /** 224 * @cgs_device: 225 * 226 * The Common Graphics Services device. It provides an interface for 227 * accessing registers. 228 */ 229 struct cgs_device *cgs_device; 230 231 struct amdgpu_device *adev; 232 struct drm_device *ddev; 233 u16 display_indexes_num; 234 235 /** 236 * @atomic_obj: 237 * 238 * In combination with &dm_atomic_state it helps manage 239 * global atomic state that doesn't map cleanly into existing 240 * drm resources, like &dc_context. 241 */ 242 struct drm_private_obj atomic_obj; 243 244 /** 245 * @dc_lock: 246 * 247 * Guards access to DC functions that can issue register write 248 * sequences. 249 */ 250 struct mutex dc_lock; 251 252 /** 253 * @audio_lock: 254 * 255 * Guards access to audio instance changes. 256 */ 257 struct mutex audio_lock; 258 259 #if defined(CONFIG_DRM_AMD_DC_DCN) 260 /** 261 * @vblank_lock: 262 * 263 * Guards access to deferred vblank work state. 264 */ 265 spinlock_t vblank_lock; 266 #endif 267 268 /** 269 * @audio_component: 270 * 271 * Used to notify ELD changes to sound driver. 272 */ 273 struct drm_audio_component *audio_component; 274 275 /** 276 * @audio_registered: 277 * 278 * True if the audio component has been registered 279 * successfully, false otherwise. 280 */ 281 bool audio_registered; 282 283 /** 284 * @irq_handler_list_low_tab: 285 * 286 * Low priority IRQ handler table. 287 * 288 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 289 * source. Low priority IRQ handlers are deferred to a workqueue to be 290 * processed. Hence, they can sleep. 291 * 292 * Note that handlers are called in the same order as they were 293 * registered (FIFO). 294 */ 295 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 296 297 /** 298 * @irq_handler_list_high_tab: 299 * 300 * High priority IRQ handler table. 301 * 302 * It is a n*m table, same as &irq_handler_list_low_tab. However, 303 * handlers in this table are not deferred and are called immediately. 304 */ 305 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 306 307 /** 308 * @pflip_params: 309 * 310 * Page flip IRQ parameters, passed to registered handlers when 311 * triggered. 312 */ 313 struct common_irq_params 314 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 315 316 /** 317 * @vblank_params: 318 * 319 * Vertical blanking IRQ parameters, passed to registered handlers when 320 * triggered. 321 */ 322 struct common_irq_params 323 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 324 325 /** 326 * @vline0_params: 327 * 328 * OTG vertical interrupt0 IRQ parameters, passed to registered 329 * handlers when triggered. 330 */ 331 struct common_irq_params 332 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 333 334 /** 335 * @vupdate_params: 336 * 337 * Vertical update IRQ parameters, passed to registered handlers when 338 * triggered. 339 */ 340 struct common_irq_params 341 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 342 343 /** 344 * @dmub_trace_params: 345 * 346 * DMUB trace event IRQ parameters, passed to registered handlers when 347 * triggered. 348 */ 349 struct common_irq_params 350 dmub_trace_params[1]; 351 352 spinlock_t irq_handler_list_table_lock; 353 354 struct backlight_device *backlight_dev; 355 356 const struct dc_link *backlight_link; 357 struct amdgpu_dm_backlight_caps backlight_caps; 358 359 struct mod_freesync *freesync_module; 360 #ifdef CONFIG_DRM_AMD_DC_HDCP 361 struct hdcp_workqueue *hdcp_workqueue; 362 #endif 363 364 #if defined(CONFIG_DRM_AMD_DC_DCN) 365 /** 366 * @vblank_workqueue: 367 * 368 * amdgpu workqueue during vblank 369 */ 370 struct vblank_workqueue *vblank_workqueue; 371 #endif 372 373 struct drm_atomic_state *cached_state; 374 struct dc_state *cached_dc_state; 375 376 struct dm_compressor_info compressor; 377 378 const struct firmware *fw_dmcu; 379 uint32_t dmcu_fw_version; 380 /** 381 * @soc_bounding_box: 382 * 383 * gpu_info FW provided soc bounding box struct or 0 if not 384 * available in FW 385 */ 386 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 387 388 #if defined(CONFIG_DRM_AMD_DC_DCN) 389 /** 390 * @active_vblank_irq_count: 391 * 392 * number of currently active vblank irqs 393 */ 394 uint32_t active_vblank_irq_count; 395 #endif 396 397 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 398 /** 399 * @crc_rd_wrk: 400 * 401 * Work to be executed in a separate thread to communicate with PSP. 402 */ 403 struct crc_rd_work *crc_rd_wrk; 404 #endif 405 406 /** 407 * @mst_encoders: 408 * 409 * fake encoders used for DP MST. 410 */ 411 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 412 bool force_timing_sync; 413 bool disable_hpd_irq; 414 bool dmcub_trace_event_en; 415 /** 416 * @da_list: 417 * 418 * DAL fb memory allocation list, for communication with SMU. 419 */ 420 struct list_head da_list; 421 }; 422 423 enum dsc_clock_force_state { 424 DSC_CLK_FORCE_DEFAULT = 0, 425 DSC_CLK_FORCE_ENABLE, 426 DSC_CLK_FORCE_DISABLE, 427 }; 428 429 struct dsc_preferred_settings { 430 enum dsc_clock_force_state dsc_force_enable; 431 uint32_t dsc_num_slices_v; 432 uint32_t dsc_num_slices_h; 433 uint32_t dsc_bits_per_pixel; 434 }; 435 436 struct amdgpu_dm_connector { 437 438 struct drm_connector base; 439 uint32_t connector_id; 440 441 /* we need to mind the EDID between detect 442 and get modes due to analog/digital/tvencoder */ 443 struct edid *edid; 444 445 /* shared with amdgpu */ 446 struct amdgpu_hpd hpd; 447 448 /* number of modes generated from EDID at 'dc_sink' */ 449 int num_modes; 450 451 /* The 'old' sink - before an HPD. 452 * The 'current' sink is in dc_link->sink. */ 453 struct dc_sink *dc_sink; 454 struct dc_link *dc_link; 455 struct dc_sink *dc_em_sink; 456 457 /* DM only */ 458 struct drm_dp_mst_topology_mgr mst_mgr; 459 struct amdgpu_dm_dp_aux dm_dp_aux; 460 struct drm_dp_mst_port *port; 461 struct amdgpu_dm_connector *mst_port; 462 struct drm_dp_aux *dsc_aux; 463 464 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 465 struct amdgpu_i2c_adapter *i2c; 466 467 /* Monitor range limits */ 468 int min_vfreq ; 469 int max_vfreq ; 470 int pixel_clock_mhz; 471 472 /* Audio instance - protected by audio_lock. */ 473 int audio_inst; 474 475 struct mutex hpd_lock; 476 477 bool fake_enable; 478 #ifdef CONFIG_DEBUG_FS 479 uint32_t debugfs_dpcd_address; 480 uint32_t debugfs_dpcd_size; 481 #endif 482 bool force_yuv420_output; 483 struct dsc_preferred_settings dsc_settings; 484 /* Cached display modes */ 485 struct drm_display_mode freesync_vid_base; 486 }; 487 488 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 489 490 extern const struct amdgpu_ip_block_version dm_ip_block; 491 492 struct dm_plane_state { 493 struct drm_plane_state base; 494 struct dc_plane_state *dc_state; 495 }; 496 497 struct dm_crtc_state { 498 struct drm_crtc_state base; 499 struct dc_stream_state *stream; 500 501 bool cm_has_degamma; 502 bool cm_is_degamma_srgb; 503 504 int update_type; 505 int active_planes; 506 507 int crc_skip_count; 508 509 bool freesync_timing_changed; 510 bool freesync_vrr_info_changed; 511 512 bool dsc_force_changed; 513 bool vrr_supported; 514 struct mod_freesync_config freesync_config; 515 struct dc_info_packet vrr_infopacket; 516 517 int abm_level; 518 }; 519 520 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 521 522 struct dm_atomic_state { 523 struct drm_private_state base; 524 525 struct dc_state *context; 526 }; 527 528 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 529 530 struct dm_connector_state { 531 struct drm_connector_state base; 532 533 enum amdgpu_rmx_type scaling; 534 uint8_t underscan_vborder; 535 uint8_t underscan_hborder; 536 bool underscan_enable; 537 bool freesync_capable; 538 #ifdef CONFIG_DRM_AMD_DC_HDCP 539 bool update_hdcp; 540 #endif 541 uint8_t abm_level; 542 int vcpi_slots; 543 uint64_t pbn; 544 }; 545 546 struct amdgpu_hdmi_vsdb_info { 547 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 548 bool freesync_supported; /* FreeSync Supported */ 549 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 550 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 551 }; 552 553 554 #define to_dm_connector_state(x)\ 555 container_of((x), struct dm_connector_state, base) 556 557 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 558 struct drm_connector_state * 559 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 560 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 561 struct drm_connector_state *state, 562 struct drm_property *property, 563 uint64_t val); 564 565 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 566 const struct drm_connector_state *state, 567 struct drm_property *property, 568 uint64_t *val); 569 570 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 571 572 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 573 struct amdgpu_dm_connector *aconnector, 574 int connector_type, 575 struct dc_link *link, 576 int link_index); 577 578 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 579 struct drm_display_mode *mode); 580 581 void dm_restore_drm_connector_state(struct drm_device *dev, 582 struct drm_connector *connector); 583 584 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 585 struct edid *edid); 586 587 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 588 589 #define MAX_COLOR_LUT_ENTRIES 4096 590 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 591 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 592 593 void amdgpu_dm_init_color_mod(void); 594 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 595 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 596 struct dc_plane_state *dc_plane_state); 597 598 void amdgpu_dm_update_connector_after_detect( 599 struct amdgpu_dm_connector *aconnector); 600 601 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 602 603 #endif /* __AMDGPU_DM_H__ */ 604